Unified Coverage Report :: Module

Line Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
TOTAL		122	122	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	480	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	573	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
ALWAYS	576	6	6	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	590	1	1	100.00
CONT_ASSIGN	593	1	1	100.00
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	612	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	634	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
ALWAYS	645	6	6	100.00
CONT_ASSIGN	656	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	690	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	715	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
480	1	1
486	1	1
490	1	1
494	1	1
511	1	1
515	1	1
518	1	1
519	1	1
573	1	1
574	1	1
576	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
			MISSING_ELSE
586	1	1
590	1	1
593	1	1
600	1	1
604	1	1
612	1	1
629	1	1
634	1	1
639	4	4
645	1	1
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
			MISSING_ELSE
656	1	1
668	1	1
669	1	1
690	1	1
702	1	1
705	1	1
709	1	1
712	1	1
715	1	1

Cond Coverage for Module : flash_phy_rd

	Total	Covered	Percent
Conditions	443	407	91.87
Logical	443	407	91.87
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       139
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       139
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       139
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       140
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       140
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       140
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       140
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       145
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T8,T37,T27
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T220
1	1	1	Covered	T8,T37,T27

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       145
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T8,T37,T72
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T220
1	1	1	Covered	T8,T37,T72

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       145
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T8,T37,T72
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T220
1	1	1	Covered	T8,T37,T72

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       145
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T8,T37,T72
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Not Covered
1	1	1	Covered	T8,T37,T72

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       166
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       166
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       166
 EXPRESSION (req_o & no_match)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T4
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T2,T45,T193
1	1	1	0	1	1	1	Covered	T1,T2,T4
1	1	1	1	0	1	1	Covered	T8,T37,T72
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T41,T211,T221
1	1	1	1	1	1	1	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T4
1	0	1	1	1	1	1	Covered	T22,T222
1	1	0	1	1	1	1	Covered	T2,T45,T193
1	1	1	0	1	1	1	Covered	T1,T2,T4
1	1	1	1	0	1	1	Covered	T8,T37,T73
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T41,T118,T211
1	1	1	1	1	1	1	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T4
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T2,T45,T193
1	1	1	0	1	1	1	Covered	T1,T2,T4
1	1	1	1	0	1	1	Covered	T37,T72,T73
1	1	1	1	1	0	1	Covered	T223,T224
1	1	1	1	1	1	0	Covered	T211,T212,T225
1	1	1	1	1	1	1	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T4
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T2,T45,T193
1	1	1	0	1	1	1	Covered	T1,T2,T4
1	1	1	1	0	1	1	Covered	T8,T72,T73
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T19,T41,T118
1	1	1	1	1	1	1	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T41,T211,T221
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T41,T118,T211
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T211,T212,T225
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T19,T41,T118
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T70,T41,T211
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T8,T70,T73
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T8,T19,T70
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T8,T19,T70
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       221
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T45,T193,T88
0	1	0	Covered	T2,T31,T75
1	0	0	Covered	T1,T4,T22

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T31,T75

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T45,T193,T88

 LINE       221
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T45,T193,T88
0	1	0	Covered	T2,T31,T75
1	0	0	Covered	T1,T4,T22

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T31,T75

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T45,T193,T88

 LINE       221
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T45,T193,T88
0	1	0	Covered	T2,T31,T75
1	0	0	Covered	T1,T4,T22

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T31,T75

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T45,T193,T88

 LINE       221
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T45,T193,T88
0	1	0	Covered	T2,T31,T75
1	0	0	Covered	T1,T4,T22

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T31,T75

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T45,T193,T88

 LINE       231
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T70
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       238
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       238
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       238
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T37
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       290
 EXPRESSION (req_o & ack_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T37,T70
1	1	Covered	T1,T2,T3

 LINE       291
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       301
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       304
 EXPRESSION (req_i && rdy_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T17,T7
1	1	Covered	T1,T2,T3

 LINE       307
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       376
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       381
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T19
1	0	Covered	T64,T65,T66
1	1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       398
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T17,T7,T8
1	1	1	1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T7,T8,T19
1	1	1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       406
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	Not Covered
1	1	0	1	1	1	Covered	T6,T7,T8
1	1	1	0	1	1	Covered	T64,T65,T66
1	1	1	1	0	1	Covered	T1,T2,T4
1	1	1	1	1	0	Covered	T8,T37,T70
1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       406
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T19,T88

 LINE       431
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T20

 LINE       441
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T37,T27

 LINE       450
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T36,T37

 LINE       450
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T36,T37
1	0	Covered	T8,T37,T27

 LINE       455
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T36,T37

 LINE       480
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T67
1	0	Covered	T64,T65,T66
1	1	Covered	T1,T2,T3

 LINE       486
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : fifo_data_valid)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       486
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       490
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T88,T150,T226
1	1	1	Covered	T1,T2,T3

 LINE       494
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T7,T41,T118
1	1	1	Covered	T1,T2,T4

 LINE       511
 EXPRESSION (hint_forward & fifo_data_valid)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       515
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       518
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       519
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       573
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T8,T37,T70
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T3

 LINE       574
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T21,T31,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       590
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T8,T37,T70
1	1	0	Covered	T88,T150,T226
1	1	1	Covered	T1,T2,T3

 LINE       600
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       600
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       604
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       604
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       612
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       612
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       629
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       629
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       629
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       634
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T67
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       634
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       634
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T4
1	1	1	0	Covered	T1,T2,T4
1	1	1	1	Covered	T1,T2,T4

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T4
1	1	1	0	Covered	T1,T2,T4
1	1	1	1	Covered	T1,T2,T4

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T4
1	1	1	0	Covered	T1,T2,T4
1	1	1	1	Covered	T1,T2,T4

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T4
1	1	1	0	Covered	T1,T2,T4
1	1	1	1	Covered	T1,T2,T4

 LINE       650
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T220
1	0	Not Covered

 LINE       656
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       669
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T13,T8

 LINE       690
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       690
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       702
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       705
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T12,T13,T8

 LINE       705
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T13,T8

 LINE       705
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T8,T37,T72

 LINE       705
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T220

 LINE       709
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T13,T8

Branch Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
Branches		40	40	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	486	2	2	100.00
TERNARY	600	3	3	100.00
TERNARY	604	3	3	100.00
TERNARY	629	3	3	100.00
TERNARY	656	2	2	100.00
TERNARY	690	2	2	100.00
TERNARY	669	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	576	4	4	100.00
IF	648	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	231	(no_match) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	301	((|alloc)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ?

Branches:

-1-	Status	Tests
1	Covered	T8,T36,T37
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	486	(hint_descram) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	600	(forward) ? 
-2-:	600	(hint_descram) ?

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	604	(forward) ? 
-2-:	604	((~hint_forward)) ?

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	629	(forward) ? 
-2-:	629	(((~hint_forward) & fifo_data_ready)) ?

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	656	((|buf_rsp_match)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	690	(rsp_fifo_rdata.intg_ecc_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	669	(data_err_o) ?

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T8
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	576	if ((!rst_ni))
-2-:	578	if (calc_req_start)
-3-:	580	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	648	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

Assert Coverage for Module : flash_phy_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	826577232	1622817	0	0
ExclusiveOps_A	826577232	824868744	0	0
ExclusiveProgHazard_A	826577232	824868744	0	0
ExclusiveState_A	826577232	824868744	0	0
ForwardCheck_A	826577232	4174649	0	0
IdleCheck_A	826577232	104394712	0	0
MaxBufs_A	2120	2120	0	0
OneHotAlloc_A	826577232	824868744	0	0
OneHotMatch_A	826577232	824868744	0	0
OneHotRspMatch_A	826577232	824868744	0	0
OneHotUpdate_A	826577232	824868744	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes
Total	826577232	1622817
T1	1634202	1106
T2	19086	104
T3	7274	0
T4	1038514	420
T5	1258	1
T6	1585134	5093
T7	0	7998
T8	0	2447
T12	2484	0
T13	2308	0
T17	25136	120
T18	8226	0
T21	0	256
T26	0	112
T31	0	768
T36	0	72
T44	0	5
T55	0	6
T74	0	3

ExclusiveOps_A

Name	Attempts	Real Successes
Total	826577232	824868744
T1	1634202	1634022
T2	19086	18722
T3	7274	6000
T4	1038514	1038348
T5	1258	1136
T6	1585134	1584852
T12	2484	2076
T13	2308	1844
T17	25136	24848
T18	8226	6982

ExclusiveProgHazard_A

Name	Attempts	Real Successes
Total	826577232	824868744
T1	1634202	1634022
T2	19086	18722
T3	7274	6000
T4	1038514	1038348
T5	1258	1136
T6	1585134	1584852
T12	2484	2076
T13	2308	1844
T17	25136	24848
T18	8226	6982

ExclusiveState_A

Name	Attempts	Real Successes
Total	826577232	824868744
T1	1634202	1634022
T2	19086	18722
T3	7274	6000
T4	1038514	1038348
T5	1258	1136
T6	1585134	1584852
T12	2484	2076
T13	2308	1844
T17	25136	24848
T18	8226	6982

ForwardCheck_A

Name	Attempts	Real Successes
Total	826577232	4174649
T1	1634202	1122
T2	19086	110
T3	7274	0
T4	1038514	486
T5	1258	0
T6	1585134	22759
T7	0	19743
T12	2484	0
T13	2308	0
T17	25136	0
T18	8226	0
T19	0	19285
T27	0	13
T31	0	544
T35	0	25375
T44	0	6
T72	0	20416
T181	0	32
T227	0	4

IdleCheck_A

Name	Attempts	Real Successes
Total	826577232	104394712
T1	1634202	3478
T2	19086	652
T3	7274	641
T4	1038514	1520
T5	1258	137
T6	1585134	1167602
T7	0	28106
T8	0	116996
T12	2484	268
T13	2308	268
T17	25136	936
T18	8226	896
T26	0	660
T44	0	17
T55	0	34

MaxBufs_A

Name	Attempts	Real Successes
Total	2120	2120
T1	2	2
T2	2	2
T3	2	2
T4	2	2
T5	2	2
T6	2	2
T12	2	2
T13	2	2
T17	2	2
T18	2	2

OneHotAlloc_A

Name	Attempts	Real Successes
Total	826577232	824868744
T1	1634202	1634022
T2	19086	18722
T3	7274	6000
T4	1038514	1038348
T5	1258	1136
T6	1585134	1584852
T12	2484	2076
T13	2308	1844
T17	25136	24848
T18	8226	6982

OneHotMatch_A

Name	Attempts	Real Successes
Total	826577232	824868744
T1	1634202	1634022
T2	19086	18722
T3	7274	6000
T4	1038514	1038348
T5	1258	1136
T6	1585134	1584852
T12	2484	2076
T13	2308	1844
T17	25136	24848
T18	8226	6982

OneHotRspMatch_A

Name	Attempts	Real Successes
Total	826577232	824868744
T1	1634202	1634022
T2	19086	18722
T3	7274	6000
T4	1038514	1038348
T5	1258	1136
T6	1585134	1584852
T12	2484	2076
T13	2308	1844
T17	25136	24848
T18	8226	6982

OneHotUpdate_A

Name	Attempts	Real Successes
Total	826577232	824868744
T1	1634202	1634022
T2	19086	18722
T3	7274	6000
T4	1038514	1038348
T5	1258	1136
T6	1585134	1584852
T12	2484	2076
T13	2308	1844
T17	25136	24848
T18	8226	6982

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		122	122	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	480	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	573	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
ALWAYS	576	6	6	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	590	1	1	100.00
CONT_ASSIGN	593	1	1	100.00
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	612	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	634	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
ALWAYS	645	6	6	100.00
CONT_ASSIGN	656	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	690	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	715	1	1	100.00

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
480	1	1
486	1	1
490	1	1
494	1	1
511	1	1
515	1	1
518	1	1
519	1	1
573	1	1
574	1	1
576	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
			MISSING_ELSE
586	1	1
590	1	1
593	1	1
600	1	1
604	1	1
612	1	1
629	1	1
634	1	1
639	4	4
645	1	1
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
			MISSING_ELSE
656	1	1
668	1	1
669	1	1
690	1	1
702	1	1
705	1	1
709	1	1
712	1	1
715	1	1

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Covered	Percent
Conditions	443	401	90.52
Logical	443	401	90.52
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       139
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       139
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       139
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       140
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       140
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       140
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       140
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       145
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T8,T37,T27
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Not Covered
1	1	1	Covered	T8,T37,T27

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       145
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T8,T37,T72
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Not Covered
1	1	1	Covered	T8,T37,T72

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       145
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T8,T37,T72
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Not Covered
1	1	1	Covered	T8,T37,T72

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       145
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T8,T37,T72
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Not Covered
1	1	1	Covered	T8,T37,T72

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       166
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       166
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       166
 EXPRESSION (req_o & no_match)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       185
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T4
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T2,T28,T228
1	1	1	0	1	1	1	Covered	T1,T2,T4
1	1	1	1	0	1	1	Covered	T8,T37,T72
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T41,T211,T221
1	1	1	1	1	1	1	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T4
1	0	1	1	1	1	1	Covered	T222
1	1	0	1	1	1	1	Covered	T2,T228,T226
1	1	1	0	1	1	1	Covered	T1,T2,T4
1	1	1	1	0	1	1	Covered	T8,T73,T229
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T118,T230,T231
1	1	1	1	1	1	1	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T4
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T2,T38,T226
1	1	1	0	1	1	1	Covered	T1,T2,T4
1	1	1	1	0	1	1	Covered	T72,T232,T220
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T212,T225,T230
1	1	1	1	1	1	1	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T4
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T2,T233,T226
1	1	1	0	1	1	1	Covered	T1,T2,T4
1	1	1	1	0	1	1	Covered	T8,T72,T234
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T41,T225,T235
1	1	1	1	1	1	1	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       195
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T41,T211,T221
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T118,T230,T231
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T212,T225,T230
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T41,T225,T235
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T70,T41,T211
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T8,T70,T73
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T8,T19,T70
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T8,T41,T211
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       221
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T24
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T22

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T24,T22,T84
0	1	0	Covered	T2,T24,T22
1	0	0	Covered	T4,T22,T23

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T24,T22

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T24
1	1	Covered	T24,T22,T84

 LINE       221
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T24
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T22

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T24,T22,T84
0	1	0	Covered	T2,T24,T22
1	0	0	Covered	T4,T22,T23

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T24,T22

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T24
1	1	Covered	T24,T22,T84

 LINE       221
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T24
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T22

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T24,T22,T84
0	1	0	Covered	T2,T24,T22
1	0	0	Covered	T4,T22,T23

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T24,T22

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T24
1	1	Covered	T24,T22,T84

 LINE       221
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T24
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T22

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T24,T22,T84
0	1	0	Covered	T2,T24,T22
1	0	0	Covered	T4,T22,T23

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T24,T22

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T24
1	1	Covered	T24,T22,T84

 LINE       231
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T70
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       238
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T70
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       238
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       238
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T37
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       290
 EXPRESSION (req_o & ack_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T37,T70
1	1	Covered	T1,T2,T4

 LINE       291
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       301
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       304
 EXPRESSION (req_i && rdy_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T17,T7
1	1	Covered	T1,T2,T4

 LINE       307
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       376
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       381
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T8,T19,T37
1	0	Covered	T64,T65,T79
1	1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       398
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T17,T8,T26
1	1	1	1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T8,T19,T37
1	1	1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T7

 LINE       406
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	Not Covered
1	1	0	1	1	1	Covered	T6,T7,T8
1	1	1	0	1	1	Covered	T65,T79,T99
1	1	1	1	0	1	Covered	T1,T2,T4
1	1	1	1	1	0	Covered	T8,T37,T70
1	1	1	1	1	1	Covered	T1,T2,T4

 LINE       406
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T7

 LINE       427
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T17,T7

 LINE       431
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T19,T175

 LINE       431
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T8

 LINE       441
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T17,T7
1	1	Covered	T8,T37,T27

 LINE       450
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T37,T27

 LINE       450
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T37,T70
1	0	Covered	T8,T37,T27

 LINE       455
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T17,T7
1	1	Covered	T8,T37,T70

 LINE       480
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T67
1	0	Covered	T64,T65,T79
1	1	Covered	T1,T2,T3

 LINE       486
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : fifo_data_valid)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T7

 LINE       486
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T17,T7
1	1	Covered	T2,T17,T7

 LINE       490
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T17,T7
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T64,T68,T65
1	1	1	Covered	T2,T17,T7

 LINE       494
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T17,T7
1	1	0	Covered	T41,T118,T236
1	1	1	Covered	T1,T2,T4

 LINE       511
 EXPRESSION (hint_forward & fifo_data_valid)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T7
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       515
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T17,T7

 LINE       518
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T17,T7

 LINE       519
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T17,T7
1	1	Covered	T1,T2,T4

 LINE       573
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T8,T37,T70
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T2,T17,T7

 LINE       574
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T70
1	0	Covered	T2,T17,T7
1	1	Covered	T2,T17,T7

 LINE       590
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T8,T37,T70
1	1	0	Covered	T64,T65,T66
1	1	1	Covered	T2,T17,T7

 LINE       600
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       600
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T7

 LINE       604
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       604
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       612
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T17,T7
1	0	Covered	T1,T2,T4

 LINE       612
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T17,T7

 LINE       629
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       629
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T7

 LINE       629
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T17,T7

 LINE       634
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T67
1	0	1	Covered	T24,T22,T84
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       634
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       634
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T4
1	1	1	0	Covered	T1,T2,T4
1	1	1	1	Covered	T1,T2,T4

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T4
1	1	1	0	Covered	T1,T2,T4
1	1	1	1	Covered	T1,T2,T4

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T4
1	1	1	0	Covered	T1,T2,T4
1	1	1	1	Covered	T1,T2,T4

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T4
1	1	1	0	Covered	T1,T2,T4
1	1	1	1	Covered	T1,T2,T4

 LINE       650
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Not Covered
1	0	Not Covered

 LINE       656
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       669
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T37,T27

 LINE       690
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T7

 LINE       690
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T2,T17,T7
1	Covered	T2,T17,T7

 LINE       702
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       705
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T8,T37,T27

 LINE       705
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T8,T37,T27

 LINE       705
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T2,T17,T7
1	0	0	Covered	T8,T37,T72

 LINE       705
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Not Covered

 LINE       709
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T8,T37,T27

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		40	40	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	486	2	2	100.00
TERNARY	600	3	3	100.00
TERNARY	604	3	3	100.00
TERNARY	629	3	3	100.00
TERNARY	656	2	2	100.00
TERNARY	690	2	2	100.00
TERNARY	669	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	576	4	4	100.00
IF	648	2	2	100.00



	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	231	(no_match) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	301	((|alloc)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ?

Branches:

-1-	Status	Tests
1	Covered	T8,T37,T27
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	486	(hint_descram) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T17,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	600	(forward) ? 
-2-:	600	(hint_descram) ?

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T2,T17,T7
0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	604	(forward) ? 
-2-:	604	((~hint_forward)) ?

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	629	(forward) ? 
-2-:	629	(((~hint_forward) & fifo_data_ready)) ?

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T2,T17,T7
0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	656	((|buf_rsp_match)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	690	(rsp_fifo_rdata.intg_ecc_en) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T17,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	669	(data_err_o) ?

Branches:

-1-	Status	Tests
1	Covered	T8,T37,T27
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	576	if ((!rst_ni))
-2-:	578	if (calc_req_start)
-3-:	580	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T17,T7
0	0	1	Covered	T2,T17,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	648	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	413288616	650341	0	0
ExclusiveOps_A	413288616	412434372	0	0
ExclusiveProgHazard_A	413288616	412434372	0	0
ExclusiveState_A	413288616	412434372	0	0
ForwardCheck_A	413288616	1806926	0	0
IdleCheck_A	413288616	49883473	0	0
MaxBufs_A	1060	1060	0	0
OneHotAlloc_A	413288616	412434372	0	0
OneHotMatch_A	413288616	412434372	0	0
OneHotRspMatch_A	413288616	412434372	0	0
OneHotUpdate_A	413288616	412434372	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes
Total	413288616	650341
T1	817101	813
T2	9543	104
T3	3637	0
T4	519257	171
T5	629	0
T6	792567	2664
T7	0	3166
T8	0	727
T12	1242	0
T13	1154	0
T17	12568	120
T18	4113	0
T26	0	112
T44	0	5
T55	0	6

ExclusiveOps_A

Name	Attempts	Real Successes
Total	413288616	412434372
T1	817101	817011
T2	9543	9361
T3	3637	3000
T4	519257	519174
T5	629	568
T6	792567	792426
T12	1242	1038
T13	1154	922
T17	12568	12424
T18	4113	3491

ExclusiveProgHazard_A

Name	Attempts	Real Successes
Total	413288616	412434372
T1	817101	817011
T2	9543	9361
T3	3637	3000
T4	519257	519174
T5	629	568
T6	792567	792426
T12	1242	1038
T13	1154	922
T17	12568	12424
T18	4113	3491

ExclusiveState_A

Name	Attempts	Real Successes
Total	413288616	412434372
T1	817101	817011
T2	9543	9361
T3	3637	3000
T4	519257	519174
T5	629	568
T6	792567	792426
T12	1242	1038
T13	1154	922
T17	12568	12424
T18	4113	3491

ForwardCheck_A

Name	Attempts	Real Successes
Total	413288616	1806926
T1	817101	823
T2	9543	110
T3	3637	0
T4	519257	199
T5	629	0
T6	792567	10609
T7	0	11212
T12	1242	0
T13	1154	0
T17	12568	0
T18	4113	0
T19	0	9208
T27	0	13
T35	0	12531
T44	0	6
T72	0	10079

IdleCheck_A

Name	Attempts	Real Successes
Total	413288616	49883473
T1	817101	2459
T2	9543	396
T3	3637	0
T4	519257	569
T5	629	0
T6	792567	543723
T7	0	28106
T8	0	116996
T12	1242	0
T13	1154	0
T17	12568	680
T18	4113	0
T26	0	660
T44	0	17
T55	0	34

MaxBufs_A

Name	Attempts	Real Successes
Total	1060	1060
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T12	1	1
T13	1	1
T17	1	1
T18	1	1

OneHotAlloc_A

Name	Attempts	Real Successes
Total	413288616	412434372
T1	817101	817011
T2	9543	9361
T3	3637	3000
T4	519257	519174
T5	629	568
T6	792567	792426
T12	1242	1038
T13	1154	922
T17	12568	12424
T18	4113	3491

OneHotMatch_A

Name	Attempts	Real Successes
Total	413288616	412434372
T1	817101	817011
T2	9543	9361
T3	3637	3000
T4	519257	519174
T5	629	568
T6	792567	792426
T12	1242	1038
T13	1154	922
T17	12568	12424
T18	4113	3491

OneHotRspMatch_A

Name	Attempts	Real Successes
Total	413288616	412434372
T1	817101	817011
T2	9543	9361
T3	3637	3000
T4	519257	519174
T5	629	568
T6	792567	792426
T12	1242	1038
T13	1154	922
T17	12568	12424
T18	4113	3491

OneHotUpdate_A

Name	Attempts	Real Successes
Total	413288616	412434372
T1	817101	817011
T2	9543	9361
T3	3637	3000
T4	519257	519174
T5	629	568
T6	792567	792426
T12	1242	1038
T13	1154	922
T17	12568	12424
T18	4113	3491

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		122	122	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	480	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	573	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
ALWAYS	576	6	6	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	590	1	1	100.00
CONT_ASSIGN	593	1	1	100.00
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	612	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	634	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
ALWAYS	645	6	6	100.00
CONT_ASSIGN	656	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	690	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	715	1	1	100.00

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
480	1	1
486	1	1
490	1	1
494	1	1
511	1	1
515	1	1
518	1	1
519	1	1
573	1	1
574	1	1
576	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
			MISSING_ELSE
586	1	1
590	1	1
593	1	1
600	1	1
604	1	1
612	1	1
629	1	1
634	1	1
639	4	4
645	1	1
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
			MISSING_ELSE
656	1	1
668	1	1
669	1	1
690	1	1
702	1	1
705	1	1
709	1	1
712	1	1
715	1	1

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Covered	Percent
Conditions	443	407	91.87
Logical	443	407	91.87
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       139
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       139
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       139
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       140
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       140
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       140
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       140
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       145
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T8,T37,T72
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T220
1	1	1	Covered	T8,T37,T72

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       145
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T8,T37,T72
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T220
1	1	1	Covered	T8,T37,T72

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       145
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T6
0	1	Covered	T8,T37,T72
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T6
1	1	0	Covered	T220
1	1	1	Covered	T8,T37,T72

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       145
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T6
0	1	Covered	T8,T37,T72
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T6
1	1	0	Not Covered
1	1	1	Covered	T8,T37,T72

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       153
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       153
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       153
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

 LINE       166
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T1,T2,T3

 LINE       166
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       166
 EXPRESSION (req_o & no_match)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T4,T5
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T45,T193,T174
1	1	1	0	1	1	1	Covered	T1,T4,T5
1	1	1	1	0	1	1	Covered	T8,T37,T72
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T212,T235,T236
1	1	1	1	1	1	1	Covered	T1,T4,T5

 LINE       195
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       195
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T4,T5
1	0	1	1	1	1	1	Covered	T22
1	1	0	1	1	1	1	Covered	T45,T193,T174
1	1	1	0	1	1	1	Covered	T1,T4,T6
1	1	1	1	0	1	1	Covered	T37,T73,T118
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T41,T118,T211
1	1	1	1	1	1	1	Covered	T1,T4,T6

 LINE       195
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       195
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T4,T6
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T45,T193,T174
1	1	1	0	1	1	1	Covered	T1,T4,T6
1	1	1	1	0	1	1	Covered	T37,T72,T73
1	1	1	1	1	0	1	Covered	T223,T224
1	1	1	1	1	1	0	Covered	T211,T213,T231
1	1	1	1	1	1	1	Covered	T1,T4,T6

 LINE       195
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T4,T6

 LINE       195
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T4,T6
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T45,T193,T174
1	1	1	0	1	1	1	Covered	T1,T4,T6
1	1	1	1	0	1	1	Covered	T72,T73,T118
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T19,T118,T212
1	1	1	1	1	1	1	Covered	T1,T4,T6

 LINE       195
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T4,T6

 LINE       195
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T212,T235,T236
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T41,T118,T211
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T211,T213,T231
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T19,T118,T212
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T70,T41,T33
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T70,T73,T41
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T19,T70,T73
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T19,T70,T175
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       221
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T31
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T31

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T45,T193,T88
0	1	0	Covered	T31,T75,T45
1	0	0	Covered	T1,T4,T23

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T20
1	1	Covered	T31,T75,T45

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T45,T193,T88

 LINE       221
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T31
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T31

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T45,T193,T88
0	1	0	Covered	T31,T75,T45
1	0	0	Covered	T1,T4,T23

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T20
1	1	Covered	T31,T75,T45

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T45,T193,T88

 LINE       221
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T31
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T4,T31

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T45,T193,T88
0	1	0	Covered	T31,T75,T45
1	0	0	Covered	T1,T4,T23

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T20
1	1	Covered	T31,T75,T45

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T45,T193,T88

 LINE       221
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T31
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T4,T31

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T45,T193,T88
0	1	0	Covered	T31,T75,T45
1	0	0	Covered	T1,T4,T23

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T20
1	1	Covered	T31,T75,T45

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T45,T193,T88

 LINE       231
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T70
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       238
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       238
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T70
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

 LINE       238
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T70
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

 LINE       290
 EXPRESSION (req_o & ack_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T37,T70
1	1	Covered	T1,T2,T3

 LINE       291
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       301
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       304
 EXPRESSION (req_i && rdy_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

 LINE       307
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       376
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       381
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T19
1	0	Covered	T64,T65,T66
1	1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       398
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T7,T8,T37
1	1	1	1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T7,T8,T19
1	1	1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       406
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	Not Covered
1	1	0	1	1	1	Covered	T6,T7,T8
1	1	1	0	1	1	Covered	T64,T65,T66
1	1	1	1	0	1	Covered	T1,T4,T5
1	1	1	1	1	0	Covered	T8,T37,T70
1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       406
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T19,T88

 LINE       431
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T20

 LINE       441
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T37,T72

 LINE       450
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T36,T37

 LINE       450
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T36,T37
1	0	Covered	T8,T37,T72

 LINE       455
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T36,T37

 LINE       480
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T67
1	0	Covered	T64,T65,T66
1	1	Covered	T1,T2,T3

 LINE       486
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : fifo_data_valid)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       486
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       490
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T6
1	1	0	Covered	T88,T150,T226
1	1	1	Covered	T1,T2,T3

 LINE       494
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T7,T118,T235
1	1	1	Covered	T1,T4,T6

 LINE       511
 EXPRESSION (hint_forward & fifo_data_valid)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T6

 LINE       515
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       518
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T2,T3

 LINE       519
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

 LINE       573
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T8,T37,T70
1	1	0	Covered	T1,T4,T6
1	1	1	Covered	T1,T2,T3

 LINE       574
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T21,T31,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       590
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T8,T37,T70
1	1	0	Covered	T88,T150,T226
1	1	1	Covered	T1,T2,T3

 LINE       600
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       600
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       604
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       604
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T1,T2,T3

 LINE       612
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T6

 LINE       612
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       629
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       629
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       629
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       634
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T67
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       634
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       634
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T4,T5
1	1	1	0	Covered	T1,T4,T5
1	1	1	1	Covered	T1,T4,T5

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T4,T6
1	1	1	0	Covered	T1,T4,T5
1	1	1	1	Covered	T1,T4,T6

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T4,T6
1	1	1	0	Covered	T1,T4,T6
1	1	1	1	Covered	T1,T4,T6

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T4,T6
1	1	1	0	Covered	T1,T4,T6
1	1	1	1	Covered	T1,T4,T6

 LINE       650
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T220
1	0	Not Covered

 LINE       656
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       669
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T13,T8

 LINE       690
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       690
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       702
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       705
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T12,T13,T8

 LINE       705
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T13,T8

 LINE       705
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T8,T37,T72

 LINE       705
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T220

 LINE       709
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T13,T8

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		40	40	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	486	2	2	100.00
TERNARY	600	3	3	100.00
TERNARY	604	3	3	100.00
TERNARY	629	3	3	100.00
TERNARY	656	2	2	100.00
TERNARY	690	2	2	100.00
TERNARY	669	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	576	4	4	100.00
IF	648	2	2	100.00



	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T6



	LineNo.	Expression
-1-:	231	(no_match) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	301	((|alloc)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ?

Branches:

-1-	Status	Tests
1	Covered	T8,T36,T37
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	486	(hint_descram) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	600	(forward) ? 
-2-:	600	(hint_descram) ?

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	604	(forward) ? 
-2-:	604	((~hint_forward)) ?

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T4,T6



	LineNo.	Expression
-1-:	629	(forward) ? 
-2-:	629	(((~hint_forward) & fifo_data_ready)) ?

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	656	((|buf_rsp_match)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	690	(rsp_fifo_rdata.intg_ecc_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	669	(data_err_o) ?

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T8
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T6



	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	576	if ((!rst_ni))
-2-:	578	if (calc_req_start)
-3-:	580	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	648	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	413288616	972476	0	0
ExclusiveOps_A	413288616	412434372	0	0
ExclusiveProgHazard_A	413288616	412434372	0	0
ExclusiveState_A	413288616	412434372	0	0
ForwardCheck_A	413288616	2367723	0	0
IdleCheck_A	413288616	54511239	0	0
MaxBufs_A	1060	1060	0	0
OneHotAlloc_A	413288616	412434372	0	0
OneHotMatch_A	413288616	412434372	0	0
OneHotRspMatch_A	413288616	412434372	0	0
OneHotUpdate_A	413288616	412434372	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes
Total	413288616	972476
T1	817101	293
T2	9543	0
T3	3637	0
T4	519257	249
T5	629	1
T6	792567	2429
T7	0	4832
T8	0	1720
T12	1242	0
T13	1154	0
T17	12568	0
T18	4113	0
T21	0	256
T31	0	768
T36	0	72
T74	0	3

ExclusiveOps_A

Name	Attempts	Real Successes
Total	413288616	412434372
T1	817101	817011
T2	9543	9361
T3	3637	3000
T4	519257	519174
T5	629	568
T6	792567	792426
T12	1242	1038
T13	1154	922
T17	12568	12424
T18	4113	3491

ExclusiveProgHazard_A

Name	Attempts	Real Successes
Total	413288616	412434372
T1	817101	817011
T2	9543	9361
T3	3637	3000
T4	519257	519174
T5	629	568
T6	792567	792426
T12	1242	1038
T13	1154	922
T17	12568	12424
T18	4113	3491

ExclusiveState_A

Name	Attempts	Real Successes
Total	413288616	412434372
T1	817101	817011
T2	9543	9361
T3	3637	3000
T4	519257	519174
T5	629	568
T6	792567	792426
T12	1242	1038
T13	1154	922
T17	12568	12424
T18	4113	3491

ForwardCheck_A

Name	Attempts	Real Successes
Total	413288616	2367723
T1	817101	299
T2	9543	0
T3	3637	0
T4	519257	287
T5	629	0
T6	792567	12150
T7	0	8531
T12	1242	0
T13	1154	0
T17	12568	0
T18	4113	0
T19	0	10077
T31	0	544
T35	0	12844
T72	0	10337
T181	0	32
T227	0	4

IdleCheck_A

Name	Attempts	Real Successes
Total	413288616	54511239
T1	817101	1019
T2	9543	256
T3	3637	641
T4	519257	951
T5	629	137
T6	792567	623879
T12	1242	268
T13	1154	268
T17	12568	256
T18	4113	896

MaxBufs_A

Name	Attempts	Real Successes
Total	1060	1060
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T12	1	1
T13	1	1
T17	1	1
T18	1	1

OneHotAlloc_A

Name	Attempts	Real Successes
Total	413288616	412434372
T1	817101	817011
T2	9543	9361
T3	3637	3000
T4	519257	519174
T5	629	568
T6	792567	792426
T12	1242	1038
T13	1154	922
T17	12568	12424
T18	4113	3491

OneHotMatch_A

Name	Attempts	Real Successes
Total	413288616	412434372
T1	817101	817011
T2	9543	9361
T3	3637	3000
T4	519257	519174
T5	629	568
T6	792567	792426
T12	1242	1038
T13	1154	922
T17	12568	12424
T18	4113	3491

OneHotRspMatch_A

Name	Attempts	Real Successes
Total	413288616	412434372
T1	817101	817011
T2	9543	9361
T3	3637	3000
T4	519257	519174
T5	629	568
T6	792567	792426
T12	1242	1038
T13	1154	922
T17	12568	12424
T18	4113	3491

OneHotUpdate_A

Name	Attempts	Real Successes
Total	413288616	412434372
T1	817101	817011
T2	9543	9361
T3	3637	3000
T4	519257	519174
T5	629	568
T6	792567	792426
T12	1242	1038
T13	1154	922
T17	12568	12424
T18	4113	3491

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.97	100.00	91.87			100.00	100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.63	100.00	90.52			100.00	100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.82	99.16	93.71	100.00		100.00	96.23

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.38	96.63	83.96		100.00	91.30	100.00	gen_flash_cores[1].u_core

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
u_bus_intg	100.00	100.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	97.22	100.00	88.89			100.00	100.00
u_plain_enc	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67