Unified Coverage Report :: Module :: flash_phy_core

Module : flash_phy_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	91.51		100.00	97.83	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core	96.36	100.00	83.96		100.00	97.83	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core	97.87	100.00	91.51		100.00	97.83	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.36	100.00	83.96		100.00	97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	97.91	93.01	96.90	100.00	99.62	97.94

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.89	97.67	84.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	98.65	100.00	96.92	95.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	91.95	75.93	91.89			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.82	99.16	93.71	100.00		100.00	96.23
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	91.51		100.00	97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.29	97.91	94.29	100.00	100.00	99.62	97.94

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.89	97.67	84.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	99.74	100.00	98.46	100.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	93.98	75.93	100.00			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.92	99.16	94.22	100.00		100.00	96.23
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
ALWAYS	202	4	4	100.00
ALWAYS	214	6	6	100.00
ALWAYS	228	6	6	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
ALWAYS	324	29	29	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	566	1	1	100.00
CONT_ASSIGN	583	1	1	100.00
CONT_ASSIGN	584	1	1	100.00
CONT_ASSIGN	585	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
164	3	3
195	1	1
199	1	1
202	1	1
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
			MISSING_ELSE
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
			MISSING_ELSE
276	1	1
279	1	1
280	1	1
281	1	1
286	1	1
316	1	1
320	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
330	1	1
332	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
			MISSING_ELSE
346	1	1
347	1	1
348	1	1
			MISSING_ELSE
355	1	1
356	1	1
357	1	1
358	1	1
			MISSING_ELSE
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
			MISSING_ELSE
373	1	1
374	1	1
387	1	1
391	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
414	1	1
427	1	1
521	1	1
548	1	1
549	1	1
550	1	1
551	1	1
553	1	1
554	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
566	1	1
583	1	1
584	1	1
585	1	1

---

Cond Coverage for Module : flash_phy_core

	Total	Covered	Percent
Conditions	106	97	91.51
Logical	106	97	91.51
Non-Logical	0	0
Event	0	0

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Covered	T10,T130,T11

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T10,T130,T11

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T7,T9
1	Covered	T1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T4,T7,T9
1	Covered	T1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T4,T7,T9

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T9,T10
1	0	1	Covered	T4,T7,T9
1	1	0	Covered	T43,T56,T57
1	1	1	Covered	T4,T7,T9

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T9
1	1	Covered	T4,T7,T9

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Covered	T4,T7,T9

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T9

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T23,T77,T78
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T9

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T9

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T2,T3

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T20
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T5,T20

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T43,T56,T57
1	0	Covered	T190,T191

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T190,T191

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T43,T56,T57

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T9

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T9

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T9

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T9

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T20

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T20

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T20,T62
1	0	Covered	T1,T5,T20

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Not Covered
1	1	Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T9

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T2,T3

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T44
1	0	Covered	T18,T19,T44

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T21

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T21

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T21

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T21

---

FSM Coverage for Module : flash_phy_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	340	Covered	T1,T5,T20
StCtrlProg	338	Covered	T1,T5,T20
StCtrlRead	336	Covered	T1,T2,T3
StDisable	334	Covered	T14,T15,T16
StIdle	348	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	368	Covered	T1,T5,T20
StCtrlProg->StIdle	358	Covered	T1,T5,T20
StCtrlRead->StIdle	348	Covered	T1,T2,T3
StIdle->StCtrl	340	Covered	T1,T5,T20
StIdle->StCtrlProg	338	Covered	T1,T5,T20
StIdle->StCtrlRead	336	Covered	T1,T2,T3
StIdle->StDisable	334	Covered	T14,T15,T16

---

Branch Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	316	2	2	100.00
TERNARY	391	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	550	2	2	100.00
TERNARY	551	2	2	100.00
TERNARY	430	2	1	50.00
IF	151	4	4	100.00
IF	164	2	2	100.00
IF	202	3	3	100.00
IF	214	4	4	100.00
IF	228	4	4	100.00
CASE	330	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	316	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	391	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	430	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if (ctrl_rsp_vld)
-3-:	155	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	202	if ((!rst_ni))
-2-:	204	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T10,T130,T11
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	216	if ((host_outstanding == '0))
-3-:	218	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T11,T17
0	0	0	Covered	T4,T7,T9

	LineNo.	Expression
-1-:	228	if ((!rst_ni))
-2-:	230	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	232	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T11,T17
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	330	case (state_q)
-2-:	333	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	335	if ((ctrl_gnt && rd_i))
-4-:	337	if ((ctrl_gnt && prog_i))
-5-:	339	if (ctrl_gnt)
-6-:	346	if (rd_stage_data_valid)
-7-:	356	if (prog_ack)
-8-:	366	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T14,T15,T16
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T1,T5,T20
StIdle	0	0	0	1	-	-	-	Covered	T1,T5,T20
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T1,T5,T20
StCtrlProg	-	-	-	-	-	0	-	Covered	T1,T5,T20
StCtrl	-	-	-	-	-	-	1	Covered	T1,T5,T20
StCtrl	-	-	-	-	-	-	0	Covered	T1,T5,T20
StDisable	-	-	-	-	-	-	-	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	Covered	T18,T11,T19

---

Assert Coverage for Module : flash_phy_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	821052226	4463487	0	0
CtrlPrio_A	821052226	4463486	0	0
HostTransIdleChk_A	821052226	46557975	0	0
NoRemainder_A	2118	2118	0	0
OneHotReqs_A	821052226	819400756	0	0
Pow2Multiple_A	2118	2118	0	0
RdTxnCheck_A	820498362	818846892	0	0
u_state_regs_A	821052226	819400756	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821052226	4463487	0	0
T4	106280	5130	0	0
T5	1640840	0	0	0
T6	147848	0	0	0
T7	239580	6543	0	0
T8	18592	0	0	0
T9	1793638	87653	0	0
T14	757520	0	0	0
T20	151366	0	0	0
T21	261706	0	0	0
T24	10038	0	0	0
T34	0	840	0	0
T36	0	4840	0	0
T37	0	4279	0	0
T47	0	14436	0	0
T49	0	3085	0	0
T64	0	7439	0	0
T121	0	4	0	0
T192	0	3210	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821052226	4463486	0	0
T4	106280	5130	0	0
T5	1640840	0	0	0
T6	147848	0	0	0
T7	239580	6543	0	0
T8	18592	0	0	0
T9	1793638	87653	0	0
T14	757520	0	0	0
T20	151366	0	0	0
T21	261706	0	0	0
T24	10038	0	0	0
T34	0	840	0	0
T36	0	4840	0	0
T37	0	4279	0	0
T47	0	14436	0	0
T49	0	3085	0	0
T64	0	7439	0	0
T121	0	4	0	0
T192	0	3210	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821052226	46557975	0	0
T4	106280	59480	0	0
T5	1640840	0	0	0
T6	147848	0	0	0
T7	239580	58327	0	0
T8	18592	0	0	0
T9	1793638	833187	0	0
T14	757520	0	0	0
T18	0	110	0	0
T20	151366	0	0	0
T21	261706	0	0	0
T23	0	28	0	0
T24	10038	20	0	0
T26	0	16	0	0
T28	0	16	0	0
T36	0	58181	0	0
T37	0	57865	0	0
T47	0	155262	0	0
T48	0	15	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2118	2118	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T20	2	2	0	0
T21	2	2	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821052226	819400756	0	0
T1	404960	387050	0	0
T2	2274	2096	0	0
T3	6076	4642	0	0
T4	106280	106152	0	0
T5	1640840	1640730	0	0
T6	147848	141682	0	0
T7	239580	239308	0	0
T8	18592	18404	0	0
T20	151366	151262	0	0
T21	261706	245892	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2118	2118	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T20	2	2	0	0
T21	2	2	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	820498362	818846892	0	0
T1	404960	387050	0	0
T2	2274	2096	0	0
T3	6076	4642	0	0
T4	106280	106152	0	0
T5	1640840	1640730	0	0
T6	147848	141682	0	0
T7	239580	239308	0	0
T8	18592	18404	0	0
T20	151366	151262	0	0
T21	261706	245892	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821052226	819400756	0	0
T1	404960	387050	0	0
T2	2274	2096	0	0
T3	6076	4642	0	0
T4	106280	106152	0	0
T5	1640840	1640730	0	0
T6	147848	141682	0	0
T7	239580	239308	0	0
T8	18592	18404	0	0
T20	151366	151262	0	0
T21	261706	245892	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
ALWAYS	202	4	4	100.00
ALWAYS	214	6	6	100.00
ALWAYS	228	6	6	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
ALWAYS	324	29	29	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	566	1	1	100.00
CONT_ASSIGN	583	1	1	100.00
CONT_ASSIGN	584	1	1	100.00
CONT_ASSIGN	585	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
164	3	3
195	1	1
199	1	1
202	1	1
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
			MISSING_ELSE
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
			MISSING_ELSE
276	1	1
279	1	1
280	1	1
281	1	1
286	1	1
316	1	1
320	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
330	1	1
332	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
			MISSING_ELSE
346	1	1
347	1	1
348	1	1
			MISSING_ELSE
355	1	1
356	1	1
357	1	1
358	1	1
			MISSING_ELSE
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
			MISSING_ELSE
373	1	1
374	1	1
387	1	1
391	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
414	1	1
427	1	1
521	1	1
548	1	1
549	1	1
550	1	1
551	1	1
553	1	1
554	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
566	1	1
583	1	1
584	1	1
585	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Covered	Percent
Conditions	106	89	83.96
Logical	106	89	83.96
Non-Logical	0	0
Event	0	0

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Not Covered

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T20
1	0	Covered	T4,T7,T9
1	1	Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T7,T9
1	Covered	T1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T4,T5,T20
1	1	Covered	T1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T4,T7,T9
1	Covered	T1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T9,T10,T36
1	1	0	Not Covered
1	1	1	Covered	T4,T7,T9

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T10,T36
1	0	1	Covered	T4,T7,T9
1	1	0	Not Covered
1	1	1	Covered	T4,T7,T9

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T9
1	1	Covered	T4,T7,T9

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T20
1	0	Covered	T4,T7,T9
1	1	Covered	T4,T7,T9

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T9

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T20
1	1	Covered	T4,T7,T9

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T4,T5,T20
1	1	Covered	T4,T7,T9

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T8
1	1	Covered	T4,T5,T20

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T20
1	0	Covered	T5,T20,T8
1	1	Covered	T5,T20,T8

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T20
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T9

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T9

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T9

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T9

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T8
1	1	Covered	T4,T5,T20

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T20
1	0	Covered	T4,T5,T20
1	1	Covered	T5,T20,T8

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T20
1	0	Covered	T4,T5,T20
1	1	Covered	T5,T20,T8

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T20,T62
1	0	Covered	T1,T5,T20

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Not Covered
1	1	Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T9

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T8
1	1	Covered	T4,T5,T20

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T44
1	0	Covered	T18,T19,T44

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T14
1	0	Covered	T14,T16,T25

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T14
1	0	Covered	T14,T16,T25

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T16,T25

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T16,T25

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	340	Covered	T5,T20,T8
StCtrlProg	338	Covered	T5,T20,T8
StCtrlRead	336	Covered	T4,T5,T20
StDisable	334	Covered	T14,T15,T16
StIdle	348	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	368	Covered	T5,T20,T8
StCtrlProg->StIdle	358	Covered	T5,T20,T8
StCtrlRead->StIdle	348	Covered	T4,T5,T20
StIdle->StCtrl	340	Covered	T5,T20,T8
StIdle->StCtrlProg	338	Covered	T5,T20,T8
StIdle->StCtrlRead	336	Covered	T4,T5,T20
StIdle->StDisable	334	Covered	T14,T15,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	316	2	2	100.00
TERNARY	391	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	550	2	2	100.00
TERNARY	551	2	2	100.00
TERNARY	430	2	1	50.00
IF	151	4	4	100.00
IF	164	2	2	100.00
IF	202	3	3	100.00
IF	214	4	4	100.00
IF	228	4	4	100.00
CASE	330	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	316	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	391	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T16,T25
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T16,T25
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	430	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if (ctrl_rsp_vld)
-3-:	155	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T20
0	0	1	Covered	T4,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	202	if ((!rst_ni))
-2-:	204	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T11,T17
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	216	if ((host_outstanding == '0))
-3-:	218	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T11,T17
0	0	0	Covered	T4,T7,T9

	LineNo.	Expression
-1-:	228	if ((!rst_ni))
-2-:	230	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	232	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T11,T17
0	0	0	Covered	T4,T5,T20

	LineNo.	Expression
-1-:	330	case (state_q)
-2-:	333	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	335	if ((ctrl_gnt && rd_i))
-4-:	337	if ((ctrl_gnt && prog_i))
-5-:	339	if (ctrl_gnt)
-6-:	346	if (rd_stage_data_valid)
-7-:	356	if (prog_ack)
-8-:	366	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T14,T15,T16
StIdle	0	1	-	-	-	-	-	Covered	T4,T5,T20
StIdle	0	0	1	-	-	-	-	Covered	T5,T20,T8
StIdle	0	0	0	1	-	-	-	Covered	T5,T20,T8
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T4,T5,T20
StCtrlRead	-	-	-	-	0	-	-	Covered	T4,T5,T20
StCtrlProg	-	-	-	-	-	1	-	Covered	T5,T20,T8
StCtrlProg	-	-	-	-	-	0	-	Covered	T5,T20,T8
StCtrl	-	-	-	-	-	-	1	Covered	T5,T20,T8
StCtrl	-	-	-	-	-	-	0	Covered	T5,T20,T8
StDisable	-	-	-	-	-	-	-	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	Covered	T18,T11,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	410526113	2193677	0	0
CtrlPrio_A	410526113	2193677	0	0
HostTransIdleChk_A	410526113	23240051	0	0
NoRemainder_A	1059	1059	0	0
OneHotReqs_A	410526113	409700378	0	0
Pow2Multiple_A	1059	1059	0	0
RdTxnCheck_A	410249181	409423446	0	0
u_state_regs_A	410526113	409700378	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	2193677	0	0
T4	53140	2169	0	0
T5	820420	0	0	0
T6	73924	0	0	0
T7	119790	2070	0	0
T8	9296	0	0	0
T9	896819	52015	0	0
T14	378760	0	0	0
T20	75683	0	0	0
T21	130853	0	0	0
T24	5019	0	0	0
T34	0	840	0	0
T36	0	2888	0	0
T37	0	1627	0	0
T47	0	6170	0	0
T49	0	1325	0	0
T64	0	4042	0	0
T192	0	1340	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	2193677	0	0
T4	53140	2169	0	0
T5	820420	0	0	0
T6	73924	0	0	0
T7	119790	2070	0	0
T8	9296	0	0	0
T9	896819	52015	0	0
T14	378760	0	0	0
T20	75683	0	0	0
T21	130853	0	0	0
T24	5019	0	0	0
T34	0	840	0	0
T36	0	2888	0	0
T37	0	1627	0	0
T47	0	6170	0	0
T49	0	1325	0	0
T64	0	4042	0	0
T192	0	1340	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	23240051	0	0
T4	53140	31091	0	0
T5	820420	0	0	0
T6	73924	0	0	0
T7	119790	29893	0	0
T8	9296	0	0	0
T9	896819	426411	0	0
T14	378760	0	0	0
T18	0	61	0	0
T20	75683	0	0	0
T21	130853	0	0	0
T23	0	14	0	0
T24	5019	20	0	0
T26	0	16	0	0
T36	0	29143	0	0
T37	0	29258	0	0
T47	0	71230	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249181	409423446	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
ALWAYS	202	4	4	100.00
ALWAYS	214	6	6	100.00
ALWAYS	228	6	6	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
ALWAYS	324	29	29	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	566	1	1	100.00
CONT_ASSIGN	583	1	1	100.00
CONT_ASSIGN	584	1	1	100.00
CONT_ASSIGN	585	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
164	3	3
195	1	1
199	1	1
202	1	1
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
			MISSING_ELSE
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
			MISSING_ELSE
276	1	1
279	1	1
280	1	1
281	1	1
286	1	1
316	1	1
320	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
330	1	1
332	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
			MISSING_ELSE
346	1	1
347	1	1
348	1	1
			MISSING_ELSE
355	1	1
356	1	1
357	1	1
358	1	1
			MISSING_ELSE
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
			MISSING_ELSE
373	1	1
374	1	1
387	1	1
391	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
414	1	1
427	1	1
521	1	1
548	1	1
549	1	1
550	1	1
551	1	1
553	1	1
554	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
566	1	1
583	1	1
584	1	1
585	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Covered	Percent
Conditions	106	97	91.51
Logical	106	97	91.51
Non-Logical	0	0
Event	0	0

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Covered	T10,T130,T11

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T10,T130,T11

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T7,T9
1	Covered	T1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T4,T7,T9
1	Covered	T1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T4,T7,T9

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T9,T10
1	0	1	Covered	T4,T7,T9
1	1	0	Covered	T43,T56,T57
1	1	1	Covered	T4,T7,T9

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T9
1	1	Covered	T4,T7,T9

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Covered	T4,T7,T9

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T9

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T23,T77,T78
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T9

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T9

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T20
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T2,T3

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T8
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T5,T20

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T43,T56,T57
1	0	Covered	T190,T191

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T190,T191

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T43,T56,T57

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T9

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T9

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T9

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T9

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T20

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T20

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T20,T62
1	0	Covered	T1,T5,T20

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Not Covered
1	1	Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T9

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T2,T3

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T44
1	0	Covered	T18,T19,T44

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T21

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T21

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T21

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T21

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	340	Covered	T1,T5,T20
StCtrlProg	338	Covered	T1,T5,T20
StCtrlRead	336	Covered	T1,T2,T3
StDisable	334	Covered	T14,T15,T16
StIdle	348	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	368	Covered	T1,T5,T20
StCtrlProg->StIdle	358	Covered	T1,T5,T20
StCtrlRead->StIdle	348	Covered	T1,T2,T3
StIdle->StCtrl	340	Covered	T1,T5,T20
StIdle->StCtrlProg	338	Covered	T1,T5,T20
StIdle->StCtrlRead	336	Covered	T1,T2,T3
StIdle->StDisable	334	Covered	T14,T15,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	316	2	2	100.00
TERNARY	391	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	550	2	2	100.00
TERNARY	551	2	2	100.00
TERNARY	430	2	1	50.00
IF	151	4	4	100.00
IF	164	2	2	100.00
IF	202	3	3	100.00
IF	214	4	4	100.00
IF	228	4	4	100.00
CASE	330	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	316	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	391	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	430	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if (ctrl_rsp_vld)
-3-:	155	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	202	if ((!rst_ni))
-2-:	204	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T10,T130,T11
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	216	if ((host_outstanding == '0))
-3-:	218	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T11,T17
0	0	0	Covered	T4,T7,T9

	LineNo.	Expression
-1-:	228	if ((!rst_ni))
-2-:	230	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	232	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T11,T17
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	330	case (state_q)
-2-:	333	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	335	if ((ctrl_gnt && rd_i))
-4-:	337	if ((ctrl_gnt && prog_i))
-5-:	339	if (ctrl_gnt)
-6-:	346	if (rd_stage_data_valid)
-7-:	356	if (prog_ack)
-8-:	366	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T14,T15,T16
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T1,T5,T20
StIdle	0	0	0	1	-	-	-	Covered	T1,T5,T20
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T1,T5,T20
StCtrlProg	-	-	-	-	-	0	-	Covered	T1,T5,T20
StCtrl	-	-	-	-	-	-	1	Covered	T1,T5,T20
StCtrl	-	-	-	-	-	-	0	Covered	T1,T5,T20
StDisable	-	-	-	-	-	-	-	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	Covered	T18,T11,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	410526113	2269810	0	0
CtrlPrio_A	410526113	2269809	0	0
HostTransIdleChk_A	410526113	23317924	0	0
NoRemainder_A	1059	1059	0	0
OneHotReqs_A	410526113	409700378	0	0
Pow2Multiple_A	1059	1059	0	0
RdTxnCheck_A	410249181	409423446	0	0
u_state_regs_A	410526113	409700378	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	2269810	0	0
T4	53140	2961	0	0
T5	820420	0	0	0
T6	73924	0	0	0
T7	119790	4473	0	0
T8	9296	0	0	0
T9	896819	35638	0	0
T14	378760	0	0	0
T20	75683	0	0	0
T21	130853	0	0	0
T24	5019	0	0	0
T36	0	1952	0	0
T37	0	2652	0	0
T47	0	8266	0	0
T49	0	1760	0	0
T64	0	3397	0	0
T121	0	4	0	0
T192	0	1870	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	2269809	0	0
T4	53140	2961	0	0
T5	820420	0	0	0
T6	73924	0	0	0
T7	119790	4473	0	0
T8	9296	0	0	0
T9	896819	35638	0	0
T14	378760	0	0	0
T20	75683	0	0	0
T21	130853	0	0	0
T24	5019	0	0	0
T36	0	1952	0	0
T37	0	2652	0	0
T47	0	8266	0	0
T49	0	1760	0	0
T64	0	3397	0	0
T121	0	4	0	0
T192	0	1870	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	23317924	0	0
T4	53140	28389	0	0
T5	820420	0	0	0
T6	73924	0	0	0
T7	119790	28434	0	0
T8	9296	0	0	0
T9	896819	406776	0	0
T14	378760	0	0	0
T18	0	49	0	0
T20	75683	0	0	0
T21	130853	0	0	0
T23	0	14	0	0
T24	5019	0	0	0
T28	0	16	0	0
T36	0	29038	0	0
T37	0	28607	0	0
T47	0	84032	0	0
T48	0	15	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249181	409423446	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0