Unified Coverage Report :: Module :: flash_phy_rd

Module : flash_phy_rd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.97	100.00	91.87			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd	97.63	100.00	90.52			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd	97.97	100.00	91.87			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.63	100.00	90.52			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.82	99.16	93.71	100.00		100.00	96.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36	100.00	83.96		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
u_bus_intg	100.00	100.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	97.22	100.00	88.89			100.00	100.00
u_plain_enc	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.97	100.00	91.87			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	99.16	94.22	100.00		100.00	96.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.87	100.00	91.51		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
u_bus_intg	100.00	100.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	97.22	100.00	88.89			100.00	100.00
u_plain_enc	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

Line Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
TOTAL		122	122	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	480	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	573	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
ALWAYS	576	6	6	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	590	1	1	100.00
CONT_ASSIGN	593	1	1	100.00
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	612	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	634	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
ALWAYS	645	6	6	100.00
CONT_ASSIGN	656	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	690	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	715	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
480	1	1
486	1	1
490	1	1
494	1	1
511	1	1
515	1	1
518	1	1
519	1	1
573	1	1
574	1	1
576	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
			MISSING_ELSE
586	1	1
590	1	1
593	1	1
600	1	1
604	1	1
612	1	1
629	1	1
634	1	1
639	4	4
645	1	1
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
			MISSING_ELSE
656	1	1
668	1	1
669	1	1
690	1	1
702	1	1
705	1	1
709	1	1
712	1	1
715	1	1

---

Cond Coverage for Module : flash_phy_rd

	Total	Covered	Percent
Conditions	443	407	91.87
Logical	443	407	91.87
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       139
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       139
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       139
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       140
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       140
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       140
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       140
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       145
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T37,T27,T76
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T37,T27,T76

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       145
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T37,T199,T76
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T200
1	1	1	Covered	T37,T199,T76

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       145
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T37,T76,T201
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T37,T76,T201

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       145
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T37,T76,T202
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T37,T76,T202

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       153
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       153
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       153
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       166
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       166
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       166
 EXPRESSION (req_o & no_match)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T4,T5
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T1,T6,T21
1	1	1	0	1	1	1	Covered	T1,T4,T5
1	1	1	1	0	1	1	Covered	T37,T76,T202
1	1	1	1	1	0	1	Covered	T37
1	1	1	1	1	1	0	Covered	T49,T186,T203
1	1	1	1	1	1	1	Covered	T1,T4,T5

 LINE       195
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       195
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T4,T5
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T1,T6,T21
1	1	1	0	1	1	1	Covered	T1,T4,T5
1	1	1	1	0	1	1	Covered	T37,T202,T204
1	1	1	1	1	0	1	Covered	T205
1	1	1	1	1	1	0	Covered	T47,T192,T206
1	1	1	1	1	1	1	Covered	T1,T4,T5

 LINE       195
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       195
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T4,T5
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T1,T6,T21
1	1	1	0	1	1	1	Covered	T1,T4,T5
1	1	1	1	0	1	1	Covered	T37,T76,T202
1	1	1	1	1	0	1	Covered	T37,T205
1	1	1	1	1	1	0	Covered	T47,T49,T192
1	1	1	1	1	1	1	Covered	T1,T4,T5

 LINE       195
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       195
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T4,T5
1	0	1	1	1	1	1	Covered	T16,T207
1	1	0	1	1	1	1	Covered	T1,T6,T21
1	1	1	0	1	1	1	Covered	T1,T4,T5
1	1	1	1	0	1	1	Covered	T37,T76,T202
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T47,T49,T192
1	1	1	1	1	1	1	Covered	T1,T4,T5

 LINE       195
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       195
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T62,T49,T119
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T24,T62,T47
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T24,T62,T47
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T62,T47,T107
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T20,T8,T9
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T20,T8,T9
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T20,T8,T9
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T20,T8
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       221
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T20
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T5,T20

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T6,T21
0	1	0	Covered	T1,T6,T21
1	0	0	Covered	T5,T20,T62

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T6,T21

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T6,T21

 LINE       221
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T20
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T5,T20

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T6,T21
0	1	0	Covered	T1,T6,T21
1	0	0	Covered	T5,T20,T62

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T6,T21

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T6,T21

 LINE       221
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T20
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T5,T20

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T6,T21
0	1	0	Covered	T1,T6,T21
1	0	0	Covered	T5,T20,T62

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T6,T21

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T6,T21

 LINE       221
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T20
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T5,T20

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T6,T21
0	1	0	Covered	T1,T6,T21
1	0	0	Covered	T5,T20,T62

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T6,T21

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T6,T21

 LINE       231
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T47,T37,T64
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       238
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T47
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       238
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T47
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       238
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T47
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       290
 EXPRESSION (req_o & ack_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T47,T64,T75
1	1	Covered	T1,T2,T3

 LINE       291
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       301
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       304
 EXPRESSION (req_i && rdy_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Covered	T1,T2,T3

 LINE       307
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       376
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       381
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T36
1	0	Covered	T10,T23,T18
1	1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       398
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T4,T7,T24
1	1	1	1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T7,T10
1	1	1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       406
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	Not Covered
1	1	0	1	1	1	Covered	T9,T47,T49
1	1	1	0	1	1	Covered	T10,T23,T43
1	1	1	1	0	1	Covered	T1,T4,T5
1	1	1	1	1	0	Covered	T4,T7,T10
1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       406
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T8
1	1	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T10,T28

 LINE       431
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T20

 LINE       441
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T9,T51,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T37,T27,T199

 LINE       450
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T36,T26

 LINE       450
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T36,T26
1	0	Covered	T37,T27,T199

 LINE       455
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T51
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T36,T26

 LINE       480
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T18,T44,T45
1	0	Covered	T10,T23,T43
1	1	Covered	T1,T2,T3

 LINE       486
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : fifo_data_valid)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       486
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       490
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T20,T8
1	1	0	Covered	T10,T28,T23
1	1	1	Covered	T1,T2,T3

 LINE       494
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T75,T208,T184
1	1	1	Covered	T5,T20,T8

 LINE       511
 EXPRESSION (hint_forward & fifo_data_valid)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T20,T8

 LINE       515
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       518
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T20,T8
1	1	Covered	T1,T2,T3

 LINE       519
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T20,T8

 LINE       573
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T64,T75,T182
1	1	0	Covered	T5,T20,T8
1	1	1	Covered	T1,T2,T3

 LINE       574
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       590
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T7,T36
1	1	0	Covered	T10,T28,T23
1	1	1	Covered	T1,T2,T3

 LINE       600
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T20,T8

 LINE       600
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       604
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T20,T8

 LINE       604
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------

-1-	Status	Tests
0	Covered	T5,T20,T8
1	Covered	T1,T2,T3

 LINE       612
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T8

 LINE       612
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       629
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T20,T8

 LINE       629
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       629
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       634
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T18,T44,T45
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       634
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       634
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T4,T5
1	1	1	0	Covered	T1,T4,T5
1	1	1	1	Covered	T1,T4,T5

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T4,T5
1	1	1	0	Covered	T1,T4,T5
1	1	1	1	Covered	T1,T4,T5

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T4,T5
1	1	1	0	Covered	T1,T4,T5
1	1	1	1	Covered	T1,T4,T5

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T4,T5
1	1	1	0	Covered	T1,T4,T5
1	1	1	1	Covered	T1,T4,T5

 LINE       650
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T200
1	0	Not Covered

 LINE       656
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       669
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T135,T26,T129

 LINE       690
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       690
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       702
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       705
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T135,T26,T129

 LINE       705
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T135,T26,T129

 LINE       705
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T37,T76,T209

 LINE       705
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T200

 LINE       709
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T135,T26,T129

---

Branch Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
Branches		40	40	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	486	2	2	100.00
TERNARY	600	3	3	100.00
TERNARY	604	3	3	100.00
TERNARY	629	3	3	100.00
TERNARY	656	2	2	100.00
TERNARY	690	2	2	100.00
TERNARY	669	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	576	4	4	100.00
IF	648	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	301	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T36,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	486	(hint_descram) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	(forward) ? 
-2-:	600	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T20,T8
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	604	(forward) ? 
-2-:	604	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T20,T8
0	1	Covered	T1,T2,T3
0	0	Covered	T5,T20,T8

	LineNo.	Expression
-1-:	629	(forward) ? 
-2-:	629	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T20,T8
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	656	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	690	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	669	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T135,T26,T129
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	576	if ((!rst_ni))
-2-:	578	if (calc_req_start)
-3-:	580	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	648	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	821052226	1613653	0	0
ExclusiveOps_A	821052226	819400756	0	0
ExclusiveProgHazard_A	821052226	819400756	0	0
ExclusiveState_A	821052226	819400756	0	0
ForwardCheck_A	821052226	4476170	0	0
IdleCheck_A	821052226	105217538	0	0
MaxBufs_A	2118	2118	0	0
OneHotAlloc_A	821052226	819400756	0	0
OneHotMatch_A	821052226	819400756	0	0
OneHotRspMatch_A	821052226	819400756	0	0
OneHotUpdate_A	821052226	819400756	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821052226	1613653	0	0
T1	202480	1456	0	0
T2	1137	0	0	0
T3	3038	0	0	0
T4	106280	1404	0	0
T5	1640840	849	0	0
T6	147848	500	0	0
T7	239580	7532	0	0
T8	18592	57	0	0
T9	896819	6971	0	0
T14	378760	0	0	0
T16	0	30	0	0
T20	151366	163	0	0
T21	261706	1364	0	0
T24	5019	122	0	0
T36	0	931	0	0
T50	0	2168	0	0
T58	0	101	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821052226	819400756	0	0
T1	404960	387050	0	0
T2	2274	2096	0	0
T3	6076	4642	0	0
T4	106280	106152	0	0
T5	1640840	1640730	0	0
T6	147848	141682	0	0
T7	239580	239308	0	0
T8	18592	18404	0	0
T20	151366	151262	0	0
T21	261706	245892	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821052226	819400756	0	0
T1	404960	387050	0	0
T2	2274	2096	0	0
T3	6076	4642	0	0
T4	106280	106152	0	0
T5	1640840	1640730	0	0
T6	147848	141682	0	0
T7	239580	239308	0	0
T8	18592	18404	0	0
T20	151366	151262	0	0
T21	261706	245892	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821052226	819400756	0	0
T1	404960	387050	0	0
T2	2274	2096	0	0
T3	6076	4642	0	0
T4	106280	106152	0	0
T5	1640840	1640730	0	0
T6	147848	141682	0	0
T7	239580	239308	0	0
T8	18592	18404	0	0
T20	151366	151262	0	0
T21	261706	245892	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821052226	4476170	0	0
T5	1640840	863	0	0
T6	147848	0	0	0
T7	239580	0	0	0
T8	18592	74	0	0
T9	1793638	24752	0	0
T14	757520	0	0	0
T16	0	101	0	0
T20	151366	195	0	0
T21	261706	0	0	0
T22	118156	0	0	0
T23	0	6	0	0
T24	10038	0	0	0
T31	0	544	0	0
T47	0	22675	0	0
T52	0	1	0	0
T58	0	187	0	0
T60	0	30	0	0
T62	0	152	0	0
T105	0	3	0	0
T210	0	14	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821052226	105217538	0	0
T1	202480	22256	0	0
T2	1137	128	0	0
T3	3038	402	0	0
T4	106280	71012	0	0
T5	1640840	2703	0	0
T6	147848	7460	0	0
T7	239580	101330	0	0
T8	18592	333	0	0
T9	896819	632847	0	0
T14	378760	524288	0	0
T16	0	524408	0	0
T20	151366	681	0	0
T21	261706	20164	0	0
T24	5019	590	0	0
T58	0	365	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2118	2118	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T20	2	2	0	0
T21	2	2	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821052226	819400756	0	0
T1	404960	387050	0	0
T2	2274	2096	0	0
T3	6076	4642	0	0
T4	106280	106152	0	0
T5	1640840	1640730	0	0
T6	147848	141682	0	0
T7	239580	239308	0	0
T8	18592	18404	0	0
T20	151366	151262	0	0
T21	261706	245892	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821052226	819400756	0	0
T1	404960	387050	0	0
T2	2274	2096	0	0
T3	6076	4642	0	0
T4	106280	106152	0	0
T5	1640840	1640730	0	0
T6	147848	141682	0	0
T7	239580	239308	0	0
T8	18592	18404	0	0
T20	151366	151262	0	0
T21	261706	245892	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821052226	819400756	0	0
T1	404960	387050	0	0
T2	2274	2096	0	0
T3	6076	4642	0	0
T4	106280	106152	0	0
T5	1640840	1640730	0	0
T6	147848	141682	0	0
T7	239580	239308	0	0
T8	18592	18404	0	0
T20	151366	151262	0	0
T21	261706	245892	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821052226	819400756	0	0
T1	404960	387050	0	0
T2	2274	2096	0	0
T3	6076	4642	0	0
T4	106280	106152	0	0
T5	1640840	1640730	0	0
T6	147848	141682	0	0
T7	239580	239308	0	0
T8	18592	18404	0	0
T20	151366	151262	0	0
T21	261706	245892	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		122	122	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	480	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	573	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
ALWAYS	576	6	6	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	590	1	1	100.00
CONT_ASSIGN	593	1	1	100.00
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	612	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	634	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
ALWAYS	645	6	6	100.00
CONT_ASSIGN	656	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	690	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	715	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
480	1	1
486	1	1
490	1	1
494	1	1
511	1	1
515	1	1
518	1	1
519	1	1
573	1	1
574	1	1
576	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
			MISSING_ELSE
586	1	1
590	1	1
593	1	1
600	1	1
604	1	1
612	1	1
629	1	1
634	1	1
639	4	4
645	1	1
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
			MISSING_ELSE
656	1	1
668	1	1
669	1	1
690	1	1
702	1	1
705	1	1
709	1	1
712	1	1
715	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Covered	Percent
Conditions	443	401	90.52
Logical	443	401	90.52
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       139
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       139
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       139
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       140
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       140
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       140
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       140
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       145
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T20
0	1	Covered	T37,T76,T202
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T20
1	1	0	Not Covered
1	1	1	Covered	T37,T76,T202

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       145
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T20
0	1	Covered	T37,T76,T209
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T20
1	1	0	Not Covered
1	1	1	Covered	T37,T76,T209

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       145
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T20
0	1	Covered	T37,T76,T201
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T20
1	1	0	Not Covered
1	1	1	Covered	T37,T76,T201

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       145
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T20
0	1	Covered	T37,T76,T202
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T20
1	1	0	Not Covered
1	1	1	Covered	T37,T76,T202

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       153
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T20

 LINE       153
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T20

 LINE       153
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T20

 LINE       166
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------

-1-	Status	Tests
0	Covered	T4,T5,T20
1	Covered	T1,T2,T3

 LINE       166
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T20
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       166
 EXPRESSION (req_o & no_match)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T20

 LINE       185
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T20
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T4,T5,T20
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T26,T211,T212
1	1	1	0	1	1	1	Covered	T4,T5,T20
1	1	1	1	0	1	1	Covered	T37,T76,T202
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T49,T186,T213
1	1	1	1	1	1	1	Covered	T4,T5,T20

 LINE       195
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T20
1	0	Covered	T4,T5,T20

 LINE       195
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T4,T5,T20
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T214,T215,T89
1	1	1	0	1	1	1	Covered	T4,T5,T20
1	1	1	1	0	1	1	Covered	T37,T216,T217
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T47,T192,T206
1	1	1	1	1	1	1	Covered	T4,T5,T20

 LINE       195
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T20
1	0	Covered	T4,T5,T20

 LINE       195
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T4,T5,T20
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T26,T112,T214
1	1	1	0	1	1	1	Covered	T4,T5,T20
1	1	1	1	0	1	1	Covered	T37,T202,T216
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T192,T206,T76
1	1	1	1	1	1	1	Covered	T4,T5,T20

 LINE       195
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T20
1	0	Covered	T4,T5,T20

 LINE       195
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T4,T5,T20
1	0	1	1	1	1	1	Covered	T16
1	1	0	1	1	1	1	Covered	T112,T214,T215
1	1	1	0	1	1	1	Covered	T4,T5,T20
1	1	1	1	0	1	1	Covered	T37,T76,T218
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T47,T49,T110
1	1	1	1	1	1	1	Covered	T4,T5,T20

 LINE       195
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T20
1	0	Covered	T4,T5,T20

 LINE       195
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T62,T49,T119
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T24,T62,T47
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T24,T62,T192
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T62,T47,T49
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T20,T8,T24
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T20,T8,T24
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T20,T8,T9
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T20,T8,T24
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       221
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T14,T16
1	0	Covered	T4,T5,T20
1	1	Covered	T5,T26,T62

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T14,T16,T59
0	1	0	Covered	T14,T16,T26
1	0	0	Covered	T5,T62,T60

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T8
1	1	Covered	T14,T16,T26

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T8
1	1	Covered	T14,T16,T59

 LINE       221
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T14,T16
1	0	Covered	T4,T5,T20
1	1	Covered	T5,T62,T60

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T14,T16,T59
0	1	0	Covered	T14,T16,T59
1	0	0	Covered	T5,T62,T60

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T8
1	1	Covered	T14,T16,T59

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T8
1	1	Covered	T14,T16,T59

 LINE       221
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T14,T16
1	0	Covered	T4,T5,T20
1	1	Covered	T5,T26,T62

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T14,T16,T59
0	1	0	Covered	T14,T16,T26
1	0	0	Covered	T5,T62,T60

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T8
1	1	Covered	T14,T16,T26

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T8
1	1	Covered	T14,T16,T59

 LINE       221
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T14,T16
1	0	Covered	T4,T5,T20
1	1	Covered	T5,T62,T60

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T14,T16,T59
0	1	0	Covered	T14,T16,T59
1	0	0	Covered	T5,T62,T60

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T8
1	1	Covered	T14,T16,T59

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T8
1	1	Covered	T14,T16,T59

 LINE       231
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Covered	T4,T5,T20
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T47,T37,T64
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T20

 LINE       238
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T9,T47,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T20

 LINE       238
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T47
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T20

 LINE       238
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T9,T47,T37
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T20

 LINE       290
 EXPRESSION (req_o & ack_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T47,T64,T75
1	1	Covered	T4,T5,T20

 LINE       291
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T8
1	0	Covered	T4,T5,T20
1	1	Covered	T4,T5,T20

 LINE       301
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       304
 EXPRESSION (req_i && rdy_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Covered	T4,T5,T20

 LINE       307
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T20
1	1	Covered	T4,T5,T20

 LINE       376
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T20
0	1	Covered	T4,T5,T20
1	0	Covered	T1,T2,T3

 LINE       381
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T36
1	0	Covered	T10,T23,T18
1	1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       398
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T4,T7,T24
1	1	1	1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---

-1-	Status	Tests
0	Covered	T4,T5,T20
1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T20
1	1	0	Covered	T4,T7,T10
1	1	1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T14

 LINE       406
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	Not Covered
1	1	0	1	1	1	Covered	T9,T47,T49
1	1	1	0	1	1	Covered	T10,T43,T190
1	1	1	1	0	1	Covered	T4,T5,T20
1	1	1	1	1	0	Covered	T4,T7,T10
1	1	1	1	1	1	Covered	T4,T5,T20

 LINE       406
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T14

 LINE       427
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T14
1	0	Covered	T5,T20,T8
1	1	Covered	T4,T7,T14

 LINE       431
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T8
1	0	Covered	T4,T5,T20
1	1	Covered	T5,T10,T47

 LINE       431
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T20,T8

 LINE       441
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T9,T51,T26
1	0	Covered	T4,T7,T14
1	1	Covered	T37,T76,T201

 LINE       450
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T36,T26

 LINE       450
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T36,T26
1	0	Covered	T37,T76,T201

 LINE       455
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T51
1	0	Covered	T4,T7,T14
1	1	Covered	T4,T36,T26

 LINE       480
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T18,T44,T45
1	0	Covered	T10,T23,T43
1	1	Covered	T1,T2,T3

 LINE       486
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : fifo_data_valid)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T14

 LINE       486
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T14
1	1	Covered	T4,T7,T14

 LINE       490
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T7,T14
1	0	1	Covered	T5,T20,T8
1	1	0	Covered	T10,T23,T43
1	1	1	Covered	T4,T7,T14

 LINE       494
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T7,T14
1	1	0	Covered	T208,T184,T219
1	1	1	Covered	T5,T20,T8

 LINE       511
 EXPRESSION (hint_forward & fifo_data_valid)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T14
1	0	Not Covered
1	1	Covered	T5,T20,T8

 LINE       515
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T7,T14

 LINE       518
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T20,T8
1	1	Covered	T4,T7,T14

 LINE       519
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T14
1	1	Covered	T5,T20,T8

 LINE       573
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T64,T75,T182
1	1	0	Covered	T5,T20,T8
1	1	1	Covered	T4,T7,T14

 LINE       574
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T25
1	0	Covered	T4,T7,T14
1	1	Covered	T4,T7,T14

 LINE       590
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T7,T36
1	1	0	Covered	T10,T23,T43
1	1	1	Covered	T4,T7,T14

 LINE       600
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T20,T8

 LINE       600
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T14

 LINE       604
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T20,T8

 LINE       604
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------

-1-	Status	Tests
0	Covered	T5,T20,T8
1	Covered	T1,T2,T3

 LINE       612
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T14
1	0	Covered	T5,T20,T8

 LINE       612
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T14

 LINE       629
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T20,T8

 LINE       629
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T14

 LINE       629
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T14

 LINE       634
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T18,T44,T45
1	0	1	Covered	T14,T16,T59
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T20

 LINE       634
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T20
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       634
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T5,T20
1	1	1	0	Covered	T4,T5,T20
1	1	1	1	Covered	T4,T5,T20

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T5,T20
1	1	1	0	Covered	T4,T5,T20
1	1	1	1	Covered	T4,T5,T20

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T5,T20
1	1	1	0	Covered	T4,T5,T20
1	1	1	1	Covered	T4,T5,T20

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T5,T20
1	1	1	0	Covered	T4,T5,T20
1	1	1	1	Covered	T4,T5,T20

 LINE       650
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T20
0	1	Not Covered
1	0	Not Covered

 LINE       656
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       669
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T37,T75

 LINE       690
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T14

 LINE       690
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T4,T7,T14
1	Covered	T4,T7,T14

 LINE       702
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T20
1	0	Covered	T4,T5,T20

 LINE       705
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T26,T37,T75

 LINE       705
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T14
1	0	Covered	T4,T5,T20
1	1	Covered	T26,T37,T75

 LINE       705
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T4,T7,T14
1	0	0	Covered	T37,T76,T209

 LINE       705
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T20
1	1	Not Covered

 LINE       709
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T14
1	0	Covered	T4,T5,T20
1	1	Covered	T26,T37,T75

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		40	40	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	486	2	2	100.00
TERNARY	600	3	3	100.00
TERNARY	604	3	3	100.00
TERNARY	629	3	3	100.00
TERNARY	656	2	2	100.00
TERNARY	690	2	2	100.00
TERNARY	669	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	576	4	4	100.00
IF	648	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T20

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T20

	LineNo.	Expression
-1-:	301	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T36,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	486	(hint_descram) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	(forward) ? 
-2-:	600	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T20,T8
0	1	Covered	T4,T7,T14
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	604	(forward) ? 
-2-:	604	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T20,T8
0	1	Covered	T1,T2,T3
0	0	Covered	T5,T20,T8

	LineNo.	Expression
-1-:	629	(forward) ? 
-2-:	629	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T20,T8
0	1	Covered	T4,T7,T14
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	656	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	690	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	669	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T26,T37,T75
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T20

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T5,T20

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T20
0	0	1	Covered	T4,T5,T20
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	576	if ((!rst_ni))
-2-:	578	if (calc_req_start)
-3-:	580	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T7,T14
0	0	1	Covered	T4,T7,T14
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	648	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T20
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	410526113	782206	0	0
ExclusiveOps_A	410526113	409700378	0	0
ExclusiveProgHazard_A	410526113	409700378	0	0
ExclusiveState_A	410526113	409700378	0	0
ForwardCheck_A	410526113	1994038	0	0
IdleCheck_A	410526113	50965187	0	0
MaxBufs_A	1059	1059	0	0
OneHotAlloc_A	410526113	409700378	0	0
OneHotMatch_A	410526113	409700378	0	0
OneHotRspMatch_A	410526113	409700378	0	0
OneHotUpdate_A	410526113	409700378	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	782206	0	0
T4	53140	509	0	0
T5	820420	522	0	0
T6	73924	0	0	0
T7	119790	2027	0	0
T8	9296	33	0	0
T9	896819	3150	0	0
T14	378760	0	0	0
T16	0	30	0	0
T20	75683	87	0	0
T21	130853	0	0	0
T24	5019	122	0	0
T36	0	931	0	0
T58	0	101	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	1994038	0	0
T5	820420	523	0	0
T6	73924	0	0	0
T7	119790	0	0	0
T8	9296	43	0	0
T9	896819	12347	0	0
T14	378760	0	0	0
T16	0	45	0	0
T20	75683	103	0	0
T21	130853	0	0	0
T22	59078	0	0	0
T23	0	6	0	0
T24	5019	0	0	0
T47	0	22675	0	0
T58	0	132	0	0
T60	0	30	0	0
T62	0	152	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	50965187	0	0
T4	53140	35488	0	0
T5	820420	1568	0	0
T6	73924	0	0	0
T7	119790	41595	0	0
T8	9296	119	0	0
T9	896819	632847	0	0
T14	378760	524288	0	0
T16	0	524408	0	0
T20	75683	293	0	0
T21	130853	0	0	0
T24	5019	590	0	0
T58	0	365	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		122	122	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	480	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	573	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
ALWAYS	576	6	6	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	590	1	1	100.00
CONT_ASSIGN	593	1	1	100.00
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	612	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	634	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
ALWAYS	645	6	6	100.00
CONT_ASSIGN	656	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	690	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	715	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
480	1	1
486	1	1
490	1	1
494	1	1
511	1	1
515	1	1
518	1	1
519	1	1
573	1	1
574	1	1
576	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
			MISSING_ELSE
586	1	1
590	1	1
593	1	1
600	1	1
604	1	1
612	1	1
629	1	1
634	1	1
639	4	4
645	1	1
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
			MISSING_ELSE
656	1	1
668	1	1
669	1	1
690	1	1
702	1	1
705	1	1
709	1	1
712	1	1
715	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Covered	Percent
Conditions	443	407	91.87
Logical	443	407	91.87
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       139
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       139
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       139
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       140
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       140
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       140
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       140
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       145
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T37,T27,T76
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T37,T27,T76

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       145
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T37,T199,T76
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T200
1	1	1	Covered	T37,T199,T76

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       145
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T37,T76,T202
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T37,T76,T202

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       145
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T37,T76,T202
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T37,T76,T202

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       153
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       153
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       153
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       166
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       166
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       166
 EXPRESSION (req_o & no_match)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T4,T5
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T1,T6,T21
1	1	1	0	1	1	1	Covered	T1,T4,T5
1	1	1	1	0	1	1	Covered	T37,T76,T202
1	1	1	1	1	0	1	Covered	T37
1	1	1	1	1	1	0	Covered	T203,T220,T221
1	1	1	1	1	1	1	Covered	T1,T4,T5

 LINE       195
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       195
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T4,T5
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T1,T6,T21
1	1	1	0	1	1	1	Covered	T1,T4,T5
1	1	1	1	0	1	1	Covered	T37,T202,T204
1	1	1	1	1	0	1	Covered	T205
1	1	1	1	1	1	0	Covered	T110,T76,T219
1	1	1	1	1	1	1	Covered	T1,T4,T5

 LINE       195
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       195
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T4,T5
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T1,T6,T21
1	1	1	0	1	1	1	Covered	T1,T4,T5
1	1	1	1	0	1	1	Covered	T37,T76,T204
1	1	1	1	1	0	1	Covered	T37,T205
1	1	1	1	1	1	0	Covered	T47,T49,T206
1	1	1	1	1	1	1	Covered	T1,T4,T5

 LINE       195
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       195
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T4,T5
1	0	1	1	1	1	1	Covered	T207
1	1	0	1	1	1	1	Covered	T1,T6,T21
1	1	1	0	1	1	1	Covered	T1,T4,T5
1	1	1	1	0	1	1	Covered	T37,T76,T202
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T47,T192,T75
1	1	1	1	1	1	1	Covered	T1,T4,T5

 LINE       195
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       195
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T119,T222,T203
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T75,T110,T76
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T47,T49,T206
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T47,T107,T192
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T20,T8,T9
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T20,T8,T9
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T20,T8,T9
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T20,T8
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       221
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T6
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T20,T6

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T6,T21
0	1	0	Covered	T1,T6,T21
1	0	0	Covered	T20,T60,T63

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T6,T21

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T6,T21

 LINE       221
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T6
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T20,T6

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T6,T21
0	1	0	Covered	T1,T6,T21
1	0	0	Covered	T20,T60,T63

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T6,T21

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T6,T21

 LINE       221
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T6
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T20,T6

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T6,T21
0	1	0	Covered	T1,T6,T21
1	0	0	Covered	T20,T60,T63

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T6,T21

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T6,T21

 LINE       221
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T6
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T20,T6

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T6,T21
0	1	0	Covered	T1,T6,T21
1	0	0	Covered	T20,T60,T63

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T6,T21

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T6,T21

 LINE       231
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T47,T37,T64
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       238
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T47,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       238
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T47,T23,T37
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       238
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T47,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       290
 EXPRESSION (req_o & ack_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T47,T64,T75
1	1	Covered	T1,T2,T3

 LINE       291
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       301
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       304
 EXPRESSION (req_i && rdy_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Covered	T1,T2,T3

 LINE       307
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       376
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       381
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T36
1	0	Covered	T10,T23,T18
1	1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       398
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T4,T7,T10
1	1	1	1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T7,T10
1	1	1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       406
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	Not Covered
1	1	0	1	1	1	Covered	T9,T47,T49
1	1	1	0	1	1	Covered	T10,T23,T11
1	1	1	1	0	1	Covered	T1,T4,T5
1	1	1	1	1	0	Covered	T4,T7,T10
1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       406
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T8
1	1	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T10,T28

 LINE       431
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T20

 LINE       441
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T9,T51,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T37,T27,T199

 LINE       450
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T36,T37

 LINE       450
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T36,T37
1	0	Covered	T37,T27,T199

 LINE       455
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T51
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T36,T37

 LINE       480
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T18,T44,T45
1	0	Covered	T10,T23,T43
1	1	Covered	T1,T2,T3

 LINE       486
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : fifo_data_valid)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       486
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       490
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T20,T8
1	1	0	Covered	T10,T28,T23
1	1	1	Covered	T1,T2,T3

 LINE       494
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T75,T223,T202
1	1	1	Covered	T5,T20,T8

 LINE       511
 EXPRESSION (hint_forward & fifo_data_valid)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T20,T8

 LINE       515
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       518
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T20,T8
1	1	Covered	T1,T2,T3

 LINE       519
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T20,T8

 LINE       573
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T64,T75,T182
1	1	0	Covered	T5,T20,T8
1	1	1	Covered	T1,T2,T3

 LINE       574
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       590
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T7,T36
1	1	0	Covered	T10,T28,T23
1	1	1	Covered	T1,T2,T3

 LINE       600
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T20,T8

 LINE       600
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       604
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T20,T8

 LINE       604
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------

-1-	Status	Tests
0	Covered	T5,T20,T8
1	Covered	T1,T2,T3

 LINE       612
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T8

 LINE       612
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       629
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T20,T8

 LINE       629
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       629
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       634
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T18,T44,T45
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       634
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       634
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T4,T5
1	1	1	0	Covered	T1,T4,T5
1	1	1	1	Covered	T1,T4,T5

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T4,T5
1	1	1	0	Covered	T1,T4,T5
1	1	1	1	Covered	T1,T4,T5

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T4,T5
1	1	1	0	Covered	T1,T4,T5
1	1	1	1	Covered	T1,T4,T5

 LINE       639
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T4,T5
1	1	1	0	Covered	T1,T4,T5
1	1	1	1	Covered	T1,T4,T5

 LINE       650
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T200
1	0	Not Covered

 LINE       656
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       669
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T135,T129,T136

 LINE       690
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       690
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       702
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       705
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T135,T129,T136

 LINE       705
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T135,T129,T136

 LINE       705
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T37,T76,T202

 LINE       705
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T200

 LINE       709
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T135,T129,T136

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		40	40	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	486	2	2	100.00
TERNARY	600	3	3	100.00
TERNARY	604	3	3	100.00
TERNARY	629	3	3	100.00
TERNARY	656	2	2	100.00
TERNARY	690	2	2	100.00
TERNARY	669	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	576	4	4	100.00
IF	648	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	301	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T36,T37
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	486	(hint_descram) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	(forward) ? 
-2-:	600	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T20,T8
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	604	(forward) ? 
-2-:	604	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T20,T8
0	1	Covered	T1,T2,T3
0	0	Covered	T5,T20,T8

	LineNo.	Expression
-1-:	629	(forward) ? 
-2-:	629	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T20,T8
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	656	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	690	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	669	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T135,T129,T136
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	576	if ((!rst_ni))
-2-:	578	if (calc_req_start)
-3-:	580	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	648	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	410526113	831447	0	0
ExclusiveOps_A	410526113	409700378	0	0
ExclusiveProgHazard_A	410526113	409700378	0	0
ExclusiveState_A	410526113	409700378	0	0
ForwardCheck_A	410526113	2482132	0	0
IdleCheck_A	410526113	54252351	0	0
MaxBufs_A	1059	1059	0	0
OneHotAlloc_A	410526113	409700378	0	0
OneHotMatch_A	410526113	409700378	0	0
OneHotRspMatch_A	410526113	409700378	0	0
OneHotUpdate_A	410526113	409700378	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	831447	0	0
T1	202480	1456	0	0
T2	1137	0	0	0
T3	3038	0	0	0
T4	53140	895	0	0
T5	820420	327	0	0
T6	73924	500	0	0
T7	119790	5505	0	0
T8	9296	24	0	0
T9	0	3821	0	0
T20	75683	76	0	0
T21	130853	1364	0	0
T50	0	2168	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	2482132	0	0
T5	820420	340	0	0
T6	73924	0	0	0
T7	119790	0	0	0
T8	9296	31	0	0
T9	896819	12405	0	0
T14	378760	0	0	0
T16	0	56	0	0
T20	75683	92	0	0
T21	130853	0	0	0
T22	59078	0	0	0
T24	5019	0	0	0
T31	0	544	0	0
T52	0	1	0	0
T58	0	55	0	0
T105	0	3	0	0
T210	0	14	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	54252351	0	0
T1	202480	22256	0	0
T2	1137	128	0	0
T3	3038	402	0	0
T4	53140	35524	0	0
T5	820420	1135	0	0
T6	73924	7460	0	0
T7	119790	59735	0	0
T8	9296	214	0	0
T20	75683	388	0	0
T21	130853	20164	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0