Unified Coverage Report :: Module Instance :: tb.dut.u_to_prog_fifo.u_sramreqfifo

Module Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.12	78.57	38.46			71.43	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.86	86.11	54.84			62.50	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.54	93.44	65.77			69.23	85.71	u_to_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	71.04	90.91	66.67			55.56

Module Instance : tb.dut.u_to_prog_fifo.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.27	92.31	47.06			85.71	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.33	91.43	57.14			68.75	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.54	93.44	65.77			69.23	85.71	u_to_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	71.04	90.91	66.67			55.56

Module Instance : tb.dut.u_prog_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.50	97.12	93.60	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_to_rd_fifo.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.49	95.38	77.39			85.19	100.00	u_to_rd_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.49	95.38	77.39			85.19	100.00	u_to_rd_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_to_rd_fifo.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.30	100.00	91.49	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.49	95.38	77.39			85.19	100.00	u_to_rd_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Module Instance : tb.dut.u_sw_rd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.67	95.12	88.64			90.91	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.50	97.12	93.60	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	92.40	92.59	100.00			84.62

Module Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.53	100.00	86.11			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.93	96.92	81.90			88.89	100.00	u_tl_adapter_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.53	100.00	86.11			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.93	96.92	81.90			88.89	100.00	u_tl_adapter_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		14	11	78.57
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	0	0
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101		unreachable
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo

	Total	Covered	Percent
Conditions	13	5	38.46
Logical	13	5	38.46
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Not Covered
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	111	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412769973	0	0	0
DepthKnown_A	412769973	411943476	0	0
RvalidKnown_A	412769973	411943476	0	0
WreadyKnown_A	412769973	411943476	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412769973	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	0	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		13	12	92.31
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	0	0
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100		unreachable
101	1	1
108	0	1
111	1	1
112		unreachable
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo

	Total	Covered	Percent
Conditions	17	8	47.06
Logical	17	8	47.06
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Unreachable

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
TERNARY	130	1	1	100.00
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412769973	0	0	0
DepthKnown_A	412769973	411943476	0	0
RvalidKnown_A	412769973	411943476	0	0
WreadyKnown_A	412769973	411943476	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412769973	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	0	0	0

Line Coverage for Instance : tb.dut.u_prog_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_prog_fifo

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T15,T37,T31
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_prog_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prog_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412769973	194267537	0	0
DepthKnown_A	412769973	411943476	0	0
RvalidKnown_A	412769973	411943476	0	0
WreadyKnown_A	412769973	411943476	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412769973	194267537	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	194267537	0	0
T1	1104	119	0	0
T2	3261	444	0	0
T3	8371	4645	0	0
T6	0	34261	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	0	0	0
T15	2180	882	0	0
T16	3921	0	0	0
T17	1748	444	0	0
T18	567627	565029	0	0
T24	0	105649	0	0
T26	0	26014	0	0
T56	0	32907	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	194267537	0	0
T1	1104	119	0	0
T2	3261	444	0	0
T3	8371	4645	0	0
T6	0	34261	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	0	0	0
T15	2180	882	0	0
T16	3921	0	0	0
T17	1748	444	0	0
T18	567627	565029	0	0
T24	0	105649	0	0
T26	0	26014	0	0
T56	0	32907	0	0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T14
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T14

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T14
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412769973	4402278	0	0
DepthKnown_A	412769973	411943476	0	0
RvalidKnown_A	412769973	411943476	0	0
WreadyKnown_A	412769973	411943476	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412769973	4402278	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	4402278	0	0
T2	3261	62	0	0
T3	8371	177	0	0
T4	0	15744	0	0
T10	643	2	0	0
T11	127622	1318	0	0
T14	5729	195	0	0
T15	2180	20	0	0
T16	3921	0	0	0
T17	1748	0	0	0
T18	567627	0	0	0
T24	0	8037	0	0
T26	0	2364	0	0
T55	2512	146	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	4402278	0	0
T2	3261	62	0	0
T3	8371	177	0	0
T4	0	15744	0	0
T10	643	2	0	0
T11	127622	1318	0	0
T14	5729	195	0	0
T15	2180	20	0	0
T16	3921	0	0	0
T17	1748	0	0	0
T18	567627	0	0	0
T24	0	8037	0	0
T26	0	2364	0	0
T55	2512	146	0	0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T14

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T14
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412769973	3300867	0	0
DepthKnown_A	412769973	411943476	0	0
RvalidKnown_A	412769973	411943476	0	0
WreadyKnown_A	412769973	411943476	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412769973	3300867	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	3300867	0	0
T2	3261	62	0	0
T3	8371	177	0	0
T4	0	15744	0	0
T10	643	2	0	0
T11	127622	1318	0	0
T14	5729	195	0	0
T15	2180	20	0	0
T16	3921	0	0	0
T17	1748	0	0	0
T18	567627	0	0	0
T24	0	8037	0	0
T26	0	2364	0	0
T55	2512	146	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	3300867	0	0
T2	3261	62	0	0
T3	8371	177	0	0
T4	0	15744	0	0
T10	643	2	0	0
T11	127622	1318	0	0
T14	5729	195	0	0
T15	2180	20	0	0
T16	3921	0	0	0
T17	1748	0	0	0
T18	567627	0	0	0
T24	0	8037	0	0
T26	0	2364	0	0
T55	2512	146	0	0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T40,T41
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T12,T13
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T14
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T14

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T14

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T14

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T11,T40,T41
1	0	Covered	T2,T3,T14
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T14
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412569403	4394836	0	0
DepthKnown_A	412769973	411943476	0	0
RvalidKnown_A	412769973	411943476	0	0
WreadyKnown_A	412769973	411943476	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412769973	4411349	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412569403	4394836	0	0
T2	3261	62	0	0
T3	8371	177	0	0
T4	0	15744	0	0
T10	643	2	0	0
T11	87028	403	0	0
T14	5729	195	0	0
T15	2180	20	0	0
T16	3921	0	0	0
T17	1748	0	0	0
T18	567627	0	0	0
T24	0	8037	0	0
T26	0	2364	0	0
T55	2512	146	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	4411349	0	0
T2	3261	62	0	0
T3	8371	177	0	0
T4	0	15744	0	0
T10	643	2	0	0
T11	127622	3381	0	0
T14	5729	195	0	0
T15	2180	20	0	0
T16	3921	0	0	0
T17	1748	0	0	0
T18	567627	0	0	0
T24	0	8037	0	0
T26	0	2364	0	0
T55	2512	146	0	0

Line Coverage for Instance : tb.dut.u_sw_rd_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sw_rd_fifo

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T5,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T14
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T14

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T14

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T14

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T14
1	0	Covered	T2,T3,T14
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T14
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sw_rd_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sw_rd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412769973	48976727	0	0
DepthKnown_A	412769973	411943476	0	0
RvalidKnown_A	412769973	411943476	0	0
WreadyKnown_A	412769973	411943476	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412769973	48976727	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	48976727	0	0
T2	3261	269	0	0
T3	8371	760	0	0
T4	0	97224	0	0
T10	643	10	0	0
T11	127622	1793	0	0
T14	5729	847	0	0
T15	2180	40	0	0
T16	3921	0	0	0
T17	1748	0	0	0
T18	567627	0	0	0
T24	0	113129	0	0
T26	0	33103	0	0
T55	2512	604	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	48976727	0	0
T2	3261	269	0	0
T3	8371	760	0	0
T4	0	97224	0	0
T10	643	10	0	0
T11	127622	1793	0	0
T14	5729	847	0	0
T15	2180	40	0	0
T16	3921	0	0	0
T17	1748	0	0	0
T18	567627	0	0	0
T24	0	113129	0	0
T26	0	33103	0	0
T55	2512	604	0	0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T14
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T14

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T14
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412769973	35733684	0	0
DepthKnown_A	412769973	411943476	0	0
RvalidKnown_A	412769973	411943476	0	0
WreadyKnown_A	412769973	411943476	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412769973	35733684	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	35733684	0	0
T2	3261	28	0	0
T3	8371	35	0	0
T4	0	46219	0	0
T5	0	45970	0	0
T6	0	193	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	27	0	0
T15	2180	0	0	0
T16	3921	0	0	0
T17	1748	0	0	0
T18	567627	0	0	0
T19	0	3595	0	0
T30	0	32489	0	0
T33	0	117639	0	0
T55	2512	0	0	0
T57	0	130891	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	35733684	0	0
T2	3261	28	0	0
T3	8371	35	0	0
T4	0	46219	0	0
T5	0	45970	0	0
T6	0	193	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	27	0	0
T15	2180	0	0	0
T16	3921	0	0	0
T17	1748	0	0	0
T18	567627	0	0	0
T19	0	3595	0	0
T30	0	32489	0	0
T33	0	117639	0	0
T55	2512	0	0	0
T57	0	130891	0	0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T14
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T14

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T14
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412769973	35064167	0	0
DepthKnown_A	412769973	411943476	0	0
RvalidKnown_A	412769973	411943476	0	0
WreadyKnown_A	412769973	411943476	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412769973	35064167	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	35064167	0	0
T2	3261	28	0	0
T3	8371	35	0	0
T4	0	46219	0	0
T5	0	45970	0	0
T6	0	193	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	27	0	0
T15	2180	0	0	0
T16	3921	0	0	0
T17	1748	0	0	0
T18	567627	0	0	0
T19	0	514	0	0
T30	0	32489	0	0
T33	0	117639	0	0
T55	2512	0	0	0
T57	0	130891	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	35064167	0	0
T2	3261	28	0	0
T3	8371	35	0	0
T4	0	46219	0	0
T5	0	45970	0	0
T6	0	193	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	27	0	0
T15	2180	0	0	0
T16	3921	0	0	0
T17	1748	0	0	0
T18	567627	0	0	0
T19	0	514	0	0
T30	0	32489	0	0
T33	0	117639	0	0
T55	2512	0	0	0
T57	0	130891	0	0