Design subhierarchy
dashboard | hierarchy | modlist | groups | tests | asserts

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NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
flash_ctrl_core_csr_assert 100.00 100.00
gen_alert_senders[0].u_alert_sender 100.00 100.00
gen_alert_senders[1].u_alert_sender 100.00 100.00
gen_alert_senders[2].u_alert_sender 100.00 100.00
gen_alert_senders[3].u_alert_sender 100.00 100.00
gen_alert_senders[4].u_alert_sender 77.78 77.78
tlul_assert_device 99.77 100.00 100.00 99.30
 u_ctrl_arb 100.00 100.00 100.00 100.00 100.00 100.00
 u_disable_buf 100.00 100.00 100.00
 u_eflash 97.11 98.09 93.27 99.49 96.43 97.90 97.49
 u_exec_en_buf 100.00 100.00
u_flash_ctrl_erase 100.00 100.00 100.00 100.00
 u_flash_ctrl_prog 97.88 100.00 97.06 100.00 94.44
 u_flash_ctrl_rd 93.49 83.02 93.94 100.00 100.00 90.48
 u_flash_hw_if 95.46 98.53 91.67 95.83 92.11 94.59 100.00
 u_flash_mp 99.39 100.00 97.55 100.00 100.00
u_intr_corr_err 93.75 100.00 75.00 100.00 100.00
u_intr_op_done 93.75 100.00 75.00 100.00 100.00
u_intr_prog_empty 86.94 90.00 77.78 80.00 100.00
u_intr_prog_lvl 86.94 90.00 77.78 80.00 100.00
u_intr_rd_full 86.94 90.00 77.78 80.00 100.00
u_intr_rd_lvl 86.94 90.00 77.78 80.00 100.00
 u_lc_escalation_en_sync 100.00 100.00 100.00 100.00
 u_lc_seed_hw_rd_en_sync 100.00 100.00 100.00 100.00
u_lfsr 100.00 100.00
 u_prog_fifo 97.73 100.00 90.91 100.00 100.00
 u_prog_tl_gate 83.73 95.45 90.00 57.14 88.57 87.50
 u_reg_core 99.24 98.96 98.41 100.00 98.85 100.00
 u_reg_idle 100.00 100.00 100.00
 u_region_cfg 87.91 63.73 100.00 100.00
 u_sw_rd_fifo 93.67 95.12 88.64 90.91 100.00
 u_tl_adapter_eflash 92.40 89.47 82.40 100.00 90.11 100.00
 u_tl_gate 79.15 93.94 80.00 57.14 77.14 87.50
 u_to_prog_fifo 73.88 82.67 64.92 66.67 81.25
 u_to_rd_fifo 88.76 85.78 77.32 100.00 80.72 100.00