Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.96 52.96 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.96 52.96 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.96 52.96 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.96 52.96 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.50 97.12 93.60 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.53 99.17 90.62 92.11 95.74 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
72.41 88.24 83.33 57.14 83.33 50.00 u_prog_tl_gate


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_lc_escalation_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.50 97.12 93.60 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_tl_gate.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
72.29 86.27 88.89 57.14 79.17 50.00 u_tl_gate


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.89 97.67 84.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

SCORELINE
100.00 100.00
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

SCORELINE
100.00 100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

SCORELINE
100.00 100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

SCORELINE
100.00 100.00
tb.dut.u_lc_seed_hw_rd_en_sync

SCORELINE
100.00 100.00
tb.dut.u_lc_escalation_en_sync

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_flash_hw_if.u_sync_rma_req

Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 3 3


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prog_tl_gate.u_err_en_sync

SCORELINE
100.00 100.00
tb.dut.u_tl_gate.u_err_en_sync

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=5,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync

Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 5 5


Assert Coverage for Module : prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 10630 10630 0 0
OutputsKnown_A 2147483647 2147483647 0 0
gen_flops.OutputDelay_A 2147483647 2147483647 0 22074
gen_no_flops.OutputDelay_A 812094646 810441652 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10630 10630 0 0
T1 10 10 0 0
T2 10 10 0 0
T3 10 10 0 0
T10 10 10 0 0
T11 10 10 0 0
T14 10 10 0 0
T15 10 10 0 0
T16 10 10 0 0
T17 10 10 0 0
T18 10 10 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 10416 9526 0 0
T2 32610 30960 0 0
T3 83710 81870 0 0
T10 6230 5660 0 0
T11 1276220 1023780 0 0
T14 57290 55730 0 0
T15 21800 21170 0 0
T16 39210 31400 0 0
T17 17480 16930 0 0
T18 5676270 5676180 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 22074
T1 8208 7475 0 21
T2 26088 24720 0 24
T3 66968 65448 0 24
T4 0 0 0 3
T10 4944 4467 0 21
T11 1020976 810840 0 24
T14 45832 44536 0 24
T15 17440 16912 0 24
T16 31368 24904 0 24
T17 13984 13520 0 24
T18 4541016 4540944 0 24
T55 0 0 0 3

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 812094646 810441652 0 0
T1 2208 2030 0 0
T2 6522 6192 0 0
T3 16742 16374 0 0
T10 1286 1172 0 0
T11 255244 204756 0 0
T14 11458 11146 0 0
T15 4360 4234 0 0
T16 7842 6280 0 0
T17 3496 3386 0 0
T18 1135254 1135236 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1063 1063 0 0
OutputsKnown_A 406047458 405220961 0 0
gen_flops.OutputDelay_A 406047458 405188654 0 2778


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1063 1063 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406047458 405220961 0 0
T1 1104 1015 0 0
T2 3261 3096 0 0
T3 8371 8187 0 0
T10 643 586 0 0
T11 127622 102378 0 0
T14 5729 5573 0 0
T15 2180 2117 0 0
T16 3921 3140 0 0
T17 1748 1693 0 0
T18 567627 567618 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406047458 405188654 0 2778
T1 1104 1012 0 3
T2 3261 3090 0 3
T3 8371 8181 0 3
T10 643 583 0 3
T11 127622 101355 0 3
T14 5729 5567 0 3
T15 2180 2114 0 3
T16 3921 3113 0 3
T17 1748 1690 0 3
T18 567627 567618 0 3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1063 1063 0 0
OutputsKnown_A 406047458 405220961 0 0
gen_flops.OutputDelay_A 406047458 405188654 0 2778


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1063 1063 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406047458 405220961 0 0
T1 1104 1015 0 0
T2 3261 3096 0 0
T3 8371 8187 0 0
T10 643 586 0 0
T11 127622 102378 0 0
T14 5729 5573 0 0
T15 2180 2117 0 0
T16 3921 3140 0 0
T17 1748 1693 0 0
T18 567627 567618 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406047458 405188654 0 2778
T1 1104 1012 0 3
T2 3261 3090 0 3
T3 8371 8181 0 3
T10 643 583 0 3
T11 127622 101355 0 3
T14 5729 5567 0 3
T15 2180 2114 0 3
T16 3921 3113 0 3
T17 1748 1690 0 3
T18 567627 567618 0 3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1063 1063 0 0
OutputsKnown_A 406047458 405220961 0 0
gen_flops.OutputDelay_A 406047458 405188654 0 2778


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1063 1063 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406047458 405220961 0 0
T1 1104 1015 0 0
T2 3261 3096 0 0
T3 8371 8187 0 0
T10 643 586 0 0
T11 127622 102378 0 0
T14 5729 5573 0 0
T15 2180 2117 0 0
T16 3921 3140 0 0
T17 1748 1693 0 0
T18 567627 567618 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406047458 405188654 0 2778
T1 1104 1012 0 3
T2 3261 3090 0 3
T3 8371 8181 0 3
T10 643 583 0 3
T11 127622 101355 0 3
T14 5729 5567 0 3
T15 2180 2114 0 3
T16 3921 3113 0 3
T17 1748 1690 0 3
T18 567627 567618 0 3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1063 1063 0 0
OutputsKnown_A 406047458 405220961 0 0
gen_flops.OutputDelay_A 406047458 405188654 0 2778


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1063 1063 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406047458 405220961 0 0
T1 1104 1015 0 0
T2 3261 3096 0 0
T3 8371 8187 0 0
T10 643 586 0 0
T11 127622 102378 0 0
T14 5729 5573 0 0
T15 2180 2117 0 0
T16 3921 3140 0 0
T17 1748 1693 0 0
T18 567627 567618 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406047458 405188654 0 2778
T1 1104 1012 0 3
T2 3261 3090 0 3
T3 8371 8181 0 3
T10 643 583 0 3
T11 127622 101355 0 3
T14 5729 5567 0 3
T15 2180 2114 0 3
T16 3921 3113 0 3
T17 1748 1690 0 3
T18 567627 567618 0 3

Line Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1063 1063 0 0
OutputsKnown_A 406047458 405220961 0 0
gen_flops.OutputDelay_A 406047458 405188654 0 2778


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1063 1063 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406047458 405220961 0 0
T1 1104 1015 0 0
T2 3261 3096 0 0
T3 8371 8187 0 0
T10 643 586 0 0
T11 127622 102378 0 0
T14 5729 5573 0 0
T15 2180 2117 0 0
T16 3921 3140 0 0
T17 1748 1693 0 0
T18 567627 567618 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406047458 405188654 0 2778
T1 1104 1012 0 3
T2 3261 3090 0 3
T3 8371 8181 0 3
T10 643 583 0 3
T11 127622 101355 0 3
T14 5729 5567 0 3
T15 2180 2114 0 3
T16 3921 3113 0 3
T17 1748 1690 0 3
T18 567627 567618 0 3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req
Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 3 3


Assert Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1063 1063 0 0
OutputsKnown_A 406047458 405220961 0 0
gen_flops.OutputDelay_A 406047458 405188654 0 2778


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1063 1063 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406047458 405220961 0 0
T1 1104 1015 0 0
T2 3261 3096 0 0
T3 8371 8187 0 0
T10 643 586 0 0
T11 127622 102378 0 0
T14 5729 5573 0 0
T15 2180 2117 0 0
T16 3921 3140 0 0
T17 1748 1693 0 0
T18 567627 567618 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406047458 405188654 0 2778
T1 1104 1012 0 3
T2 3261 3090 0 3
T3 8371 8181 0 3
T10 643 583 0 3
T11 127622 101355 0 3
T14 5729 5567 0 3
T15 2180 2114 0 3
T16 3921 3113 0 3
T17 1748 1690 0 3
T18 567627 567618 0 3

Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1063 1063 0 0
OutputsKnown_A 406047323 405220826 0 0
gen_no_flops.OutputDelay_A 406047323 405220826 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1063 1063 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406047323 405220826 0 0
T1 1104 1015 0 0
T2 3261 3096 0 0
T3 8371 8187 0 0
T10 643 586 0 0
T11 127622 102378 0 0
T14 5729 5573 0 0
T15 2180 2117 0 0
T16 3921 3140 0 0
T17 1748 1693 0 0
T18 567627 567618 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406047323 405220826 0 0
T1 1104 1015 0 0
T2 3261 3096 0 0
T3 8371 8187 0 0
T10 643 586 0 0
T11 127622 102378 0 0
T14 5729 5573 0 0
T15 2180 2117 0 0
T16 3921 3140 0 0
T17 1748 1693 0 0
T18 567627 567618 0 0

Line Coverage for Instance : tb.dut.u_lc_escalation_en_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_lc_escalation_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1063 1063 0 0
OutputsKnown_A 406023885 405197388 0 0
gen_flops.OutputDelay_A 406023885 405165231 0 2628


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1063 1063 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406023885 405197388 0 0
T1 480 391 0 0
T2 3261 3096 0 0
T3 8371 8187 0 0
T10 443 386 0 0
T11 127622 102378 0 0
T14 5729 5573 0 0
T15 2180 2117 0 0
T16 3921 3140 0 0
T17 1748 1693 0 0
T18 567627 567618 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406023885 405165231 0 2628
T1 480 391 0 0
T2 3261 3090 0 3
T3 8371 8181 0 3
T4 0 0 0 3
T10 443 386 0 0
T11 127622 101355 0 3
T14 5729 5567 0 3
T15 2180 2114 0 3
T16 3921 3113 0 3
T17 1748 1690 0 3
T18 567627 567618 0 3
T55 0 0 0 3

Line Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1063 1063 0 0
OutputsKnown_A 406047323 405220826 0 0
gen_no_flops.OutputDelay_A 406047323 405220826 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1063 1063 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406047323 405220826 0 0
T1 1104 1015 0 0
T2 3261 3096 0 0
T3 8371 8187 0 0
T10 643 586 0 0
T11 127622 102378 0 0
T14 5729 5573 0 0
T15 2180 2117 0 0
T16 3921 3140 0 0
T17 1748 1693 0 0
T18 567627 567618 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406047323 405220826 0 0
T1 1104 1015 0 0
T2 3261 3096 0 0
T3 8371 8187 0 0
T10 643 586 0 0
T11 127622 102378 0 0
T14 5729 5573 0 0
T15 2180 2117 0 0
T16 3921 3140 0 0
T17 1748 1693 0 0
T18 567627 567618 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync
Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 5 5


Assert Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1063 1063 0 0
OutputsKnown_A 406047323 405220826 0 0
gen_flops.OutputDelay_A 406047323 405188534 0 2778


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1063 1063 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406047323 405220826 0 0
T1 1104 1015 0 0
T2 3261 3096 0 0
T3 8371 8187 0 0
T10 643 586 0 0
T11 127622 102378 0 0
T14 5729 5573 0 0
T15 2180 2117 0 0
T16 3921 3140 0 0
T17 1748 1693 0 0
T18 567627 567618 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406047323 405188534 0 2778
T1 1104 1012 0 3
T2 3261 3090 0 3
T3 8371 8181 0 3
T10 643 583 0 3
T11 127622 101355 0 3
T14 5729 5567 0 3
T15 2180 2114 0 3
T16 3921 3113 0 3
T17 1748 1690 0 3
T18 567627 567618 0 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%