Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.50	97.12	93.60	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	87	87	100.00	87	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	87	87	100.00	87	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	415549248	3706	0	0
addr_rd_A	415549248	1363	0	0
bank0_info0_page_cfg_0_rd_A	415549248	1788	0	0
bank0_info0_page_cfg_1_rd_A	415549248	1749	0	0
bank0_info0_page_cfg_2_rd_A	415549248	1903	0	0
bank0_info0_page_cfg_3_rd_A	415549248	1655	0	0
bank0_info0_page_cfg_4_rd_A	415549248	1670	0	0
bank0_info0_page_cfg_5_rd_A	415549248	1675	0	0
bank0_info0_page_cfg_6_rd_A	415549248	1812	0	0
bank0_info0_page_cfg_7_rd_A	415549248	1689	0	0
bank0_info0_page_cfg_8_rd_A	415549248	1670	0	0
bank0_info0_page_cfg_9_rd_A	415549248	1664	0	0
bank0_info0_regwen_0_rd_A	415549248	1352	0	0
bank0_info0_regwen_1_rd_A	415549248	1446	0	0
bank0_info0_regwen_2_rd_A	415549248	1370	0	0
bank0_info0_regwen_3_rd_A	415549248	1483	0	0
bank0_info0_regwen_4_rd_A	415549248	1338	0	0
bank0_info0_regwen_5_rd_A	415549248	1393	0	0
bank0_info0_regwen_6_rd_A	415549248	1354	0	0
bank0_info0_regwen_7_rd_A	415549248	1353	0	0
bank0_info0_regwen_8_rd_A	415549248	1304	0	0
bank0_info0_regwen_9_rd_A	415549248	1480	0	0
bank0_info1_page_cfg_rd_A	415549248	1705	0	0
bank0_info1_regwen_rd_A	415549248	1382	0	0
bank0_info2_page_cfg_0_rd_A	415549248	1823	0	0
bank0_info2_page_cfg_1_rd_A	415549248	1703	0	0
bank0_info2_regwen_0_rd_A	415549248	1369	0	0
bank0_info2_regwen_1_rd_A	415549248	1303	0	0
bank1_info0_page_cfg_0_rd_A	415549248	1782	0	0
bank1_info0_page_cfg_1_rd_A	415549248	1898	0	0
bank1_info0_page_cfg_2_rd_A	415549248	1740	0	0
bank1_info0_page_cfg_3_rd_A	415549248	1667	0	0
bank1_info0_page_cfg_4_rd_A	415549248	1735	0	0
bank1_info0_page_cfg_5_rd_A	415549248	1818	0	0
bank1_info0_page_cfg_6_rd_A	415549248	1796	0	0
bank1_info0_page_cfg_7_rd_A	415549248	1882	0	0
bank1_info0_page_cfg_8_rd_A	415549248	1765	0	0
bank1_info0_page_cfg_9_rd_A	415549248	1815	0	0
bank1_info0_regwen_0_rd_A	415549248	1320	0	0
bank1_info0_regwen_1_rd_A	415549248	1334	0	0
bank1_info0_regwen_2_rd_A	415549248	1415	0	0
bank1_info0_regwen_3_rd_A	415549248	1461	0	0
bank1_info0_regwen_4_rd_A	415549248	1483	0	0
bank1_info0_regwen_5_rd_A	415549248	1368	0	0
bank1_info0_regwen_6_rd_A	415549248	1291	0	0
bank1_info0_regwen_7_rd_A	415549248	1428	0	0
bank1_info0_regwen_8_rd_A	415549248	1380	0	0
bank1_info0_regwen_9_rd_A	415549248	1360	0	0
bank1_info1_page_cfg_rd_A	415549248	1711	0	0
bank1_info1_regwen_rd_A	415549248	1375	0	0
bank1_info2_page_cfg_0_rd_A	415549248	1736	0	0
bank1_info2_page_cfg_1_rd_A	415549248	1686	0	0
bank1_info2_regwen_0_rd_A	415549248	1397	0	0
bank1_info2_regwen_1_rd_A	415549248	1301	0	0
bank_cfg_regwen_rd_A	415549248	1329	0	0
default_region_rd_A	415549248	1781	0	0
exec_rd_A	415549248	1407	0	0
fifo_lvl_rd_A	415549248	1518	0	0
fifo_rst_rd_A	415549248	1336	0	0
hw_info_cfg_override_rd_A	415549248	1477	0	0
intr_enable_rd_A	415549248	1592	0	0
mp_region_0_rd_A	415549248	1464	0	0
mp_region_1_rd_A	415549248	1409	0	0
mp_region_2_rd_A	415549248	1362	0	0
mp_region_3_rd_A	415549248	1576	0	0
mp_region_4_rd_A	415549248	1369	0	0
mp_region_5_rd_A	415549248	1554	0	0
mp_region_6_rd_A	415549248	1413	0	0
mp_region_7_rd_A	415549248	1392	0	0
mp_region_cfg_0_rd_A	415549248	1675	0	0
mp_region_cfg_1_rd_A	415549248	1812	0	0
mp_region_cfg_2_rd_A	415549248	1829	0	0
mp_region_cfg_3_rd_A	415549248	1570	0	0
mp_region_cfg_4_rd_A	415549248	1802	0	0
mp_region_cfg_5_rd_A	415549248	1888	0	0
mp_region_cfg_6_rd_A	415549248	1930	0	0
mp_region_cfg_7_rd_A	415549248	1815	0	0
phy_alert_cfg_rd_A	415549248	134	0	0
region_cfg_regwen_0_rd_A	415549248	1365	0	0
region_cfg_regwen_1_rd_A	415549248	1415	0	0
region_cfg_regwen_2_rd_A	415549248	1273	0	0
region_cfg_regwen_3_rd_A	415549248	1452	0	0
region_cfg_regwen_4_rd_A	415549248	1431	0	0
region_cfg_regwen_5_rd_A	415549248	1358	0	0
region_cfg_regwen_6_rd_A	415549248	1475	0	0
region_cfg_regwen_7_rd_A	415549248	1455	0	0
scratch_rd_A	415549248	1434	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	3706	0	0
T170	2787	247	0	0
T171	5438	2	0	0
T172	3674	9	0	0
T173	2208	42	0	0
T207	4104	262	0	0
T208	2674	20	0	0
T209	3397	79	0	0
T221	4949	186	0	0
T222	2390	2	0	0
T223	4605	205	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1363	0	0
T62	4448	3	0	0
T237	3552	8	0	0
T242	6206	12	0	0
T273	8968	15	0	0
T274	38572	42	0	0
T275	5449	9	0	0
T276	5300	10	0	0
T277	4079	7	0	0
T278	4955	10	0	0
T279	9467	24	0	0

bank0_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1788	0	0
T62	4448	3	0	0
T242	6206	70	0	0
T273	8968	8	0	0
T274	38572	117	0	0
T275	5449	9	0	0
T276	5300	21	0	0
T277	4079	27	0	0
T278	4955	12	0	0
T280	3973	4	0	0
T281	5149	6	0	0

bank0_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1749	0	0
T62	4448	12	0	0
T237	3552	6	0	0
T242	6206	10	0	0
T273	8968	47	0	0
T274	38572	134	0	0
T275	5449	28	0	0
T276	5300	40	0	0
T277	4079	5	0	0
T278	4955	4	0	0
T280	3973	11	0	0

bank0_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1903	0	0
T62	4448	9	0	0
T242	6206	3	0	0
T273	8968	55	0	0
T274	38572	209	0	0
T275	5449	36	0	0
T276	5300	2	0	0
T277	4079	28	0	0
T278	4955	11	0	0
T280	3973	17	0	0
T281	5149	19	0	0

bank0_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1655	0	0
T237	3552	6	0	0
T242	6206	37	0	0
T273	8968	50	0	0
T274	38572	134	0	0
T275	5449	40	0	0
T276	5300	13	0	0
T277	4079	8	0	0
T278	4955	26	0	0
T279	9467	35	0	0
T280	3973	3	0	0

bank0_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1670	0	0
T62	4448	8	0	0
T237	3552	8	0	0
T242	6206	35	0	0
T273	8968	6	0	0
T274	38572	138	0	0
T275	5449	5	0	0
T276	5300	4	0	0
T277	4079	18	0	0
T280	3973	14	0	0
T281	5149	3	0	0

bank0_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1675	0	0
T62	4448	5	0	0
T237	3552	2	0	0
T242	6206	13	0	0
T273	8968	5	0	0
T274	38572	119	0	0
T275	5449	6	0	0
T276	5300	34	0	0
T277	4079	32	0	0
T278	4955	25	0	0
T280	3973	15	0	0

bank0_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1812	0	0
T62	4448	5	0	0
T242	6206	24	0	0
T273	8968	14	0	0
T274	38572	164	0	0
T275	5449	54	0	0
T276	5300	3	0	0
T277	4079	36	0	0
T278	4955	7	0	0
T280	3973	6	0	0
T281	5149	10	0	0

bank0_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1689	0	0
T237	3552	19	0	0
T242	6206	13	0	0
T273	8968	14	0	0
T274	38572	158	0	0
T275	5449	16	0	0
T276	5300	22	0	0
T277	4079	2	0	0
T278	4955	6	0	0
T280	3973	8	0	0
T281	5149	15	0	0

bank0_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1670	0	0
T62	4448	15	0	0
T242	6206	26	0	0
T273	8968	11	0	0
T274	38572	158	0	0
T275	5449	37	0	0
T276	5300	8	0	0
T277	4079	29	0	0
T278	4955	33	0	0
T279	9467	26	0	0
T281	5149	6	0	0

bank0_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1664	0	0
T242	6206	23	0	0
T273	8968	10	0	0
T274	38572	188	0	0
T275	5449	17	0	0
T276	5300	29	0	0
T277	4079	4	0	0
T278	4955	8	0	0
T279	9467	42	0	0
T281	5149	4	0	0
T282	328145	421	0	0

bank0_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1352	0	0
T62	4448	3	0	0
T237	3552	7	0	0
T242	6206	6	0	0
T273	8968	2	0	0
T274	38572	46	0	0
T275	5449	8	0	0
T276	5300	10	0	0
T277	4079	6	0	0
T280	3973	2	0	0
T281	5149	2	0	0

bank0_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1446	0	0
T237	3552	1	0	0
T242	6206	5	0	0
T273	8968	17	0	0
T274	38572	26	0	0
T275	5449	12	0	0
T276	5300	14	0	0
T277	4079	8	0	0
T278	4955	7	0	0
T280	3973	3	0	0
T281	5149	1	0	0

bank0_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1370	0	0
T242	6206	5	0	0
T273	8968	13	0	0
T274	38572	40	0	0
T275	5449	13	0	0
T276	5300	7	0	0
T277	4079	9	0	0
T278	4955	6	0	0
T279	9467	19	0	0
T281	5149	6	0	0
T283	4003	7	0	0

bank0_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1483	0	0
T62	4448	5	0	0
T237	3552	4	0	0
T242	6206	5	0	0
T273	8968	10	0	0
T274	38572	39	0	0
T275	5449	6	0	0
T276	5300	14	0	0
T277	4079	8	0	0
T278	4955	7	0	0
T281	5149	6	0	0

bank0_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1338	0	0
T62	4448	6	0	0
T237	3552	3	0	0
T242	6206	9	0	0
T273	8968	3	0	0
T274	38572	49	0	0
T275	5449	16	0	0
T276	5300	6	0	0
T278	4955	7	0	0
T279	9467	19	0	0
T283	4003	7	0	0

bank0_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1393	0	0
T62	4448	3	0	0
T242	6206	15	0	0
T274	38572	43	0	0
T275	5449	12	0	0
T276	5300	7	0	0
T278	4955	15	0	0
T279	9467	11	0	0
T281	5149	14	0	0
T282	328145	455	0	0
T283	4003	6	0	0

bank0_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1354	0	0
T62	4448	4	0	0
T237	3552	4	0	0
T242	6206	6	0	0
T273	8968	9	0	0
T274	38572	41	0	0
T275	5449	10	0	0
T276	5300	6	0	0
T277	4079	3	0	0
T280	3973	4	0	0
T281	5149	4	0	0

bank0_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1353	0	0
T62	4448	11	0	0
T273	8968	5	0	0
T274	38572	40	0	0
T275	5449	9	0	0
T276	5300	9	0	0
T277	4079	5	0	0
T278	4955	3	0	0
T279	9467	20	0	0
T280	3973	2	0	0
T283	4003	3	0	0

bank0_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1304	0	0
T62	4448	3	0	0
T237	3552	3	0	0
T242	6206	8	0	0
T273	8968	4	0	0
T274	38572	28	0	0
T275	5449	2	0	0
T276	5300	3	0	0
T278	4955	7	0	0
T280	3973	3	0	0
T281	5149	4	0	0

bank0_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1480	0	0
T62	4448	2	0	0
T237	3552	9	0	0
T242	6206	8	0	0
T273	8968	1	0	0
T274	38572	26	0	0
T275	5449	4	0	0
T276	5300	10	0	0
T277	4079	6	0	0
T278	4955	10	0	0
T280	3973	7	0	0

bank0_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1705	0	0
T62	4448	2	0	0
T237	3552	1	0	0
T242	6206	20	0	0
T273	8968	20	0	0
T274	38572	150	0	0
T275	5449	4	0	0
T276	5300	4	0	0
T277	4079	25	0	0
T278	4955	38	0	0
T281	5149	2	0	0

bank0_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1382	0	0
T62	4448	8	0	0
T237	3552	8	0	0
T242	6206	7	0	0
T273	8968	1	0	0
T274	38572	32	0	0
T275	5449	7	0	0
T276	5300	10	0	0
T277	4079	9	0	0
T280	3973	2	0	0
T281	5149	16	0	0

bank0_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1823	0	0
T62	4448	8	0	0
T237	3552	10	0	0
T242	6206	54	0	0
T273	8968	37	0	0
T274	38572	154	0	0
T275	5449	30	0	0
T276	5300	45	0	0
T278	4955	5	0	0
T279	9467	43	0	0
T281	5149	5	0	0

bank0_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1703	0	0
T237	3552	18	0	0
T242	6206	15	0	0
T273	8968	39	0	0
T274	38572	172	0	0
T275	5449	8	0	0
T276	5300	12	0	0
T277	4079	23	0	0
T278	4955	11	0	0
T280	3973	30	0	0
T281	5149	7	0	0

bank0_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1369	0	0
T62	4448	9	0	0
T242	6206	5	0	0
T273	8968	7	0	0
T274	38572	33	0	0
T275	5449	8	0	0
T276	5300	7	0	0
T277	4079	1	0	0
T278	4955	13	0	0
T279	9467	16	0	0
T281	5149	1	0	0

bank0_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1303	0	0
T62	4448	4	0	0
T237	3552	1	0	0
T242	6206	14	0	0
T273	8968	14	0	0
T274	38572	60	0	0
T275	5449	5	0	0
T276	5300	8	0	0
T277	4079	8	0	0
T280	3973	5	0	0
T281	5149	2	0	0

bank1_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1782	0	0
T62	4448	9	0	0
T237	3552	23	0	0
T242	6206	33	0	0
T273	8968	30	0	0
T274	38572	107	0	0
T275	5449	8	0	0
T276	5300	21	0	0
T277	4079	1	0	0
T278	4955	2	0	0
T281	5149	17	0	0

bank1_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1898	0	0
T62	4448	3	0	0
T242	6206	35	0	0
T273	8968	24	0	0
T274	38572	133	0	0
T275	5449	21	0	0
T276	5300	33	0	0
T277	4079	39	0	0
T278	4955	5	0	0
T279	9467	57	0	0
T281	5149	14	0	0

bank1_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1740	0	0
T62	4448	1	0	0
T237	3552	5	0	0
T242	6206	36	0	0
T273	8968	36	0	0
T274	38572	99	0	0
T275	5449	3	0	0
T276	5300	18	0	0
T277	4079	19	0	0
T280	3973	7	0	0
T281	5149	10	0	0

bank1_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1667	0	0
T62	4448	8	0	0
T237	3552	9	0	0
T242	6206	44	0	0
T273	8968	20	0	0
T274	38572	107	0	0
T275	5449	6	0	0
T276	5300	26	0	0
T278	4955	26	0	0
T280	3973	9	0	0
T281	5149	7	0	0

bank1_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1735	0	0
T62	4448	8	0	0
T237	3552	22	0	0
T242	6206	4	0	0
T273	8968	34	0	0
T274	38572	168	0	0
T275	5449	23	0	0
T276	5300	6	0	0
T277	4079	9	0	0
T278	4955	28	0	0
T281	5149	12	0	0

bank1_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1818	0	0
T237	3552	15	0	0
T242	6206	20	0	0
T273	8968	26	0	0
T274	38572	140	0	0
T275	5449	3	0	0
T276	5300	36	0	0
T277	4079	28	0	0
T278	4955	8	0	0
T280	3973	20	0	0
T281	5149	20	0	0

bank1_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1796	0	0
T62	4448	2	0	0
T237	3552	5	0	0
T242	6206	38	0	0
T273	8968	2	0	0
T274	38572	144	0	0
T275	5449	18	0	0
T276	5300	10	0	0
T277	4079	51	0	0
T280	3973	5	0	0
T281	5149	12	0	0

bank1_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1882	0	0
T237	3552	16	0	0
T242	6206	29	0	0
T274	38572	173	0	0
T275	5449	8	0	0
T276	5300	8	0	0
T277	4079	20	0	0
T278	4955	34	0	0
T279	9467	26	0	0
T280	3973	25	0	0
T281	5149	12	0	0

bank1_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1765	0	0
T62	4448	7	0	0
T237	3552	1	0	0
T242	6206	13	0	0
T273	8968	5	0	0
T274	38572	230	0	0
T275	5449	3	0	0
T276	5300	2	0	0
T277	4079	44	0	0
T280	3973	10	0	0
T281	5149	20	0	0

bank1_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1815	0	0
T62	4448	7	0	0
T237	3552	8	0	0
T242	6206	67	0	0
T273	8968	18	0	0
T274	38572	158	0	0
T275	5449	6	0	0
T276	5300	3	0	0
T277	4079	27	0	0
T278	4955	32	0	0
T279	9467	78	0	0

bank1_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1320	0	0
T62	4448	6	0	0
T237	3552	7	0	0
T242	6206	10	0	0
T273	8968	15	0	0
T274	38572	28	0	0
T275	5449	5	0	0
T276	5300	12	0	0
T277	4079	5	0	0
T278	4955	9	0	0
T280	3973	1	0	0

bank1_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1334	0	0
T242	6206	3	0	0
T273	8968	5	0	0
T274	38572	26	0	0
T275	5449	10	0	0
T276	5300	4	0	0
T277	4079	7	0	0
T278	4955	9	0	0
T279	9467	16	0	0
T280	3973	6	0	0
T283	4003	7	0	0

bank1_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1415	0	0
T62	4448	16	0	0
T242	6206	7	0	0
T273	8968	17	0	0
T274	38572	43	0	0
T275	5449	12	0	0
T276	5300	12	0	0
T278	4955	12	0	0
T279	9467	25	0	0
T280	3973	7	0	0
T281	5149	2	0	0

bank1_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1461	0	0
T62	4448	1	0	0
T237	3552	1	0	0
T242	6206	4	0	0
T273	8968	14	0	0
T274	38572	41	0	0
T275	5449	9	0	0
T276	5300	7	0	0
T277	4079	4	0	0
T278	4955	11	0	0
T281	5149	9	0	0

bank1_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1483	0	0
T62	4448	8	0	0
T237	3552	2	0	0
T242	6206	11	0	0
T273	8968	11	0	0
T274	38572	32	0	0
T275	5449	14	0	0
T276	5300	8	0	0
T277	4079	3	0	0
T280	3973	5	0	0
T281	5149	8	0	0

bank1_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1368	0	0
T62	4448	7	0	0
T242	6206	2	0	0
T273	8968	8	0	0
T274	38572	73	0	0
T275	5449	2	0	0
T276	5300	7	0	0
T277	4079	5	0	0
T278	4955	2	0	0
T279	9467	19	0	0
T280	3973	6	0	0

bank1_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1291	0	0
T62	4448	5	0	0
T242	6206	8	0	0
T273	8968	27	0	0
T274	38572	37	0	0
T275	5449	11	0	0
T276	5300	8	0	0
T277	4079	9	0	0
T278	4955	8	0	0
T279	9467	16	0	0
T280	3973	2	0	0

bank1_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1428	0	0
T62	4448	6	0	0
T237	3552	2	0	0
T242	6206	3	0	0
T273	8968	26	0	0
T274	38572	49	0	0
T275	5449	15	0	0
T276	5300	6	0	0
T277	4079	8	0	0
T278	4955	13	0	0
T281	5149	1	0	0

bank1_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1380	0	0
T62	4448	4	0	0
T242	6206	13	0	0
T273	8968	16	0	0
T274	38572	39	0	0
T275	5449	9	0	0
T276	5300	9	0	0
T277	4079	2	0	0
T278	4955	15	0	0
T279	9467	27	0	0
T281	5149	4	0	0

bank1_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1360	0	0
T62	4448	7	0	0
T242	6206	3	0	0
T273	8968	1	0	0
T274	38572	31	0	0
T275	5449	12	0	0
T276	5300	4	0	0
T277	4079	6	0	0
T278	4955	16	0	0
T279	9467	11	0	0
T284	3430	8	0	0

bank1_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1711	0	0
T62	4448	2	0	0
T237	3552	2	0	0
T242	6206	37	0	0
T273	8968	10	0	0
T274	38572	192	0	0
T275	5449	11	0	0
T276	5300	11	0	0
T278	4955	11	0	0
T279	9467	37	0	0
T281	5149	13	0	0

bank1_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1375	0	0
T62	4448	10	0	0
T237	3552	3	0	0
T242	6206	6	0	0
T273	8968	6	0	0
T274	38572	52	0	0
T275	5449	2	0	0
T276	5300	9	0	0
T277	4079	5	0	0
T278	4955	6	0	0
T281	5149	12	0	0

bank1_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1736	0	0
T237	3552	29	0	0
T242	6206	7	0	0
T273	8968	34	0	0
T274	38572	196	0	0
T275	5449	29	0	0
T276	5300	10	0	0
T278	4955	9	0	0
T279	9467	24	0	0
T280	3973	19	0	0
T281	5149	26	0	0

bank1_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1686	0	0
T237	3552	16	0	0
T242	6206	8	0	0
T273	8968	18	0	0
T274	38572	104	0	0
T275	5449	28	0	0
T276	5300	4	0	0
T277	4079	38	0	0
T278	4955	32	0	0
T279	9467	33	0	0
T281	5149	14	0	0

bank1_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1397	0	0
T237	3552	2	0	0
T242	6206	9	0	0
T273	8968	12	0	0
T274	38572	48	0	0
T275	5449	14	0	0
T276	5300	10	0	0
T277	4079	3	0	0
T278	4955	11	0	0
T280	3973	5	0	0
T281	5149	8	0	0

bank1_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1301	0	0
T237	3552	9	0	0
T242	6206	12	0	0
T273	8968	11	0	0
T274	38572	32	0	0
T275	5449	3	0	0
T276	5300	4	0	0
T277	4079	1	0	0
T278	4955	10	0	0
T280	3973	6	0	0
T281	5149	3	0	0

bank_cfg_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1329	0	0
T237	3552	7	0	0
T242	6206	9	0	0
T273	8968	6	0	0
T274	38572	42	0	0
T275	5449	10	0	0
T276	5300	8	0	0
T277	4079	1	0	0
T278	4955	8	0	0
T279	9467	10	0	0
T280	3973	3	0	0

default_region_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1781	0	0
T62	4448	6	0	0
T237	3552	11	0	0
T242	6206	17	0	0
T273	8968	22	0	0
T274	38572	172	0	0
T275	5449	35	0	0
T276	5300	23	0	0
T277	4079	19	0	0
T280	3973	16	0	0
T281	5149	11	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1407	0	0
T62	4448	2	0	0
T237	3552	3	0	0
T242	6206	6	0	0
T273	8968	10	0	0
T274	38572	48	0	0
T275	5449	4	0	0
T276	5300	4	0	0
T277	4079	1	0	0
T278	4955	5	0	0
T280	3973	3	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1518	0	0
T62	4448	3	0	0
T237	3552	1	0	0
T242	6206	7	0	0
T273	8968	21	0	0
T274	38572	69	0	0
T275	5449	7	0	0
T276	5300	9	0	0
T277	4079	4	0	0
T278	4955	10	0	0
T281	5149	12	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1336	0	0
T62	4448	1	0	0
T237	3552	10	0	0
T242	6206	8	0	0
T273	8968	15	0	0
T274	38572	31	0	0
T275	5449	16	0	0
T276	5300	12	0	0
T277	4079	5	0	0
T278	4955	5	0	0
T280	3973	5	0	0

hw_info_cfg_override_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1477	0	0
T237	3552	6	0	0
T242	6206	9	0	0
T273	8968	9	0	0
T274	38572	68	0	0
T275	5449	11	0	0
T276	5300	3	0	0
T277	4079	7	0	0
T278	4955	6	0	0
T280	3973	7	0	0
T281	5149	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1592	0	0
T62	4448	1	0	0
T237	3552	6	0	0
T242	6206	20	0	0
T273	8968	25	0	0
T274	38572	120	0	0
T275	5449	9	0	0
T276	5300	5	0	0
T277	4079	25	0	0
T278	4955	9	0	0
T281	5149	6	0	0

mp_region_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1464	0	0
T237	3552	1	0	0
T242	6206	3	0	0
T273	8968	6	0	0
T274	38572	40	0	0
T275	5449	11	0	0
T276	5300	9	0	0
T277	4079	9	0	0
T278	4955	14	0	0
T280	3973	1	0	0
T281	5149	8	0	0

mp_region_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1409	0	0
T237	3552	4	0	0
T242	6206	9	0	0
T273	8968	5	0	0
T274	38572	57	0	0
T275	5449	13	0	0
T276	5300	9	0	0
T277	4079	3	0	0
T278	4955	3	0	0
T280	3973	9	0	0
T281	5149	2	0	0

mp_region_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1362	0	0
T62	4448	1	0	0
T237	3552	3	0	0
T242	6206	19	0	0
T273	8968	13	0	0
T274	38572	51	0	0
T275	5449	6	0	0
T276	5300	8	0	0
T277	4079	6	0	0
T280	3973	10	0	0
T281	5149	9	0	0

mp_region_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1576	0	0
T62	4448	2	0	0
T237	3552	1	0	0
T242	6206	7	0	0
T273	8968	15	0	0
T274	38572	91	0	0
T275	5449	9	0	0
T276	5300	1	0	0
T277	4079	7	0	0
T280	3973	8	0	0
T281	5149	14	0	0

mp_region_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1369	0	0
T62	4448	8	0	0
T242	6206	21	0	0
T273	8968	5	0	0
T274	38572	86	0	0
T275	5449	1	0	0
T276	5300	13	0	0
T277	4079	12	0	0
T278	4955	4	0	0
T280	3973	1	0	0
T281	5149	6	0	0

mp_region_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1554	0	0
T242	6206	23	0	0
T273	8968	9	0	0
T274	38572	48	0	0
T275	5449	6	0	0
T276	5300	18	0	0
T277	4079	4	0	0
T278	4955	11	0	0
T279	9467	20	0	0
T283	4003	2	0	0
T284	3430	4	0	0

mp_region_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1413	0	0
T62	4448	3	0	0
T242	6206	16	0	0
T273	8968	19	0	0
T274	38572	51	0	0
T275	5449	14	0	0
T276	5300	6	0	0
T278	4955	6	0	0
T279	9467	15	0	0
T280	3973	1	0	0
T283	4003	4	0	0

mp_region_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1392	0	0
T242	6206	3	0	0
T273	8968	12	0	0
T274	38572	74	0	0
T275	5449	13	0	0
T276	5300	14	0	0
T277	4079	9	0	0
T278	4955	10	0	0
T279	9467	16	0	0
T280	3973	4	0	0
T281	5149	3	0	0

mp_region_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1675	0	0
T242	6206	6	0	0
T273	8968	15	0	0
T274	38572	80	0	0
T275	5449	13	0	0
T276	5300	9	0	0
T277	4079	2	0	0
T278	4955	6	0	0
T279	9467	36	0	0
T280	3973	20	0	0
T281	5149	5	0	0

mp_region_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1812	0	0
T62	4448	3	0	0
T237	3552	18	0	0
T242	6206	30	0	0
T273	8968	4	0	0
T274	38572	130	0	0
T275	5449	26	0	0
T276	5300	1	0	0
T277	4079	39	0	0
T278	4955	39	0	0
T281	5149	11	0	0

mp_region_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1829	0	0
T237	3552	16	0	0
T242	6206	50	0	0
T273	8968	28	0	0
T274	38572	167	0	0
T275	5449	10	0	0
T276	5300	7	0	0
T277	4079	16	0	0
T278	4955	56	0	0
T280	3973	4	0	0
T281	5149	16	0	0

mp_region_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1570	0	0
T62	4448	5	0	0
T237	3552	3	0	0
T242	6206	42	0	0
T273	8968	6	0	0
T274	38572	124	0	0
T275	5449	5	0	0
T276	5300	19	0	0
T277	4079	36	0	0
T278	4955	8	0	0
T280	3973	11	0	0

mp_region_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1802	0	0
T62	4448	6	0	0
T237	3552	7	0	0
T242	6206	10	0	0
T273	8968	21	0	0
T274	38572	145	0	0
T275	5449	28	0	0
T276	5300	29	0	0
T277	4079	16	0	0
T278	4955	4	0	0
T281	5149	23	0	0

mp_region_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1888	0	0
T62	4448	7	0	0
T237	3552	7	0	0
T242	6206	55	0	0
T273	8968	56	0	0
T274	38572	183	0	0
T275	5449	12	0	0
T276	5300	1	0	0
T278	4955	38	0	0
T280	3973	11	0	0
T281	5149	15	0	0

mp_region_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1930	0	0
T62	4448	8	0	0
T242	6206	39	0	0
T273	8968	33	0	0
T274	38572	169	0	0
T275	5449	28	0	0
T276	5300	5	0	0
T277	4079	6	0	0
T278	4955	6	0	0
T279	9467	10	0	0
T281	5149	21	0	0

mp_region_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1815	0	0
T62	4448	13	0	0
T237	3552	9	0	0
T242	6206	58	0	0
T273	8968	65	0	0
T274	38572	170	0	0
T275	5449	13	0	0
T276	5300	22	0	0
T277	4079	3	0	0
T280	3973	4	0	0
T281	5149	2	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	134	0	0
T273	8968	2	0	0
T275	5449	7	0	0
T278	4955	8	0	0
T279	9467	4	0	0
T285	8982	6	0	0
T286	20450	75	0	0
T287	21422	32	0	0

region_cfg_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1365	0	0
T62	4448	16	0	0
T273	8968	5	0	0
T274	38572	34	0	0
T275	5449	10	0	0
T276	5300	16	0	0
T277	4079	6	0	0
T278	4955	8	0	0
T279	9467	16	0	0
T281	5149	5	0	0
T283	4003	6	0	0

region_cfg_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1415	0	0
T237	3552	1	0	0
T242	6206	15	0	0
T273	8968	9	0	0
T274	38572	59	0	0
T275	5449	9	0	0
T277	4079	2	0	0
T278	4955	8	0	0
T279	9467	14	0	0
T280	3973	5	0	0
T281	5149	10	0	0

region_cfg_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1273	0	0
T242	6206	4	0	0
T273	8968	4	0	0
T274	38572	26	0	0
T275	5449	8	0	0
T276	5300	14	0	0
T277	4079	7	0	0
T279	9467	19	0	0
T281	5149	2	0	0
T282	328145	433	0	0
T283	4003	1	0	0

region_cfg_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1452	0	0
T62	4448	1	0	0
T242	6206	11	0	0
T273	8968	18	0	0
T274	38572	36	0	0
T275	5449	8	0	0
T276	5300	5	0	0
T277	4079	4	0	0
T278	4955	2	0	0
T280	3973	1	0	0
T281	5149	2	0	0

region_cfg_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1431	0	0
T62	4448	7	0	0
T242	6206	11	0	0
T273	8968	5	0	0
T274	38572	44	0	0
T275	5449	9	0	0
T276	5300	18	0	0
T277	4079	8	0	0
T278	4955	13	0	0
T280	3973	5	0	0
T281	5149	2	0	0

region_cfg_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1358	0	0
T62	4448	17	0	0
T242	6206	10	0	0
T273	8968	12	0	0
T274	38572	41	0	0
T275	5449	11	0	0
T276	5300	4	0	0
T277	4079	5	0	0
T278	4955	8	0	0
T280	3973	3	0	0
T281	5149	3	0	0

region_cfg_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1475	0	0
T62	4448	4	0	0
T242	6206	5	0	0
T273	8968	11	0	0
T274	38572	33	0	0
T275	5449	4	0	0
T276	5300	12	0	0
T277	4079	7	0	0
T278	4955	12	0	0
T279	9467	16	0	0
T281	5149	4	0	0

region_cfg_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1455	0	0
T62	4448	13	0	0
T237	3552	4	0	0
T242	6206	3	0	0
T273	8968	18	0	0
T274	38572	40	0	0
T275	5449	10	0	0
T276	5300	15	0	0
T277	4079	4	0	0
T278	4955	8	0	0
T280	3973	3	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415549248	1434	0	0
T62	4448	5	0	0
T237	3552	2	0	0
T242	6206	7	0	0
T273	8968	10	0	0
T274	38572	30	0	0
T275	5449	4	0	0
T277	4079	1	0	0
T278	4955	6	0	0
T279	9467	28	0	0
T281	5149	2	0	0