Unified Coverage Report :: Module :: flash_phy_core

Module : flash_phy_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	91.51		100.00	97.83	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core	96.36	100.00	83.96		100.00	97.83	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core	97.87	100.00	91.51		100.00	97.83	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.36	100.00	83.96		100.00	97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.59	97.91	93.15	96.90	100.00	99.62	97.94

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.89	97.67	84.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	98.65	100.00	96.92	95.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	91.95	75.93	91.89			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.85	99.16	93.88	100.00		100.00	96.23
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	91.51		100.00	97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.28	97.91	94.22	100.00	100.00	99.62	97.94

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.89	97.67	84.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	99.74	100.00	98.46	100.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	93.98	75.93	100.00			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.90	99.16	94.13	100.00		100.00	96.23
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
ALWAYS	202	4	4	100.00
ALWAYS	214	6	6	100.00
ALWAYS	228	6	6	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
ALWAYS	324	29	29	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	566	1	1	100.00
CONT_ASSIGN	583	1	1	100.00
CONT_ASSIGN	584	1	1	100.00
CONT_ASSIGN	585	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
164	3	3
195	1	1
199	1	1
202	1	1
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
			MISSING_ELSE
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
			MISSING_ELSE
276	1	1
279	1	1
280	1	1
281	1	1
286	1	1
316	1	1
320	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
330	1	1
332	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
			MISSING_ELSE
346	1	1
347	1	1
348	1	1
			MISSING_ELSE
355	1	1
356	1	1
357	1	1
358	1	1
			MISSING_ELSE
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
			MISSING_ELSE
373	1	1
374	1	1
387	1	1
391	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
414	1	1
427	1	1
521	1	1
548	1	1
549	1	1
550	1	1
551	1	1
553	1	1
554	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
566	1	1
583	1	1
584	1	1
585	1	1

---

Cond Coverage for Module : flash_phy_core

	Total	Covered	Percent
Conditions	106	97	91.51
Logical	106	97	91.51
Non-Logical	0	0
Event	0	0

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T11,T74,T75

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T11,T74,T75

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T6,T7
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T6

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T7
1	0	1	Covered	T3,T4,T6
1	1	0	Covered	T68,T69
1	1	1	Covered	T3,T4,T6

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T6
1	1	Covered	T3,T4,T6

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T3,T4,T6

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T66,T80,T81
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T6

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T8

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T16
1	1	Covered	T1,T2,T3

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T7
1	0	Covered	T4,T16,T59
1	1	Covered	T1,T16,T7

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T68,T69
1	0	Covered	T65,T191,T178

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T65,T191,T178

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T68,T69

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T16
1	1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T16,T7

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T16,T59
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T16,T59

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T25,T42
1	0	Covered	T4,T16,T59

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Not Covered
1	1	Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T16
1	1	Covered	T1,T2,T3

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T43
1	0	Covered	T5,T15,T43

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T18,T59

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T18,T59

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T18,T59

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T18,T59

---

FSM Coverage for Module : flash_phy_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	340	Covered	T4,T16,T59
StCtrlProg	338	Covered	T1,T16,T7
StCtrlRead	336	Covered	T1,T2,T3
StDisable	334	Covered	T5,T12,T13
StIdle	348	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	368	Covered	T4,T16,T59
StCtrlProg->StIdle	358	Covered	T1,T16,T7
StCtrlRead->StIdle	348	Covered	T1,T2,T3
StIdle->StCtrl	340	Covered	T4,T16,T59
StIdle->StCtrlProg	338	Covered	T1,T16,T7
StIdle->StCtrlRead	336	Covered	T1,T2,T3
StIdle->StDisable	334	Covered	T5,T12,T13

---

Branch Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	316	2	2	100.00
TERNARY	391	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	550	2	2	100.00
TERNARY	551	2	2	100.00
TERNARY	430	2	1	50.00
IF	151	4	4	100.00
IF	164	2	2	100.00
IF	202	3	3	100.00
IF	214	4	4	100.00
IF	228	4	4	100.00
CASE	330	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	316	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	391	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T18,T59
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T18,T59
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	430	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if (ctrl_rsp_vld)
-3-:	155	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T6,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	202	if ((!rst_ni))
-2-:	204	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T11,T74,T75
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	216	if ((host_outstanding == '0))
-3-:	218	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T11,T14
0	0	0	Covered	T3,T4,T6

	LineNo.	Expression
-1-:	228	if ((!rst_ni))
-2-:	230	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	232	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T11,T14
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	330	case (state_q)
-2-:	333	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	335	if ((ctrl_gnt && rd_i))
-4-:	337	if ((ctrl_gnt && prog_i))
-5-:	339	if (ctrl_gnt)
-6-:	346	if (rd_stage_data_valid)
-7-:	356	if (prog_ack)
-8-:	366	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T5,T12,T13
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T1,T16,T7
StIdle	0	0	0	1	-	-	-	Covered	T4,T16,T59
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T1,T16,T7
StCtrlProg	-	-	-	-	-	0	-	Covered	T1,T16,T7
StCtrl	-	-	-	-	-	-	1	Covered	T4,T16,T59
StCtrl	-	-	-	-	-	-	0	Covered	T4,T16,T59
StDisable	-	-	-	-	-	-	-	Covered	T5,T12,T13
default	-	-	-	-	-	-	-	Covered	T5,T15,T11

---

Assert Coverage for Module : flash_phy_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	840326400	4326735	0	0
CtrlPrio_A	840326400	4326725	0	0
HostTransIdleChk_A	840326400	46309875	0	0
NoRemainder_A	2124	2124	0	0
OneHotReqs_A	840326400	838612154	0	0
Pow2Multiple_A	2124	2124	0	0
RdTxnCheck_A	840002832	838288586	0	0
u_state_regs_A	840326400	838612154	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840326400	4326735	0	0
T6	1648330	76735	0	0
T7	612872	10135	0	0
T8	584490	13793	0	0
T12	2248	0	0	0
T13	760600	0	0	0
T17	10626	0	0	0
T18	3786	0	0	0
T19	0	83739	0	0
T29	0	72100	0	0
T31	0	6111	0	0
T42	0	84	0	0
T45	0	6469	0	0
T46	145998	0	0	0
T55	0	4992	0	0
T59	196160	0	0	0
T60	426986	0	0	0
T73	0	14360	0	0
T125	0	11611	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840326400	4326725	0	0
T6	1648330	76735	0	0
T7	612872	10135	0	0
T8	584490	13793	0	0
T12	2248	0	0	0
T13	760600	0	0	0
T17	10626	0	0	0
T18	3786	0	0	0
T19	0	83739	0	0
T29	0	72100	0	0
T31	0	6111	0	0
T42	0	84	0	0
T45	0	6469	0	0
T46	145998	0	0	0
T55	0	4992	0	0
T59	196160	0	0	0
T60	426986	0	0	0
T73	0	14360	0	0
T125	0	11611	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840326400	46309875	0	0
T3	3467	40	0	0
T4	20536	37	0	0
T5	288538	0	0	0
T6	1648330	847875	0	0
T7	612872	151165	0	0
T8	0	151883	0	0
T12	2248	0	0	0
T13	380300	0	0	0
T16	521056	0	0	0
T17	10626	8	0	0
T18	3786	0	0	0
T19	0	843139	0	0
T20	0	32	0	0
T29	0	843540	0	0
T30	0	32	0	0
T42	0	343	0	0
T54	0	20	0	0
T59	196160	0	0	0
T61	0	16	0	0
T76	0	156	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2124	2124	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840326400	838612154	0	0
T1	108046	107926	0	0
T2	7326	7132	0	0
T3	6934	6636	0	0
T4	20536	20244	0	0
T5	288538	236668	0	0
T6	1648330	1648042	0	0
T7	612872	612688	0	0
T16	521056	520946	0	0
T17	10626	10324	0	0
T18	3786	3500	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2124	2124	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840002832	838288586	0	0
T1	108046	107926	0	0
T2	7326	7132	0	0
T3	6934	6636	0	0
T4	20536	20244	0	0
T5	184158	132288	0	0
T6	1648330	1648042	0	0
T7	612872	612688	0	0
T16	521056	520946	0	0
T17	10626	10324	0	0
T18	3786	3500	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840326400	838612154	0	0
T1	108046	107926	0	0
T2	7326	7132	0	0
T3	6934	6636	0	0
T4	20536	20244	0	0
T5	288538	236668	0	0
T6	1648330	1648042	0	0
T7	612872	612688	0	0
T16	521056	520946	0	0
T17	10626	10324	0	0
T18	3786	3500	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
ALWAYS	202	4	4	100.00
ALWAYS	214	6	6	100.00
ALWAYS	228	6	6	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
ALWAYS	324	29	29	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	566	1	1	100.00
CONT_ASSIGN	583	1	1	100.00
CONT_ASSIGN	584	1	1	100.00
CONT_ASSIGN	585	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
164	3	3
195	1	1
199	1	1
202	1	1
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
			MISSING_ELSE
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
			MISSING_ELSE
276	1	1
279	1	1
280	1	1
281	1	1
286	1	1
316	1	1
320	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
330	1	1
332	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
			MISSING_ELSE
346	1	1
347	1	1
348	1	1
			MISSING_ELSE
355	1	1
356	1	1
357	1	1
358	1	1
			MISSING_ELSE
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
			MISSING_ELSE
373	1	1
374	1	1
387	1	1
391	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
414	1	1
427	1	1
521	1	1
548	1	1
549	1	1
550	1	1
551	1	1
553	1	1
554	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
566	1	1
583	1	1
584	1	1
585	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Covered	Percent
Conditions	106	89	83.96
Logical	106	89	83.96
Non-Logical	0	0
Event	0	0

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T17
1	1	Not Covered

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T16,T6
1	0	Covered	T4,T6,T17
1	1	Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T6,T17
1	Covered	T1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T17
1	0	Covered	T4,T16,T6
1	1	Covered	T1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T4,T6,T17
1	Covered	T1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T6,T7
1	1	0	Not Covered
1	1	1	Covered	T4,T6,T17

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T7
1	0	1	Covered	T4,T6,T17
1	1	0	Not Covered
1	1	1	Covered	T4,T6,T17

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T17
1	1	Covered	T4,T6,T17

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T16,T6
1	0	Covered	T4,T6,T17
1	1	Covered	T4,T6,T17

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T17

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T16,T6
1	1	Covered	T4,T6,T17

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T17
1	0	Covered	T4,T16,T6
1	1	Covered	T6,T7,T8

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T7,T59
1	1	Covered	T4,T16,T6

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T7
1	0	Covered	T16,T59,T13
1	1	Covered	T16,T7,T59

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T16,T6
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T17
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T17

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T17

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T17

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T17

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T7,T59
1	1	Covered	T4,T16,T6

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T7
1	0	Covered	T4,T16,T6
1	1	Covered	T16,T7,T59

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T16,T59
1	0	Covered	T4,T16,T6
1	1	Covered	T16,T59,T13

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T25,T42
1	0	Covered	T4,T16,T59

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T17
1	0	Not Covered
1	1	Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T17

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T7,T59
1	1	Covered	T4,T16,T6

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T17
1	0	Covered	T1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T43
1	0	Covered	T5,T15,T43

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T17,T13
1	0	Covered	T7,T13,T72

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T17,T13
1	0	Covered	T7,T13,T72

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T13,T72

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T13,T72

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	340	Covered	T16,T59,T13
StCtrlProg	338	Covered	T16,T7,T59
StCtrlRead	336	Covered	T4,T16,T6
StDisable	334	Covered	T5,T12,T13
StIdle	348	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	368	Covered	T16,T59,T13
StCtrlProg->StIdle	358	Covered	T16,T7,T59
StCtrlRead->StIdle	348	Covered	T4,T16,T6
StIdle->StCtrl	340	Covered	T16,T59,T13
StIdle->StCtrlProg	338	Covered	T16,T7,T59
StIdle->StCtrlRead	336	Covered	T4,T16,T6
StIdle->StDisable	334	Covered	T5,T12,T13

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	316	2	2	100.00
TERNARY	391	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	550	2	2	100.00
TERNARY	551	2	2	100.00
TERNARY	430	2	1	50.00
IF	151	4	4	100.00
IF	164	2	2	100.00
IF	202	3	3	100.00
IF	214	4	4	100.00
IF	228	4	4	100.00
CASE	330	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	316	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	391	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T13,T72
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T13,T72
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	430	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if (ctrl_rsp_vld)
-3-:	155	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T16,T6
0	0	1	Covered	T6,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	202	if ((!rst_ni))
-2-:	204	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T11,T14
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	216	if ((host_outstanding == '0))
-3-:	218	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T11,T14
0	0	0	Covered	T4,T6,T17

	LineNo.	Expression
-1-:	228	if ((!rst_ni))
-2-:	230	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	232	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T11,T14
0	0	0	Covered	T4,T16,T6

	LineNo.	Expression
-1-:	330	case (state_q)
-2-:	333	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	335	if ((ctrl_gnt && rd_i))
-4-:	337	if ((ctrl_gnt && prog_i))
-5-:	339	if (ctrl_gnt)
-6-:	346	if (rd_stage_data_valid)
-7-:	356	if (prog_ack)
-8-:	366	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T5,T12,T13
StIdle	0	1	-	-	-	-	-	Covered	T4,T16,T6
StIdle	0	0	1	-	-	-	-	Covered	T16,T7,T59
StIdle	0	0	0	1	-	-	-	Covered	T16,T59,T13
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T4,T16,T6
StCtrlRead	-	-	-	-	0	-	-	Covered	T4,T16,T6
StCtrlProg	-	-	-	-	-	1	-	Covered	T16,T7,T59
StCtrlProg	-	-	-	-	-	0	-	Covered	T16,T7,T59
StCtrl	-	-	-	-	-	-	1	Covered	T16,T59,T13
StCtrl	-	-	-	-	-	-	0	Covered	T16,T59,T13
StDisable	-	-	-	-	-	-	-	Covered	T5,T12,T13
default	-	-	-	-	-	-	-	Covered	T5,T15,T11

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	420163200	2138043	0	0
CtrlPrio_A	420163200	2138038	0	0
HostTransIdleChk_A	420163200	22915665	0	0
NoRemainder_A	1062	1062	0	0
OneHotReqs_A	420163200	419306077	0	0
Pow2Multiple_A	1062	1062	0	0
RdTxnCheck_A	420001416	419144293	0	0
u_state_regs_A	420163200	419306077	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	2138043	0	0
T6	824165	47689	0	0
T7	306436	2477	0	0
T8	292245	4484	0	0
T12	1124	0	0	0
T13	380300	0	0	0
T17	5313	0	0	0
T18	1893	0	0	0
T19	0	43672	0	0
T29	0	30282	0	0
T31	0	4671	0	0
T45	0	3342	0	0
T46	72999	0	0	0
T55	0	2553	0	0
T59	98080	0	0	0
T60	213493	0	0	0
T73	0	4670	0	0
T125	0	11611	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	2138038	0	0
T6	824165	47689	0	0
T7	306436	2477	0	0
T8	292245	4484	0	0
T12	1124	0	0	0
T13	380300	0	0	0
T17	5313	0	0	0
T18	1893	0	0	0
T19	0	43672	0	0
T29	0	30282	0	0
T31	0	4671	0	0
T45	0	3342	0	0
T46	72999	0	0	0
T55	0	2553	0	0
T59	98080	0	0	0
T60	213493	0	0	0
T73	0	4670	0	0
T125	0	11611	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	22915665	0	0
T4	10268	37	0	0
T5	144269	0	0	0
T6	824165	433296	0	0
T7	306436	66421	0	0
T8	0	60747	0	0
T12	1124	0	0	0
T13	380300	0	0	0
T16	260528	0	0	0
T17	5313	8	0	0
T18	1893	0	0	0
T19	0	411777	0	0
T20	0	32	0	0
T29	0	405501	0	0
T42	0	17	0	0
T59	98080	0	0	0
T76	0	156	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420001416	419144293	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	92079	66144	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
ALWAYS	202	4	4	100.00
ALWAYS	214	6	6	100.00
ALWAYS	228	6	6	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
ALWAYS	324	29	29	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	566	1	1	100.00
CONT_ASSIGN	583	1	1	100.00
CONT_ASSIGN	584	1	1	100.00
CONT_ASSIGN	585	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
164	3	3
195	1	1
199	1	1
202	1	1
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
			MISSING_ELSE
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
			MISSING_ELSE
276	1	1
279	1	1
280	1	1
281	1	1
286	1	1
316	1	1
320	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
330	1	1
332	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
			MISSING_ELSE
346	1	1
347	1	1
348	1	1
			MISSING_ELSE
355	1	1
356	1	1
357	1	1
358	1	1
			MISSING_ELSE
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
			MISSING_ELSE
373	1	1
374	1	1
387	1	1
391	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
414	1	1
427	1	1
521	1	1
548	1	1
549	1	1
550	1	1
551	1	1
553	1	1
554	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
566	1	1
583	1	1
584	1	1
585	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Covered	Percent
Conditions	106	97	91.51
Logical	106	97	91.51
Non-Logical	0	0
Event	0	0

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Covered	T11,T74,T75

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T11,T74,T75

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T3,T6,T7

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T7,T8
1	0	1	Covered	T3,T6,T7
1	1	0	Covered	T68,T69
1	1	1	Covered	T3,T6,T7

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T7

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T66,T80,T81
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T7

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T8

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T4,T16,T6
1	0	Covered	T1,T4,T16
1	1	Covered	T1,T2,T3

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T16,T7,T59
1	0	Covered	T4,T16,T59
1	1	Covered	T1,T16,T7

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T68,T69
1	0	Covered	T65,T191,T178

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T65,T191,T178

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T68,T69

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T7

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T7

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T7

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T7

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T16
1	1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T16,T7

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T16,T59
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T16,T59

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T25,T42
1	0	Covered	T4,T16,T59

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Not Covered
1	1	Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T7

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T16
1	1	Covered	T1,T2,T3

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T43
1	0	Covered	T5,T15,T43

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T59,T12

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T59,T12

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T59,T12

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T59,T12

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	340	Covered	T4,T16,T59
StCtrlProg	338	Covered	T1,T16,T7
StCtrlRead	336	Covered	T1,T2,T3
StDisable	334	Covered	T5,T12,T13
StIdle	348	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	368	Covered	T4,T16,T59
StCtrlProg->StIdle	358	Covered	T1,T16,T7
StCtrlRead->StIdle	348	Covered	T1,T2,T3
StIdle->StCtrl	340	Covered	T4,T16,T59
StIdle->StCtrlProg	338	Covered	T1,T16,T7
StIdle->StCtrlRead	336	Covered	T1,T2,T3
StIdle->StDisable	334	Covered	T5,T12,T13

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	316	2	2	100.00
TERNARY	391	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	550	2	2	100.00
TERNARY	551	2	2	100.00
TERNARY	430	2	1	50.00
IF	151	4	4	100.00
IF	164	2	2	100.00
IF	202	3	3	100.00
IF	214	4	4	100.00
IF	228	4	4	100.00
CASE	330	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	316	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	391	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T59,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T59,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	430	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if (ctrl_rsp_vld)
-3-:	155	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T6,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	202	if ((!rst_ni))
-2-:	204	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T11,T74,T75
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	216	if ((host_outstanding == '0))
-3-:	218	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T11,T14
0	0	0	Covered	T3,T6,T7

	LineNo.	Expression
-1-:	228	if ((!rst_ni))
-2-:	230	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	232	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T11,T14
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	330	case (state_q)
-2-:	333	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	335	if ((ctrl_gnt && rd_i))
-4-:	337	if ((ctrl_gnt && prog_i))
-5-:	339	if (ctrl_gnt)
-6-:	346	if (rd_stage_data_valid)
-7-:	356	if (prog_ack)
-8-:	366	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T5,T12,T13
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T1,T16,T7
StIdle	0	0	0	1	-	-	-	Covered	T4,T16,T59
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T1,T16,T7
StCtrlProg	-	-	-	-	-	0	-	Covered	T1,T16,T7
StCtrl	-	-	-	-	-	-	1	Covered	T4,T16,T59
StCtrl	-	-	-	-	-	-	0	Covered	T4,T16,T59
StDisable	-	-	-	-	-	-	-	Covered	T5,T12,T13
default	-	-	-	-	-	-	-	Covered	T5,T15,T11

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	420163200	2188692	0	0
CtrlPrio_A	420163200	2188687	0	0
HostTransIdleChk_A	420163200	23394210	0	0
NoRemainder_A	1062	1062	0	0
OneHotReqs_A	420163200	419306077	0	0
Pow2Multiple_A	1062	1062	0	0
RdTxnCheck_A	420001416	419144293	0	0
u_state_regs_A	420163200	419306077	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	2188692	0	0
T6	824165	29046	0	0
T7	306436	7658	0	0
T8	292245	9309	0	0
T12	1124	0	0	0
T13	380300	0	0	0
T17	5313	0	0	0
T18	1893	0	0	0
T19	0	40067	0	0
T29	0	41818	0	0
T31	0	1440	0	0
T42	0	84	0	0
T45	0	3127	0	0
T46	72999	0	0	0
T55	0	2439	0	0
T59	98080	0	0	0
T60	213493	0	0	0
T73	0	9690	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	2188687	0	0
T6	824165	29046	0	0
T7	306436	7658	0	0
T8	292245	9309	0	0
T12	1124	0	0	0
T13	380300	0	0	0
T17	5313	0	0	0
T18	1893	0	0	0
T19	0	40067	0	0
T29	0	41818	0	0
T31	0	1440	0	0
T42	0	84	0	0
T45	0	3127	0	0
T46	72999	0	0	0
T55	0	2439	0	0
T59	98080	0	0	0
T60	213493	0	0	0
T73	0	9690	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	23394210	0	0
T3	3467	40	0	0
T4	10268	0	0	0
T5	144269	0	0	0
T6	824165	414579	0	0
T7	306436	84744	0	0
T8	0	91136	0	0
T12	1124	0	0	0
T16	260528	0	0	0
T17	5313	0	0	0
T18	1893	0	0	0
T19	0	431362	0	0
T29	0	438039	0	0
T30	0	32	0	0
T42	0	326	0	0
T54	0	20	0	0
T59	98080	0	0	0
T61	0	16	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420001416	419144293	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	92079	66144	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0