Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.69	100.00	98.46		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	99.69	100.00	98.46		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.65	100.00	96.92	95.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36	100.00	83.96		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.69	100.00	98.46		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.74	100.00	98.46	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.87	100.00	91.51		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	64	98.46
Logical	65	64	98.46
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T16,T7

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T16,T7

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T146,T147,T9
1	0	Covered	T146,T147,T9

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T16,T7
1	1	Covered	T146,T147,T9

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T65,T257
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T146,T147,T9
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T16,T7

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T16,T7
1	Covered	T16,T7,T12

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T7
1	0	Covered	T1,T16,T7
1	1	Covered	T1,T16,T7

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T16,T7

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T16,T7
1	1	Covered	T16,T7,T18

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T14
1	Covered	T16,T7,T18

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T7
1	0	Covered	T1,T16,T7
1	1	Covered	T1,T16,T7

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T16,T7
1	Covered	T1,T16,T7

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T7
1	0	Covered	T1,T16,T7
1	1	Covered	T16,T7,T12

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T11,T14
1	Covered	T16,T7,T12

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T1,T16,T7
1	Covered	T7,T18,T59

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T16,T7
1	Covered	T1,T16,T7

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T16,T7
1	Covered	T1,T16,T7

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T16,T7
1	1	Covered	T1,T16,T7

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T18,T59
1	1	Covered	T7,T18,T59

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T18,T59
1	1	Covered	T7,T18,T59

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T16,T7
1	1	0	Covered	T1,T16,T7
1	1	1	Covered	T1,T16,T7

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T16,T7

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T7,T18,T59
StCalcMask	237	Covered	T7,T18,T59
StCalcPlainEcc	215	Covered	T1,T16,T7
StDisabled	193	Covered	T5,T12,T13
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T16,T7
StPostPack	218	Covered	T16,T7,T12
StPrePack	195	Covered	T16,T7,T18
StReqFlash	237	Covered	T1,T16,T7
StScrambleData	244	Covered	T7,T18,T59
StWaitFlash	270	Covered	T1,T16,T7

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T7,T18,T59
StCalcMask->StScrambleData	244	Covered	T7,T18,T59
StCalcPlainEcc->StCalcMask	237	Covered	T7,T18,T59
StCalcPlainEcc->StReqFlash	237	Covered	T1,T16,T7
StIdle->StDisabled	193	Covered	T5,T12,T13
StIdle->StPackData	197	Covered	T1,T16,T7
StIdle->StPrePack	195	Covered	T16,T7,T18
StPackData->StCalcPlainEcc	215	Covered	T1,T16,T7
StPackData->StPostPack	218	Covered	T16,T7,T12
StPostPack->StCalcPlainEcc	231	Covered	T16,T7,T12
StPrePack->StPackData	205	Covered	T16,T7,T18
StReqFlash->StIdle	273	Covered	T1,T16,T7
StReqFlash->StWaitFlash	270	Covered	T1,T16,T7
StScrambleData->StCalcEcc	252	Covered	T7,T18,T59
StWaitFlash->StIdle	280	Covered	T1,T16,T7

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T16,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T16,T7
0	0	1	Covered	T1,T16,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T13
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T7,T18
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T7
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T7,T18
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T7
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T16,T7,T12
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T16,T7
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T16,T7
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T16,T7,T12
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T11,T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T7,T18,T59
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T16,T7
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T7,T18,T59
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T7,T18,T59
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T7,T18,T59
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T7,T18,T59
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T18,T59
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T16,T7
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T16,T7
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T16,T7
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T1,T16,T7
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T16,T7
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T16,T7
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T15,T11

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T16,T7
0	0	1	-	-	Covered	T7,T18,T59
0	0	0	1	-	Covered	T7,T18,T59
0	0	0	0	1	Covered	T1,T16,T7
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T16,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	840326400	2399765	0	0
PostPackRule_A	840326400	29090	0	0
PrePackRule_A	840326400	14126	0	0
WidthCheck_A	2124	2124	0	0
u_state_regs_A	840326400	838612154	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840326400	2399765	0	0
T1	54023	32	0	0
T2	3663	0	0	0
T3	3467	0	0	0
T4	10268	0	0	0
T5	288538	0	0	0
T6	1648330	0	0	0
T7	612872	838	0	0
T8	0	1139	0	0
T12	1124	1	0	0
T13	380300	65920	0	0
T16	521056	74	0	0
T17	10626	0	0	0
T18	3786	0	0	0
T20	0	1	0	0
T25	0	32800	0	0
T46	0	57	0	0
T47	0	51	0	0
T59	98080	100	0	0
T60	213493	964	0	0
T79	0	139	0	0
T104	0	55	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840326400	29090	0	0
T5	288538	0	0	0
T6	1648330	0	0	0
T7	612872	307	0	0
T8	0	363	0	0
T12	2248	1	0	0
T13	760600	0	0	0
T16	521056	45	0	0
T17	10626	0	0	0
T18	3786	0	0	0
T20	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T59	196160	0	0	0
T60	426986	358	0	0
T61	0	1	0	0
T79	0	12	0	0
T88	0	19	0	0
T89	0	300	0	0
T104	0	1	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840326400	14126	0	0
T5	288538	0	0	0
T6	1648330	0	0	0
T7	612872	147	0	0
T8	0	187	0	0
T12	2248	1	0	0
T13	760600	0	0	0
T16	521056	29	0	0
T17	10626	0	0	0
T18	3786	1	0	0
T42	0	1	0	0
T59	196160	0	0	0
T60	426986	201	0	0
T73	0	80	0	0
T79	0	9	0	0
T88	0	12	0	0
T89	0	147	0	0
T104	0	1	0	0
T234	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2124	2124	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840326400	838612154	0	0
T1	108046	107926	0	0
T2	7326	7132	0	0
T3	6934	6636	0	0
T4	20536	20244	0	0
T5	288538	236668	0	0
T6	1648330	1648042	0	0
T7	612872	612688	0	0
T16	521056	520946	0	0
T17	10626	10324	0	0
T18	3786	3500	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T7,T59

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T7,T59

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T257
1	0	Covered	T9,T10,T257

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T7,T59
1	1	Covered	T9,T10,T257

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T257
1	0	Covered	T4,T16,T6

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T7,T59

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T16,T7,T59
1	Covered	T16,T7,T60

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T16,T7,T59
1	0	Covered	T16,T7,T59
1	1	Covered	T16,T7,T59

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T7,T59

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T7,T59
1	1	Covered	T16,T7,T60

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T14
1	Covered	T16,T7,T60

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T16,T7,T59
1	0	Covered	T16,T7,T59
1	1	Covered	T16,T7,T59

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T16,T7,T59
1	Covered	T16,T7,T59

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T16,T7,T59
1	0	Covered	T16,T7,T59
1	1	Covered	T16,T7,T60

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T11,T14
1	Covered	T16,T7,T60

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T16,T7,T59
1	Covered	T7,T13,T72

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T16,T7,T59
1	Covered	T16,T7,T59

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T16,T7,T59
1	Covered	T16,T7,T59

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T7,T59
1	1	Covered	T16,T7,T59

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T17,T13
1	0	Covered	T7,T13,T72
1	1	Covered	T7,T13,T72

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T17,T13
1	0	Covered	T7,T13,T72
1	1	Covered	T7,T13,T72

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T16,T7,T59
1	1	0	Covered	T16,T7,T59
1	1	1	Covered	T16,T7,T59

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T7,T59

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T16,T6

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T7,T72,T20
StCalcMask	237	Covered	T7,T72,T20
StCalcPlainEcc	215	Covered	T16,T7,T59
StDisabled	193	Covered	T5,T12,T13
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T16,T7,T59
StPostPack	218	Covered	T16,T7,T60
StPrePack	195	Covered	T16,T7,T60
StReqFlash	237	Covered	T16,T7,T59
StScrambleData	244	Covered	T7,T72,T20
StWaitFlash	270	Covered	T16,T7,T59

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T7,T72,T20
StCalcMask->StScrambleData	244	Covered	T7,T72,T20
StCalcPlainEcc->StCalcMask	237	Covered	T7,T72,T20
StCalcPlainEcc->StReqFlash	237	Covered	T16,T7,T59
StIdle->StDisabled	193	Covered	T5,T12,T13
StIdle->StPackData	197	Covered	T16,T7,T59
StIdle->StPrePack	195	Covered	T16,T7,T60
StPackData->StCalcPlainEcc	215	Covered	T16,T7,T59
StPackData->StPostPack	218	Covered	T16,T7,T60
StPostPack->StCalcPlainEcc	231	Covered	T16,T7,T60
StPrePack->StPackData	205	Covered	T16,T7,T60
StReqFlash->StIdle	273	Covered	T16,T7,T59
StReqFlash->StWaitFlash	270	Covered	T16,T7,T59
StScrambleData->StCalcEcc	252	Covered	T7,T72,T20
StWaitFlash->StIdle	280	Covered	T16,T7,T59

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T7,T59
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T7,T59
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T7,T59
0	1	Covered	T4,T16,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T16,T7,T59
0	0	1	Covered	T16,T7,T59
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T13
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T7,T60
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T7,T59
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T7,T60
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T16,T7,T59
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T16,T7,T60
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T16,T7,T59
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T16,T7,T59
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T16,T7,T60
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T11,T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T7,T13,T72
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T16,T7,T59
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T7,T13,T72
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T7,T13,T72
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T7,T13,T72
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T7,T13,T72
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T13,T72
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T16,T7,T59
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T16,T7,T59
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T16,T7,T59
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T16,T7,T59
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T16,T7,T59
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T16,T7,T59
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T15,T11

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T16,T7,T59
0	0	1	-	-	Covered	T7,T13,T72
0	0	0	1	-	Covered	T7,T13,T72
0	0	0	0	1	Covered	T16,T7,T59
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T16,T7,T59
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	420163200	1184532	0	0
PostPackRule_A	420163200	12149	0	0
PrePackRule_A	420163200	6059	0	0
WidthCheck_A	1062	1062	0	0
u_state_regs_A	420163200	419306077	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	1184532	0	0
T5	144269	0	0	0
T6	824165	0	0	0
T7	306436	493	0	0
T8	0	306	0	0
T12	1124	0	0	0
T13	380300	32768	0	0
T16	260528	34	0	0
T17	5313	0	0	0
T18	1893	0	0	0
T20	0	1	0	0
T25	0	32800	0	0
T59	98080	54	0	0
T60	213493	425	0	0
T79	0	139	0	0
T104	0	55	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	12149	0	0
T5	144269	0	0	0
T6	824165	0	0	0
T7	306436	171	0	0
T8	0	86	0	0
T12	1124	0	0	0
T13	380300	0	0	0
T16	260528	21	0	0
T17	5313	0	0	0
T18	1893	0	0	0
T20	0	1	0	0
T44	0	1	0	0
T59	98080	0	0	0
T60	213493	170	0	0
T79	0	7	0	0
T88	0	8	0	0
T89	0	122	0	0
T104	0	1	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	6059	0	0
T5	144269	0	0	0
T6	824165	0	0	0
T7	306436	90	0	0
T8	0	42	0	0
T12	1124	0	0	0
T13	380300	0	0	0
T16	260528	13	0	0
T17	5313	0	0	0
T18	1893	0	0	0
T59	98080	0	0	0
T60	213493	59	0	0
T73	0	80	0	0
T79	0	6	0	0
T88	0	5	0	0
T89	0	73	0	0
T104	0	1	0	0
T234	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	64	98.46
Logical	65	64	98.46
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T16,T7

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T16,T7

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T146,T147,T9
1	0	Covered	T146,T147,T9

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T16,T7
1	1	Covered	T146,T147,T9

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T65,T257
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T146,T147,T9
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T16,T7

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T16,T7
1	Covered	T16,T7,T12

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T7
1	0	Covered	T1,T16,T7
1	1	Covered	T1,T16,T7

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T16,T7

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T16,T7
1	1	Covered	T16,T7,T18

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T14
1	Covered	T16,T7,T18

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T7
1	0	Covered	T1,T16,T7
1	1	Covered	T1,T16,T7

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T16,T7
1	Covered	T1,T16,T7

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T7
1	0	Covered	T1,T16,T7
1	1	Covered	T16,T7,T12

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T11,T14
1	Covered	T16,T7,T12

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T1,T16,T7
1	Covered	T18,T59,T12

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T16,T7
1	Covered	T1,T16,T7

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T16,T7
1	Covered	T1,T16,T7

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T16,T7
1	1	Covered	T1,T16,T7

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T59,T12
1	1	Covered	T18,T59,T12

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T59,T12
1	1	Covered	T18,T59,T12

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T16,T7
1	1	0	Covered	T1,T16,T7
1	1	1	Covered	T1,T16,T7

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T16,T7

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T18,T59,T12
StCalcMask	237	Covered	T18,T59,T12
StCalcPlainEcc	215	Covered	T1,T16,T7
StDisabled	193	Covered	T5,T12,T13
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T16,T7
StPostPack	218	Covered	T16,T7,T12
StPrePack	195	Covered	T16,T7,T18
StReqFlash	237	Covered	T1,T16,T7
StScrambleData	244	Covered	T18,T59,T12
StWaitFlash	270	Covered	T1,T16,T7

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T18,T59,T12
StCalcMask->StScrambleData	244	Covered	T18,T59,T12
StCalcPlainEcc->StCalcMask	237	Covered	T18,T59,T12
StCalcPlainEcc->StReqFlash	237	Covered	T1,T16,T7
StIdle->StDisabled	193	Covered	T5,T12,T13
StIdle->StPackData	197	Covered	T1,T16,T7
StIdle->StPrePack	195	Covered	T16,T7,T18
StPackData->StCalcPlainEcc	215	Covered	T1,T16,T7
StPackData->StPostPack	218	Covered	T16,T7,T12
StPostPack->StCalcPlainEcc	231	Covered	T16,T7,T12
StPrePack->StPackData	205	Covered	T16,T7,T18
StReqFlash->StIdle	273	Covered	T1,T16,T7
StReqFlash->StWaitFlash	270	Covered	T1,T16,T7
StScrambleData->StCalcEcc	252	Covered	T18,T59,T12
StWaitFlash->StIdle	280	Covered	T1,T16,T7

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T16,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T16,T7
0	0	1	Covered	T1,T16,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T13
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T7,T18
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T7
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T7,T18
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T7
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T16,T7,T12
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T16,T7
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T16,T7
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T16,T7,T12
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T11,T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T18,T59,T12
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T16,T7
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T18,T59,T12
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T18,T59,T12
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T18,T59,T12
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T18,T59,T12
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T59,T12
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T16,T7
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T16,T7
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T16,T7
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T1,T16,T7
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T16,T7
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T16,T7
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T15,T11

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T16,T7
0	0	1	-	-	Covered	T18,T59,T12
0	0	0	1	-	Covered	T18,T59,T12
0	0	0	0	1	Covered	T1,T16,T7
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T16,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	420163200	1215233	0	0
PostPackRule_A	420163200	16941	0	0
PrePackRule_A	420163200	8067	0	0
WidthCheck_A	1062	1062	0	0
u_state_regs_A	420163200	419306077	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	1215233	0	0
T1	54023	32	0	0
T2	3663	0	0	0
T3	3467	0	0	0
T4	10268	0	0	0
T5	144269	0	0	0
T6	824165	0	0	0
T7	306436	345	0	0
T8	0	833	0	0
T12	0	1	0	0
T13	0	33152	0	0
T16	260528	40	0	0
T17	5313	0	0	0
T18	1893	0	0	0
T46	0	57	0	0
T47	0	51	0	0
T59	0	46	0	0
T60	0	539	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	16941	0	0
T5	144269	0	0	0
T6	824165	0	0	0
T7	306436	136	0	0
T8	0	277	0	0
T12	1124	1	0	0
T13	380300	0	0	0
T16	260528	24	0	0
T17	5313	0	0	0
T18	1893	0	0	0
T42	0	2	0	0
T59	98080	0	0	0
T60	213493	188	0	0
T61	0	1	0	0
T79	0	5	0	0
T88	0	11	0	0
T89	0	178	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	8067	0	0
T5	144269	0	0	0
T6	824165	0	0	0
T7	306436	57	0	0
T8	0	145	0	0
T12	1124	1	0	0
T13	380300	0	0	0
T16	260528	16	0	0
T17	5313	0	0	0
T18	1893	1	0	0
T42	0	1	0	0
T59	98080	0	0	0
T60	213493	142	0	0
T79	0	3	0	0
T88	0	7	0	0
T89	0	74	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0