Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total995010
Category 0995010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total995010
Severity 0995010

Summary for Assertions
NUMBERPERCENT
Total Number995100.00
Uncovered171.71
Success97898.29
Failure00.00
Incomplete151.51
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered330.00
All Matches770.00
First Matches770.00
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ASSERTIONS   CATEGORY   SEVERITY   ATTEMPTS   REAL SUCCESSES   FAILURES   INCOMPLETE   
tb.dut.u_tl_adapter_eflash.rvalidHighWhenRspFifoFull 00392920580458931600
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A 001063106300
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_A 003929205803572171800
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A 0039292058039208317400
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A 0039292058039208317400
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A 0039292058039208317400
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 003929205803572171800
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A 001063106300
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck 001063106300
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_A 00392920580534375500
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A 0039292058039208317400
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A 0039292058039208317400
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A 0039292058039208317400
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00392920580534375500
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_A 003929205803496071000
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A 0039292058039208317400
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A 0039292058039208317400
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A 0039292058039208317400
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 003929205803496071000
tb.dut.u_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A 001063106300
tb.dut.u_tl_gate.u_err_en_sync.OutputsKnown_A 0038625511938541771300
tb.dut.u_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A 0038625511938541771300
tb.dut.u_tl_gate.u_state_regs.AssertConnected_A 001063106300
tb.dut.u_tl_gate.u_state_regs_A 0039292058039208317400
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A 001063106300
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck 001063106300
tb.dut.u_to_prog_fifo.AddrOutKnown_A 0039292058039208317400
tb.dut.u_to_prog_fifo.DataIntgOptions_A 001063106300
tb.dut.u_to_prog_fifo.ReqOutKnown_A 0039292058039208317400
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A 001063106300
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A 001063106300
tb.dut.u_to_prog_fifo.TlOutKnown_A 0039292058039208317400
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_A 00392920580273734800
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_AKnownEnable 0039292058039208317400
tb.dut.u_to_prog_fifo.WdataOutKnown_A 0039292058039208317400
tb.dut.u_to_prog_fifo.WeOutKnown_A 0039292058039208317400
tb.dut.u_to_prog_fifo.WmaskOutKnown_A 0039292058039208317400
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite 001063106300
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A 001063106300
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A 00392920580273734800
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A 0039292058039208317400
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A 0039292058039208317400
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A 0039292058039208317400
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00392920580273734800
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A 001063106300
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck 001063106300
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A 0039292058039208317400
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A 0039292058039208317400
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A 0039292058039208317400
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A 0039292058039208317400
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A 0039292058039208317400
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A 0039292058039208317400
tb.dut.u_to_rd_fifo.AddrOutKnown_A 0039292058039208317400
tb.dut.u_to_rd_fifo.DataIntgOptions_A 001063106300
tb.dut.u_to_rd_fifo.ReqOutKnown_A 0039292058039208317400
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A 001063106300
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A 001063106300
tb.dut.u_to_rd_fifo.TlOutKnown_A 0039292058039208317400
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_A 00392920580405644100
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_AKnownEnable 0039292058039208317400
tb.dut.u_to_rd_fifo.WdataOutKnown_A 0039292058039208317400
tb.dut.u_to_rd_fifo.WeOutKnown_A 0039292058039208317400
tb.dut.u_to_rd_fifo.WmaskOutKnown_A 0039292058039208317400
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite 001063106300
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty 00392920580332742800
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull 00392344795332061700
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A 001063106300
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A 00392920580405644100
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A 0039292058039208317400
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A 0039292058039208317400
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A 0039292058039208317400
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00392920580405644100
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A 001063106300
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck 001063106300
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A 00392755359404765400
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A 0039292058039208317400
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A 0039292058039208317400
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A 0039292058039208317400
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00392920580406156000
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A 00392920580332742800
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A 0039292058039208317400
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A 0039292058039208317400
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A 0039292058039208317400
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00392920580332742800

Assertions Incomplete:
ASSERTIONS   CATEGORY   SEVERITY   ATTEMPTS   REAL SUCCESSES   FAILURES   INCOMPLETE   SRC   
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A 003929205803376701057
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A 003929205802989601057
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A 0038625511938538479402781
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A 00392920580001057
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A 00392920580001057
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A 00392920580001057
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A 00392920580001057
tb.dut.u_flash_hw_if.DisableChk_A 003809445555677162050
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A 0038625518138538484102781
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A 0038623318238536299202631
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A 0038625518138538484102781
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0038625518138538484102781
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A 0038625518138538484102781
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A 0038625518138538484102781
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0038625518138538484102781

Detail Report for Cover Sequences

Cover Sequences Uncovered:
COVER SEQUENCES   CATEGORY   SEVERITY   ATTEMPTS   ALL MATCHES   FIRST MATCHES   INCOMPLETE   SRC   
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 00395869096000
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00395869096000
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00395869096000

Cover Sequences All Matches:
COVER SEQUENCES   CATEGORY   SEVERITY   ATTEMPTS   ALL MATCHES   FIRST MATCHES   INCOMPLETE   SRC   
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 003958690961058481058480
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0039586909618180
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00395869096660
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0039586909610100
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0039586909618855188550
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 003958690963359313359310
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0039586909619495247194952471252

Cover Sequences First Matches:
COVER SEQUENCES   CATEGORY   SEVERITY   ATTEMPTS   ALL MATCHES   FIRST MATCHES   INCOMPLETE   SRC   
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 003958690961058481058480
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0039586909618180
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00395869096660
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0039586909610100
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0039586909618855188550
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 003958690963359313359310
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0039586909619495247194952471252