Assertions
dashboard | hierarchy | modlist | groups | tests | asserts
Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total995010
Category 0995010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total995010
Severity 0995010

Summary for Assertions
NUMBERPERCENT
Total Number995100.00
Uncovered171.71
Success97898.29
Failure00.00
Incomplete151.51
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered330.00
All Matches770.00
First Matches770.00
Go previous page
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.u_tl_adapter_eflash.rvalidHighWhenRspFifoFull 00420913160458808000
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A 001058105800
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_A 004209131603661937500
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A 0042091316042003798700
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A 0042091316042003798700
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A 0042091316042003798700
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 004209131603661937500
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A 001058105800
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck 001058105800
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_A 00420913160615747600
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A 0042091316042003798700
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A 0042091316042003798700
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A 0042091316042003798700
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00420913160615747600
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_A 004209131603504200000
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A 0042091316042003798700
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A 0042091316042003798700
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A 0042091316042003798700
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 004209131603504200000
tb.dut.u_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A 001058105800
tb.dut.u_tl_gate.u_err_en_sync.OutputsKnown_A 0041543342041455824700
tb.dut.u_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A 0041543342041455824700
tb.dut.u_tl_gate.u_state_regs.AssertConnected_A 001058105800
tb.dut.u_tl_gate.u_state_regs_A 0042091316042003798700
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A 001058105800
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck 001058105800
tb.dut.u_to_prog_fifo.AddrOutKnown_A 0042091316042003798700
tb.dut.u_to_prog_fifo.DataIntgOptions_A 001058105800
tb.dut.u_to_prog_fifo.ReqOutKnown_A 0042091316042003798700
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A 001058105800
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A 001058105800
tb.dut.u_to_prog_fifo.TlOutKnown_A 0042091316042003798700
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_A 00420913160362803600
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_AKnownEnable 0042091316042003798700
tb.dut.u_to_prog_fifo.WdataOutKnown_A 0042091316042003798700
tb.dut.u_to_prog_fifo.WeOutKnown_A 0042091316042003798700
tb.dut.u_to_prog_fifo.WmaskOutKnown_A 0042091316042003798700
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite 001058105800
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A 001058105800
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A 00420913160362803600
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A 0042091316042003798700
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A 0042091316042003798700
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A 0042091316042003798700
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00420913160362803600
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A 001058105800
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck 001058105800
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A 0042091316042003798700
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A 0042091316042003798700
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A 0042091316042003798700
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A 0042091316042003798700
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A 0042091316042003798700
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A 0042091316042003798700
tb.dut.u_to_rd_fifo.AddrOutKnown_A 0042091316042003798700
tb.dut.u_to_rd_fifo.DataIntgOptions_A 001058105800
tb.dut.u_to_rd_fifo.ReqOutKnown_A 0042091316042003798700
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A 001058105800
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A 001058105800
tb.dut.u_to_rd_fifo.TlOutKnown_A 0042091316042003798700
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_A 00420913160495118300
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_AKnownEnable 0042091316042003798700
tb.dut.u_to_rd_fifo.WdataOutKnown_A 0042091316042003798700
tb.dut.u_to_rd_fifo.WeOutKnown_A 0042091316042003798700
tb.dut.u_to_rd_fifo.WmaskOutKnown_A 0042091316042003798700
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite 001058105800
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty 00420913160330508200
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull 00420293619329874300
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A 001058105800
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A 00420913160495118300
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A 0042091316042003798700
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A 0042091316042003798700
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A 0042091316042003798700
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00420913160495118300
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A 001058105800
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck 001058105800
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A 00420717781494121600
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A 0042091316042003798700
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A 0042091316042003798700
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A 0042091316042003798700
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00420913160495483500
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A 00420913160330508200
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A 0042091316042003798700
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A 0042091316042003798700
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A 0042091316042003798700
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00420913160330508200

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A 004209131603443801053
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A 004209131601898701053
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A 0041543342041452407402769
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A 00420913160001053
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A 00420913160001053
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A 00420913160001053
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A 00420913160001053
tb.dut.u_flash_hw_if.DisableChk_A 004089283345316681045
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A 0041543344441452408602769
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A 0041541001641450080802619
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A 0041543344441452408602769
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0041543344441452408602769
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A 0041543344441452408602769
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A 0041543344441452408602769
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0041543344441452408602769

Detail Report for Cover Sequences

Cover Sequences Uncovered:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 00423517640000
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00423517640000
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00423517640000

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 004235176401121811121810
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0042351764021210
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 0042351764012120
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00423517640770
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 00423517640964796470
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 004235176402912142912140
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0042351764020565074205650741248

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 004235176401121811121810
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0042351764021210
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 0042351764012120
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00423517640770
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 00423517640964796470
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 004235176402912142912140
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0042351764020565074205650741248