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Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_to_prog_fifo.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 100.00 68.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.36 100.00 75.00 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.25 100.00 66.67 84.62 85.71 u_to_prog_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 90.30 100.00 80.00 90.91

Go back
Module Instances:
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo
tb.dut.u_to_prog_fifo.u_reqfifo
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 438426742 33665796 0 0
DepthKnown_A 438426742 437476671 0 0
RvalidKnown_A 438426742 437476671 0 0
WreadyKnown_A 438426742 437476671 0 0
gen_passthru_fifo.paramCheckPass 1277 1277 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 33665796 0 0
T1 36336 17614 0 0
T2 1494 129 0 0
T3 834762 26188 0 0
T4 107254 15076 0 0
T5 4570 1931 0 0
T15 4780 1846 0 0
T16 159044 70698 0 0
T17 3239 150 0 0
T18 1898 229 0 0
T19 496992 28281 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1277 1277 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 438426742 43023110 0 0
DepthKnown_A 438426742 437476671 0 0
RvalidKnown_A 438426742 437476671 0 0
WreadyKnown_A 438426742 437476671 0 0
gen_passthru_fifo.paramCheckPass 1277 1277 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 43023110 0 0
T1 36336 17460 0 0
T2 1494 122 0 0
T3 834762 26188 0 0
T4 107254 15076 0 0
T5 4570 1450 0 0
T15 4780 1846 0 0
T16 159044 70698 0 0
T17 3239 150 0 0
T18 1898 229 0 0
T19 496992 28281 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1277 1277 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 438426742 2382568 0 0
DepthKnown_A 438426742 437476671 0 0
RvalidKnown_A 438426742 437476671 0 0
WreadyKnown_A 438426742 437476671 0 0
gen_passthru_fifo.paramCheckPass 1277 1277 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 2382568 0 0
T1 36336 951 0 0
T2 1494 0 0 0
T3 834762 0 0 0
T4 107254 5120 0 0
T5 4570 517 0 0
T15 4780 243 0 0
T16 159044 1512 0 0
T17 3239 0 0 0
T18 1898 32 0 0
T19 496992 18784 0 0
T20 0 7589 0 0
T23 0 16 0 0
T24 0 16 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1277 1277 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 438426742 3609202 0 0
DepthKnown_A 438426742 437476671 0 0
RvalidKnown_A 438426742 437476671 0 0
WreadyKnown_A 438426742 437476671 0 0
gen_passthru_fifo.paramCheckPass 1277 1277 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 3609202 0 0
T1 36336 951 0 0
T2 1494 0 0 0
T3 834762 0 0 0
T4 107254 5120 0 0
T5 4570 42 0 0
T15 4780 243 0 0
T16 159044 1512 0 0
T17 3239 0 0 0
T18 1898 32 0 0
T19 496992 18784 0 0
T20 0 14068 0 0
T23 0 16 0 0
T24 0 16 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1277 1277 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 438426742 4112329 0 0
DepthKnown_A 438426742 437476671 0 0
RvalidKnown_A 438426742 437476671 0 0
WreadyKnown_A 438426742 437476671 0 0
gen_passthru_fifo.paramCheckPass 1277 1277 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 4112329 0 0
T1 36336 1295 0 0
T2 1494 19 0 0
T3 834762 13440 0 0
T4 107254 4096 0 0
T5 4570 18 0 0
T15 4780 305 0 0
T16 159044 2896 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T20 0 4096 0 0
T22 0 160 0 0
T23 0 74 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1277 1277 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 438426742 4887785 0 0
DepthKnown_A 438426742 437476671 0 0
RvalidKnown_A 438426742 437476671 0 0
WreadyKnown_A 438426742 437476671 0 0
gen_passthru_fifo.paramCheckPass 1277 1277 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 4887785 0 0
T1 36336 1141 0 0
T2 1494 12 0 0
T3 834762 13440 0 0
T4 107254 4096 0 0
T5 4570 12 0 0
T15 4780 305 0 0
T16 159044 2896 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T20 0 12905 0 0
T22 0 160 0 0
T23 0 74 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1277 1277 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 438426742 27102106 0 0
DepthKnown_A 438426742 437476671 0 0
RvalidKnown_A 438426742 437476671 0 0
WreadyKnown_A 438426742 437476671 0 0
gen_passthru_fifo.paramCheckPass 1277 1277 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 27102106 0 0
T1 36336 15368 0 0
T2 1494 110 0 0
T3 834762 12748 0 0
T4 107254 5860 0 0
T5 4570 1396 0 0
T15 4780 1298 0 0
T16 159044 66290 0 0
T17 3239 150 0 0
T18 1898 197 0 0
T19 496992 9497 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1277 1277 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 438426742 34526123 0 0
DepthKnown_A 438426742 437476671 0 0
RvalidKnown_A 438426742 437476671 0 0
WreadyKnown_A 438426742 437476671 0 0
gen_passthru_fifo.paramCheckPass 1277 1277 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 34526123 0 0
T1 36336 15368 0 0
T2 1494 110 0 0
T3 834762 12748 0 0
T4 107254 5860 0 0
T5 4570 1396 0 0
T15 4780 1298 0 0
T16 159044 66290 0 0
T17 3239 150 0 0
T18 1898 197 0 0
T19 496992 9497 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438426742 437476671 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1277 1277 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo
TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T4,T15
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T4,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T15,T20
110Not Covered
111CoveredT1,T4,T15

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T4,T15
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T15


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T4,T15
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 435599635 3581913 0 0
DepthKnown_A 435599635 434729124 0 0
RvalidKnown_A 435599635 434729124 0 0
WreadyKnown_A 435599635 434729124 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 435599635 3581913 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 3581913 0 0
T1 36336 951 0 0
T2 1494 0 0 0
T3 834762 0 0 0
T4 107254 5120 0 0
T5 4570 42 0 0
T15 4780 243 0 0
T16 159044 1512 0 0
T17 3239 0 0 0
T18 1898 32 0 0
T19 496992 18784 0 0
T20 0 14068 0 0
T23 0 16 0 0
T24 0 16 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 3581913 0 0
T1 36336 951 0 0
T2 1494 0 0 0
T3 834762 0 0 0
T4 107254 5120 0 0
T5 4570 42 0 0
T15 4780 243 0 0
T16 159044 1512 0 0
T17 3239 0 0 0
T18 1898 32 0 0
T19 496992 18784 0 0
T20 0 14068 0 0
T23 0 16 0 0
T24 0 16 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%