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Module Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
67.47 85.71 38.46 85.71 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.63 94.44 54.84 81.25 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.25 100.00 66.67 84.62 85.71 u_to_prog_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.48 100.00 66.67 77.78


Module Instance : tb.dut.u_to_prog_fifo.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.27 92.31 47.06 85.71 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.33 91.43 57.14 68.75 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.25 100.00 66.67 84.62 85.71 u_to_prog_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 71.04 90.91 66.67 55.56


Module Instance : tb.dut.u_prog_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 100.00 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.34 97.12 92.80 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_to_rd_fifo.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 100.00 68.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.36 100.00 75.00 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.86 100.00 79.13 96.30 100.00 u_to_rd_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 90.30 100.00 80.00 90.91


Module Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.62 100.00 62.50 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 72.22 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.86 100.00 79.13 96.30 100.00 u_to_rd_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 90.30 100.00 80.00 90.91


Module Instance : tb.dut.u_to_rd_fifo.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 100.00 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.30 100.00 91.49 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.86 100.00 79.13 96.30 100.00 u_to_rd_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_sw_rd_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.79 100.00 79.17 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.67 95.12 88.64 90.91 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.34 97.12 92.80 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 92.40 92.59 100.00 84.62


Module Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 100.00 68.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.53 100.00 86.11 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.41 100.00 85.34 96.30 100.00 u_tl_adapter_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 100.00 68.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.53 100.00 86.11 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.41 100.00 85.34 96.30 100.00 u_tl_adapter_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00

Go back
Module Instances:
tb.dut.u_to_prog_fifo.u_sramreqfifo
tb.dut.u_to_prog_fifo.u_rspfifo
tb.dut.u_prog_fifo
tb.dut.u_to_rd_fifo.u_reqfifo
tb.dut.u_to_rd_fifo.u_sramreqfifo
tb.dut.u_to_rd_fifo.u_rspfifo
tb.dut.u_sw_rd_fifo
tb.dut.u_tl_adapter_eflash.u_reqfifo
tb.dut.u_tl_adapter_eflash.u_sramreqfifo
Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL141285.71
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10100
CONT_ASSIGN108100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN133100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 unreachable
108 0 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 0 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo
TotalCoveredPercent
Conditions13538.46
Logical13538.46
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Unreachable
101Not Covered
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 7 6 85.71
TERNARY 138 2 1 50.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T6
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 435599635 0 0 0
DepthKnown_A 435599635 434729124 0 0
RvalidKnown_A 435599635 434729124 0 0
WreadyKnown_A 435599635 434729124 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 435599635 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 0 0 0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo
Line No.TotalCoveredPercent
TOTAL131292.31
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10000
CONT_ASSIGN10111100.00
CONT_ASSIGN108100.00
ALWAYS11111100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 unreachable
101 1 1
108 0 1
111 1 1
112 unreachable
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo
TotalCoveredPercent
Conditions17847.06
Logical17847.06
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01Not Covered
10Unreachable
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo
Line No.TotalCoveredPercent
Branches 7 6 85.71
TERNARY 130 1 1 100.00
TERNARY 138 2 1 50.00
IF 69 3 3 100.00
IF 111 1 1 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Unreachable
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Unreachable
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 435599635 0 0 0
DepthKnown_A 435599635 434729124 0 0
RvalidKnown_A 435599635 434729124 0 0
WreadyKnown_A 435599635 434729124 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 435599635 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 0 0 0

Line Coverage for Instance : tb.dut.u_prog_fifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_prog_fifo
TotalCoveredPercent
Conditions242083.33
Logical242083.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T5,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT5,T20,T27
110Not Covered
111CoveredT1,T4,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T4,T15
110Not Covered
111CoveredT1,T4,T15

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T15

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T16,T5
10CoveredT1,T2,T3
11CoveredT1,T4,T15

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T4,T15
10CoveredT1,T4,T15
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T4,T15
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_prog_fifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T15


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T4,T15
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_prog_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 435599635 195322528 0 0
DepthKnown_A 435599635 434729124 0 0
RvalidKnown_A 435599635 434729124 0 0
WreadyKnown_A 435599635 434729124 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 435599635 195322528 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 195322528 0 0
T1 36336 23187 0 0
T2 1494 0 0 0
T3 834762 0 0 0
T4 107254 5440 0 0
T5 4570 1402 0 0
T15 4780 282 0 0
T16 159044 43092 0 0
T17 3239 0 0 0
T18 1898 145 0 0
T19 496992 494598 0 0
T20 0 17993 0 0
T23 0 444 0 0
T24 0 563 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 195322528 0 0
T1 36336 23187 0 0
T2 1494 0 0 0
T3 834762 0 0 0
T4 107254 5440 0 0
T5 4570 1402 0 0
T15 4780 282 0 0
T16 159044 43092 0 0
T17 3239 0 0 0
T18 1898 145 0 0
T19 496992 494598 0 0
T20 0 17993 0 0
T23 0 444 0 0
T24 0 563 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo
TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T15,T20
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 435599635 4884335 0 0
DepthKnown_A 435599635 434729124 0 0
RvalidKnown_A 435599635 434729124 0 0
WreadyKnown_A 435599635 434729124 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 435599635 4884335 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 4884335 0 0
T1 36336 1141 0 0
T2 1494 12 0 0
T3 834762 13440 0 0
T4 107254 4096 0 0
T5 4570 12 0 0
T15 4780 305 0 0
T16 159044 2896 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T20 0 12905 0 0
T22 0 160 0 0
T23 0 74 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 4884335 0 0
T1 36336 1141 0 0
T2 1494 12 0 0
T3 834762 13440 0 0
T4 107254 4096 0 0
T5 4570 12 0 0
T15 4780 305 0 0
T16 159044 2896 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T20 0 12905 0 0
T22 0 160 0 0
T23 0 74 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo
TotalCoveredPercent
Conditions161062.50
Logical161062.50
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 435599635 3298015 0 0
DepthKnown_A 435599635 434729124 0 0
RvalidKnown_A 435599635 434729124 0 0
WreadyKnown_A 435599635 434729124 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 435599635 3298015 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 3298015 0 0
T1 36336 1141 0 0
T2 1494 12 0 0
T3 834762 13440 0 0
T4 107254 4096 0 0
T5 4570 12 0 0
T15 4780 305 0 0
T16 159044 2896 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T20 0 4096 0 0
T22 0 160 0 0
T23 0 74 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 3298015 0 0
T1 36336 1141 0 0
T2 1494 12 0 0
T3 834762 13440 0 0
T4 107254 4096 0 0
T5 4570 12 0 0
T15 4780 305 0 0
T16 159044 2896 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T20 0 4096 0 0
T22 0 160 0 0
T23 0 74 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
TotalCoveredPercent
Conditions242083.33
Logical242083.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT20,T27,T44
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT13,T14,T36
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T15,T20
110Not Covered
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT13,T14,T36
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT20,T27,T44
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 435432772 4876888 0 0
DepthKnown_A 435599635 434729124 0 0
RvalidKnown_A 435599635 434729124 0 0
WreadyKnown_A 435599635 434729124 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 435599635 4890193 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435432772 4876888 0 0
T1 36336 1141 0 0
T2 1494 12 0 0
T3 834762 13440 0 0
T4 107254 4096 0 0
T5 4570 12 0 0
T15 4780 305 0 0
T16 159044 2896 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T20 0 12905 0 0
T22 0 160 0 0
T23 0 74 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 4890193 0 0
T1 36336 1141 0 0
T2 1494 12 0 0
T3 834762 13440 0 0
T4 107254 4096 0 0
T5 4570 12 0 0
T15 4780 305 0 0
T16 159044 2896 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T20 0 12905 0 0
T22 0 160 0 0
T23 0 74 0 0

Line Coverage for Instance : tb.dut.u_sw_rd_fifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_sw_rd_fifo
TotalCoveredPercent
Conditions241979.17
Logical241979.17
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T20,T27
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_sw_rd_fifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_sw_rd_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 435599635 52162141 0 0
DepthKnown_A 435599635 434729124 0 0
RvalidKnown_A 435599635 434729124 0 0
WreadyKnown_A 435599635 434729124 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 435599635 52162141 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 52162141 0 0
T1 36336 4911 0 0
T2 1494 24 0 0
T3 834762 652832 0 0
T4 107254 57302 0 0
T5 4570 25 0 0
T15 4780 1273 0 0
T16 159044 12239 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T20 0 74551 0 0
T22 0 703 0 0
T23 0 317 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 52162141 0 0
T1 36336 4911 0 0
T2 1494 24 0 0
T3 834762 652832 0 0
T4 107254 57302 0 0
T5 4570 25 0 0
T15 4780 1273 0 0
T16 159044 12239 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T20 0 74551 0 0
T22 0 703 0 0
T23 0 317 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo
TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T3,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T3,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T15
110Not Covered
111CoveredT1,T3,T15

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T3,T15
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T15


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T3,T15
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 435599635 36048739 0 0
DepthKnown_A 435599635 434729124 0 0
RvalidKnown_A 435599635 434729124 0 0
WreadyKnown_A 435599635 434729124 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 435599635 36048739 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 36048739 0 0
T1 36336 252 0 0
T2 1494 0 0 0
T3 834762 587813 0 0
T4 107254 0 0 0
T5 4570 758 0 0
T15 4780 8 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 42395 0 0
T22 0 44 0 0
T23 0 24 0 0
T24 0 15 0 0
T31 0 37609 0 0
T39 0 703 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 36048739 0 0
T1 36336 252 0 0
T2 1494 0 0 0
T3 834762 587813 0 0
T4 107254 0 0 0
T5 4570 758 0 0
T15 4780 8 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 42395 0 0
T22 0 44 0 0
T23 0 24 0 0
T24 0 15 0 0
T31 0 37609 0 0
T39 0 703 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo
TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T3,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T3,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T15
110Not Covered
111CoveredT1,T3,T15

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T3,T15
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T15


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T3,T15
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 435599635 34795957 0 0
DepthKnown_A 435599635 434729124 0 0
RvalidKnown_A 435599635 434729124 0 0
WreadyKnown_A 435599635 434729124 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 435599635 34795957 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 34795957 0 0
T1 36336 252 0 0
T2 1494 0 0 0
T3 834762 587813 0 0
T4 107254 0 0 0
T5 4570 758 0 0
T15 4780 8 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 42395 0 0
T22 0 44 0 0
T23 0 24 0 0
T24 0 15 0 0
T31 0 37609 0 0
T39 0 448 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 34795957 0 0
T1 36336 252 0 0
T2 1494 0 0 0
T3 834762 587813 0 0
T4 107254 0 0 0
T5 4570 758 0 0
T15 4780 8 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 42395 0 0
T22 0 44 0 0
T23 0 24 0 0
T24 0 15 0 0
T31 0 37609 0 0
T39 0 448 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%