Unified Coverage Report :: Module Instance :: tb.dut.u_tl_adapter_eflash.u_rspfifo

Module Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.16	100.00	88.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.41	100.00	85.34			96.30	100.00	u_tl_adapter_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.u_bank_sequence_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.53	100.00	86.11			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.89	97.67	84.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.09	100.00	92.86		87.50	100.00		gen_prim_flash_banks[0].u_prim_flash_bank

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.65	100.00	92.86		93.75	100.00		gen_prim_flash_banks[1].u_prim_flash_bank

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.60	100.00	82.98	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.89	97.67	84.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	97.83	100.00	91.30	100.00		100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.44	100.00	87.18	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.74	100.00	90.97			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.44	100.00	87.18	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.74	100.00	90.97			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	80.56			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.74	100.00	90.97			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.60	100.00	82.98	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.89	97.67	84.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	97.83	100.00	91.30	100.00		100.00

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T37,T45,T46
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T21
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T15

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T15

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T37,T45,T46
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T15

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T47,T48,T49
1	0	Covered	T1,T3,T15
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T15

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	435599635	5834566	0	0
DepthKnown_A	435599635	434729124	0	0
RvalidKnown_A	435599635	434729124	0	0
WreadyKnown_A	435599635	434729124	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	435599635	5834566	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	5834566	0	0
T1	36336	124	0	0
T2	1494	0	0	0
T3	834762	16117	0	0
T4	107254	0	0	0
T5	4570	115	0	0
T15	4780	4	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	0	0	0
T19	496992	0	0	0
T21	0	16135	0	0
T22	0	18	0	0
T23	0	6	0	0
T24	0	6	0	0
T31	0	16400	0	0
T39	0	291	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	5834566	0	0
T1	36336	124	0	0
T2	1494	0	0	0
T3	834762	16117	0	0
T4	107254	0	0	0
T5	4570	115	0	0
T15	4780	4	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	0	0	0
T19	496992	0	0	0
T21	0	16135	0	0
T22	0	18	0	0
T23	0	6	0	0
T24	0	6	0	0
T31	0	16400	0	0
T39	0	291	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T15
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T15

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T15

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	435599635	34795957	0	0
DepthKnown_A	435599635	434729124	0	0
RvalidKnown_A	435599635	434729124	0	0
WreadyKnown_A	435599635	434729124	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	435599635	34795957	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	34795957	0	0
T1	36336	252	0	0
T2	1494	0	0	0
T3	834762	587813	0	0
T4	107254	0	0	0
T5	4570	758	0	0
T15	4780	8	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	0	0	0
T19	496992	0	0	0
T21	0	42395	0	0
T22	0	44	0	0
T23	0	24	0	0
T24	0	15	0	0
T31	0	37609	0	0
T39	0	448	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	34795957	0	0
T1	36336	252	0	0
T2	1494	0	0	0
T3	834762	587813	0	0
T4	107254	0	0	0
T5	4570	758	0	0
T15	4780	8	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	0	0	0
T19	496992	0	0	0
T21	0	42395	0	0
T22	0	44	0	0
T23	0	24	0	0
T24	0	15	0	0
T31	0	37609	0	0
T39	0	448	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T16,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T16
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	435599635	98693257	0	0
DepthKnown_A	435599635	434729124	0	0
RvalidKnown_A	435599635	434729124	0	0
WreadyKnown_A	435599635	434729124	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	435599635	98693257	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	98693257	0	0
T1	36336	8465	0	0
T2	1494	38	0	0
T3	834762	10916	0	0
T4	107254	290	0	0
T5	4570	2021	0	0
T15	4780	102	0	0
T16	159044	95002	0	0
T17	3239	32	0	0
T18	1898	64	0	0
T19	496992	289775	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	98693257	0	0
T1	36336	8465	0	0
T2	1494	38	0	0
T3	834762	10916	0	0
T4	107254	290	0	0
T5	4570	2021	0	0
T15	4780	102	0	0
T16	159044	95002	0	0
T17	3239	32	0	0
T18	1898	64	0	0
T19	496992	289775	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T5,T18
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T5,T18
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	435599635	101377096	0	0
DepthKnown_A	435599635	434729124	0	0
RvalidKnown_A	435599635	434729124	0	0
WreadyKnown_A	435599635	434729124	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	435599635	101377096	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	101377096	0	0
T1	36336	12964	0	0
T2	1494	0	0	0
T3	834762	12726	0	0
T4	107254	0	0	0
T5	4570	353	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	112	0	0
T19	496992	203946	0	0
T21	0	8347	0	0
T23	0	474	0	0
T24	0	584	0	0
T25	0	157936	0	0
T31	0	12530	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	101377096	0	0
T1	36336	12964	0	0
T2	1494	0	0	0
T3	834762	12726	0	0
T4	107254	0	0	0
T5	4570	353	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	112	0	0
T19	496992	203946	0	0
T21	0	8347	0	0
T23	0	474	0	0
T24	0	584	0	0
T25	0	157936	0	0
T31	0	12530	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T50,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T31,T50,T29
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T15

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T15

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T15

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T31,T50,T29
1	0	Covered	T1,T3,T15
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T15

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	435432772	2725415	0	0
DepthKnown_A	435432772	434562261	0	0
RvalidKnown_A	435432772	434562261	0	0
WreadyKnown_A	435432772	434562261	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	435432772	2725415	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	2725415	0	0
T1	36336	67	0	0
T2	1494	0	0	0
T3	834762	7811	0	0
T4	107254	0	0	0
T5	4570	72	0	0
T15	4780	4	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	0	0	0
T19	496992	0	0	0
T21	0	8181	0	0
T22	0	18	0	0
T31	0	10050	0	0
T39	0	129	0	0
T40	0	8509	0	0
T42	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	434562261	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	434562261	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	434562261	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	2725415	0	0
T1	36336	67	0	0
T2	1494	0	0	0
T3	834762	7811	0	0
T4	107254	0	0	0
T5	4570	72	0	0
T15	4780	4	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	0	0	0
T19	496992	0	0	0
T21	0	8181	0	0
T22	0	18	0	0
T31	0	10050	0	0
T39	0	129	0	0
T40	0	8509	0	0
T42	0	3	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T31
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	435432772	52731837	0	0
DepthKnown_A	435432772	434562261	0	0
RvalidKnown_A	435432772	434562261	0	0
WreadyKnown_A	435432772	434562261	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	435432772	52731837	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	52731837	0	0
T1	36336	1243	0	0
T2	1494	146	0	0
T3	834762	559201	0	0
T4	107254	64	0	0
T5	4570	663	0	0
T15	4780	496	0	0
T16	159044	23176	0	0
T17	3239	128	0	0
T18	1898	256	0	0
T19	496992	1696	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	434562261	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	434562261	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	434562261	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	52731837	0	0
T1	36336	1243	0	0
T2	1494	146	0	0
T3	834762	559201	0	0
T4	107254	64	0	0
T5	4570	663	0	0
T15	4780	496	0	0
T16	159044	23176	0	0
T17	3239	128	0	0
T18	1898	256	0	0
T19	496992	1696	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T36
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	435432772	13815037	0	0
DepthKnown_A	435432772	434562261	0	0
RvalidKnown_A	435432772	434562261	0	0
WreadyKnown_A	435432772	434562261	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	435432772	13815037	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	13815037	0	0
T1	36336	523	0	0
T2	1494	70	0	0
T3	834762	10949	0	0
T4	107254	32	0	0
T5	4570	103	0	0
T15	4780	192	0	0
T16	159044	10832	0	0
T17	3239	64	0	0
T18	1898	128	0	0
T19	496992	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	434562261	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	434562261	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	434562261	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	13815037	0	0
T1	36336	523	0	0
T2	1494	70	0	0
T3	834762	10949	0	0
T4	107254	32	0	0
T5	4570	103	0	0
T15	4780	192	0	0
T16	159044	10832	0	0
T17	3239	64	0	0
T18	1898	128	0	0
T19	496992	64	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	435599635	12749734	0	0
DepthKnown_A	435599635	434729124	0	0
RvalidKnown_A	435599635	434729124	0	0
WreadyKnown_A	435599635	434729124	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	435599635	12749734	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	12749734	0	0
T1	36336	514	0	0
T2	1494	64	0	0
T3	834762	1750	0	0
T4	107254	0	0	0
T5	4570	64	0	0
T15	4780	180	0	0
T16	159044	10832	0	0
T17	3239	64	0	0
T18	1898	128	0	0
T19	496992	1632	0	0
T38	0	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	12749734	0	0
T1	36336	514	0	0
T2	1494	64	0	0
T3	834762	1750	0	0
T4	107254	0	0	0
T5	4570	64	0	0
T15	4780	180	0	0
T16	159044	10832	0	0
T17	3239	64	0	0
T18	1898	128	0	0
T19	496992	1632	0	0
T38	0	64	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T31,T33
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T31,T33
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T31,T33
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	435432772	3433353	0	0
DepthKnown_A	435432772	434562261	0	0
RvalidKnown_A	435432772	434562261	0	0
WreadyKnown_A	435432772	434562261	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	435432772	3433353	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	3433353	0	0
T1	36336	76	0	0
T2	1494	0	0	0
T3	834762	8306	0	0
T4	107254	0	0	0
T5	4570	43	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	0	0	0
T19	496992	0	0	0
T21	0	7954	0	0
T23	0	6	0	0
T24	0	6	0	0
T31	0	8677	0	0
T33	0	10431	0	0
T39	0	162	0	0
T40	0	8052	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	434562261	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	434562261	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	434562261	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	435432772	3433353	0	0
T1	36336	76	0	0
T2	1494	0	0	0
T3	834762	8306	0	0
T4	107254	0	0	0
T5	4570	43	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	0	0	0
T19	496992	0	0	0
T21	0	7954	0	0
T23	0	6	0	0
T24	0	6	0	0
T31	0	8677	0	0
T33	0	10431	0	0
T39	0	162	0	0
T40	0	8052	0	0