Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T9
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T9

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1651839064	1648649060	0	0
CheckNGreaterZero_A	4248	4248	0	0
GntImpliesReady_A	1651839064	459544803	0	0
GntImpliesValid_A	1651839064	459544803	0	0
GrantKnown_A	1651839064	1648649060	0	0
IdxKnown_A	1651839064	1648649060	0	0
IndexIsCorrect_A	1651839064	459544803	0	0
NoReadyValidNoGrant_A	1651839064	180764146	0	0
Priority_A	1651839064	484191441	0	0
ReadyAndValidImplyGrant_A	1651839064	459544803	0	0
ReqAndReadyImplyGrant_A	1651839064	459544803	0	0
ReqImpliesValid_A	1651839064	484191441	0	0
ValidKnown_A	1651839064	1648649060	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651839064	1648649060	0	0
T1	15436	13004	0	0
T2	4756	3688	0	0
T3	1993060	1993024	0	0
T4	279904	279504	0	0
T5	165644	165392	0	0
T6	361384	361052	0	0
T8	438648	437924	0	0
T9	278988	278704	0	0
T16	2061724	2061336	0	0
T17	8948	8564	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4248	4248	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651839064	459544803	0	0
T1	7718	280	0	0
T2	2378	134	0	0
T3	1993060	991662	0	0
T4	279904	134014	0	0
T5	165644	59006	0	0
T6	361384	28606	0	0
T7	0	26372	0	0
T8	438648	65858	0	0
T9	278988	134414	0	0
T16	2061724	960844	0	0
T17	8948	64	0	0
T23	8334	0	0	0
T24	0	29796	0	0
T33	4648	292	0	0
T54	0	247	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651839064	459544803	0	0
T1	7718	280	0	0
T2	2378	134	0	0
T3	1993060	991662	0	0
T4	279904	134014	0	0
T5	165644	59006	0	0
T6	361384	28606	0	0
T7	0	26372	0	0
T8	438648	65858	0	0
T9	278988	134414	0	0
T16	2061724	960844	0	0
T17	8948	64	0	0
T23	8334	0	0	0
T24	0	29796	0	0
T33	4648	292	0	0
T54	0	247	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651839064	1648649060	0	0
T1	15436	13004	0	0
T2	4756	3688	0	0
T3	1993060	1993024	0	0
T4	279904	279504	0	0
T5	165644	165392	0	0
T6	361384	361052	0	0
T8	438648	437924	0	0
T9	278988	278704	0	0
T16	2061724	2061336	0	0
T17	8948	8564	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651839064	1648649060	0	0
T1	15436	13004	0	0
T2	4756	3688	0	0
T3	1993060	1993024	0	0
T4	279904	279504	0	0
T5	165644	165392	0	0
T6	361384	361052	0	0
T8	438648	437924	0	0
T9	278988	278704	0	0
T16	2061724	2061336	0	0
T17	8948	8564	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651839064	459544803	0	0
T1	7718	280	0	0
T2	2378	134	0	0
T3	1993060	991662	0	0
T4	279904	134014	0	0
T5	165644	59006	0	0
T6	361384	28606	0	0
T7	0	26372	0	0
T8	438648	65858	0	0
T9	278988	134414	0	0
T16	2061724	960844	0	0
T17	8948	64	0	0
T23	8334	0	0	0
T24	0	29796	0	0
T33	4648	292	0	0
T54	0	247	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651839064	180764146	0	0
T1	7718	928	0	0
T2	2378	536	0	0
T3	996530	3392	0	0
T4	279904	1432	0	0
T5	165644	2192	0	0
T6	361384	256	0	0
T7	0	899956	0	0
T8	438648	183550	0	0
T9	278988	826	0	0
T13	2314	0	0	0
T16	2061724	3456	0	0
T17	8948	256	0	0
T23	8334	0	0	0
T24	0	46956	0	0
T33	4648	438	0	0
T54	0	250	0	0
T60	0	1048576	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651839064	484191441	0	0
T1	7718	280	0	0
T2	2378	134	0	0
T3	1993060	991662	0	0
T4	279904	134294	0	0
T5	165644	59006	0	0
T6	361384	28606	0	0
T7	0	185328	0	0
T8	438648	69918	0	0
T9	278988	134454	0	0
T16	2061724	960844	0	0
T17	8948	64	0	0
T23	8334	0	0	0
T24	0	34598	0	0
T33	4648	292	0	0
T54	0	261	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651839064	459544803	0	0
T1	7718	280	0	0
T2	2378	134	0	0
T3	1993060	991662	0	0
T4	279904	134014	0	0
T5	165644	59006	0	0
T6	361384	28606	0	0
T7	0	26372	0	0
T8	438648	65858	0	0
T9	278988	134414	0	0
T16	2061724	960844	0	0
T17	8948	64	0	0
T23	8334	0	0	0
T24	0	29796	0	0
T33	4648	292	0	0
T54	0	247	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651839064	459544803	0	0
T1	7718	280	0	0
T2	2378	134	0	0
T3	1993060	991662	0	0
T4	279904	134014	0	0
T5	165644	59006	0	0
T6	361384	28606	0	0
T7	0	26372	0	0
T8	438648	65858	0	0
T9	278988	134414	0	0
T16	2061724	960844	0	0
T17	8948	64	0	0
T23	8334	0	0	0
T24	0	29796	0	0
T33	4648	292	0	0
T54	0	247	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651839064	484191441	0	0
T1	7718	280	0	0
T2	2378	134	0	0
T3	1993060	991662	0	0
T4	279904	134294	0	0
T5	165644	59006	0	0
T6	361384	28606	0	0
T7	0	185328	0	0
T8	438648	69918	0	0
T9	278988	134454	0	0
T16	2061724	960844	0	0
T17	8948	64	0	0
T23	8334	0	0	0
T24	0	34598	0	0
T33	4648	292	0	0
T54	0	261	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651839064	1648649060	0	0
T1	15436	13004	0	0
T2	4756	3688	0	0
T3	1993060	1993024	0	0
T4	279904	279504	0	0
T5	165644	165392	0	0
T6	361384	361052	0	0
T8	438648	437924	0	0
T9	278988	278704	0	0
T16	2061724	2061336	0	0
T17	8948	8564	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T9
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T9

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412959766	412162265	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	412959766	124253198	0	0
GntImpliesValid_A	412959766	124253198	0	0
GrantKnown_A	412959766	412162265	0	0
IdxKnown_A	412959766	412162265	0	0
IndexIsCorrect_A	412959766	124253198	0	0
NoReadyValidNoGrant_A	412959766	47130926	0	0
Priority_A	412959766	130543924	0	0
ReadyAndValidImplyGrant_A	412959766	124253198	0	0
ReqAndReadyImplyGrant_A	412959766	124253198	0	0
ReqImpliesValid_A	412959766	130543924	0	0
ValidKnown_A	412959766	412162265	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	124253198	0	0
T1	3859	140	0	0
T2	1189	67	0	0
T3	498265	257887	0	0
T4	69976	544	0	0
T5	41411	12453	0	0
T6	90346	14303	0	0
T8	109662	20454	0	0
T9	69747	66188	0	0
T16	515431	143124	0	0
T17	2237	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	124253198	0	0
T1	3859	140	0	0
T2	1189	67	0	0
T3	498265	257887	0	0
T4	69976	544	0	0
T5	41411	12453	0	0
T6	90346	14303	0	0
T8	109662	20454	0	0
T9	69747	66188	0	0
T16	515431	143124	0	0
T17	2237	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	124253198	0	0
T1	3859	140	0	0
T2	1189	67	0	0
T3	498265	257887	0	0
T4	69976	544	0	0
T5	41411	12453	0	0
T6	90346	14303	0	0
T8	109662	20454	0	0
T9	69747	66188	0	0
T16	515431	143124	0	0
T17	2237	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	47130926	0	0
T1	3859	464	0	0
T2	1189	268	0	0
T3	498265	1696	0	0
T4	69976	444	0	0
T5	41411	908	0	0
T6	90346	128	0	0
T8	109662	55649	0	0
T9	69747	343	0	0
T16	515431	1030	0	0
T17	2237	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	130543924	0	0
T1	3859	140	0	0
T2	1189	67	0	0
T3	498265	257887	0	0
T4	69976	597	0	0
T5	41411	12453	0	0
T6	90346	14303	0	0
T8	109662	21210	0	0
T9	69747	66208	0	0
T16	515431	143124	0	0
T17	2237	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	124253198	0	0
T1	3859	140	0	0
T2	1189	67	0	0
T3	498265	257887	0	0
T4	69976	544	0	0
T5	41411	12453	0	0
T6	90346	14303	0	0
T8	109662	20454	0	0
T9	69747	66188	0	0
T16	515431	143124	0	0
T17	2237	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	124253198	0	0
T1	3859	140	0	0
T2	1189	67	0	0
T3	498265	257887	0	0
T4	69976	544	0	0
T5	41411	12453	0	0
T6	90346	14303	0	0
T8	109662	20454	0	0
T9	69747	66188	0	0
T16	515431	143124	0	0
T17	2237	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	130543924	0	0
T1	3859	140	0	0
T2	1189	67	0	0
T3	498265	257887	0	0
T4	69976	597	0	0
T5	41411	12453	0	0
T6	90346	14303	0	0
T8	109662	21210	0	0
T9	69747	66208	0	0
T16	515431	143124	0	0
T17	2237	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T9
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T9

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412959766	412162265	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	412959766	124253209	0	0
GntImpliesValid_A	412959766	124253209	0	0
GrantKnown_A	412959766	412162265	0	0
IdxKnown_A	412959766	412162265	0	0
IndexIsCorrect_A	412959766	124253209	0	0
NoReadyValidNoGrant_A	412959766	47130854	0	0
Priority_A	412959766	130544007	0	0
ReadyAndValidImplyGrant_A	412959766	124253209	0	0
ReqAndReadyImplyGrant_A	412959766	124253209	0	0
ReqImpliesValid_A	412959766	130544007	0	0
ValidKnown_A	412959766	412162265	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	124253209	0	0
T1	3859	140	0	0
T2	1189	67	0	0
T3	498265	257887	0	0
T4	69976	544	0	0
T5	41411	12453	0	0
T6	90346	14303	0	0
T8	109662	20454	0	0
T9	69747	66188	0	0
T16	515431	143124	0	0
T17	2237	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	124253209	0	0
T1	3859	140	0	0
T2	1189	67	0	0
T3	498265	257887	0	0
T4	69976	544	0	0
T5	41411	12453	0	0
T6	90346	14303	0	0
T8	109662	20454	0	0
T9	69747	66188	0	0
T16	515431	143124	0	0
T17	2237	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	124253209	0	0
T1	3859	140	0	0
T2	1189	67	0	0
T3	498265	257887	0	0
T4	69976	544	0	0
T5	41411	12453	0	0
T6	90346	14303	0	0
T8	109662	20454	0	0
T9	69747	66188	0	0
T16	515431	143124	0	0
T17	2237	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	47130854	0	0
T1	3859	464	0	0
T2	1189	268	0	0
T3	498265	1696	0	0
T4	69976	444	0	0
T5	41411	908	0	0
T6	90346	128	0	0
T8	109662	55649	0	0
T9	69747	343	0	0
T16	515431	1030	0	0
T17	2237	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	130544007	0	0
T1	3859	140	0	0
T2	1189	67	0	0
T3	498265	257887	0	0
T4	69976	597	0	0
T5	41411	12453	0	0
T6	90346	14303	0	0
T8	109662	21210	0	0
T9	69747	66208	0	0
T16	515431	143124	0	0
T17	2237	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	124253209	0	0
T1	3859	140	0	0
T2	1189	67	0	0
T3	498265	257887	0	0
T4	69976	544	0	0
T5	41411	12453	0	0
T6	90346	14303	0	0
T8	109662	20454	0	0
T9	69747	66188	0	0
T16	515431	143124	0	0
T17	2237	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	124253209	0	0
T1	3859	140	0	0
T2	1189	67	0	0
T3	498265	257887	0	0
T4	69976	544	0	0
T5	41411	12453	0	0
T6	90346	14303	0	0
T8	109662	20454	0	0
T9	69747	66188	0	0
T16	515431	143124	0	0
T17	2237	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	130544007	0	0
T1	3859	140	0	0
T2	1189	67	0	0
T3	498265	257887	0	0
T4	69976	597	0	0
T5	41411	12453	0	0
T6	90346	14303	0	0
T8	109662	21210	0	0
T9	69747	66208	0	0
T16	515431	143124	0	0
T17	2237	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T4,T8,T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T54
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T8,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T9
1	1	Covered	T3,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T54
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T9

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412959766	412162265	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	412959766	105519279	0	0
GntImpliesValid_A	412959766	105519279	0	0
GrantKnown_A	412959766	412162265	0	0
IdxKnown_A	412959766	412162265	0	0
IndexIsCorrect_A	412959766	105519279	0	0
NoReadyValidNoGrant_A	412959766	43251181	0	0
Priority_A	412959766	111551838	0	0
ReadyAndValidImplyGrant_A	412959766	105519279	0	0
ReqAndReadyImplyGrant_A	412959766	105519279	0	0
ReqImpliesValid_A	412959766	111551838	0	0
ValidKnown_A	412959766	412162265	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	105519279	0	0
T3	498265	237944	0	0
T4	69976	66463	0	0
T5	41411	17050	0	0
T6	90346	0	0	0
T7	0	13186	0	0
T8	109662	12475	0	0
T9	69747	1019	0	0
T16	515431	337298	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	14898	0	0
T33	2324	146	0	0
T54	0	164	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	105519279	0	0
T3	498265	237944	0	0
T4	69976	66463	0	0
T5	41411	17050	0	0
T6	90346	0	0	0
T7	0	13186	0	0
T8	109662	12475	0	0
T9	69747	1019	0	0
T16	515431	337298	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	14898	0	0
T33	2324	146	0	0
T54	0	164	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	105519279	0	0
T3	498265	237944	0	0
T4	69976	66463	0	0
T5	41411	17050	0	0
T6	90346	0	0	0
T7	0	13186	0	0
T8	109662	12475	0	0
T9	69747	1019	0	0
T16	515431	337298	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	14898	0	0
T33	2324	146	0	0
T54	0	164	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	43251181	0	0
T4	69976	272	0	0
T5	41411	188	0	0
T6	90346	0	0	0
T7	0	449978	0	0
T8	109662	36126	0	0
T9	69747	70	0	0
T13	1157	0	0	0
T16	515431	698	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	23478	0	0
T33	2324	219	0	0
T54	0	124	0	0
T60	0	524288	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	111551838	0	0
T3	498265	237944	0	0
T4	69976	66550	0	0
T5	41411	17050	0	0
T6	90346	0	0	0
T7	0	92664	0	0
T8	109662	13749	0	0
T9	69747	1019	0	0
T16	515431	337298	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	17299	0	0
T33	2324	146	0	0
T54	0	172	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	105519279	0	0
T3	498265	237944	0	0
T4	69976	66463	0	0
T5	41411	17050	0	0
T6	90346	0	0	0
T7	0	13186	0	0
T8	109662	12475	0	0
T9	69747	1019	0	0
T16	515431	337298	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	14898	0	0
T33	2324	146	0	0
T54	0	164	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	105519279	0	0
T3	498265	237944	0	0
T4	69976	66463	0	0
T5	41411	17050	0	0
T6	90346	0	0	0
T7	0	13186	0	0
T8	109662	12475	0	0
T9	69747	1019	0	0
T16	515431	337298	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	14898	0	0
T33	2324	146	0	0
T54	0	164	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	111551838	0	0
T3	498265	237944	0	0
T4	69976	66550	0	0
T5	41411	17050	0	0
T6	90346	0	0	0
T7	0	92664	0	0
T8	109662	13749	0	0
T9	69747	1019	0	0
T16	515431	337298	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	17299	0	0
T33	2324	146	0	0
T54	0	172	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T4,T8,T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T54
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T8,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T9
1	1	Covered	T3,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T54
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T9

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412959766	412162265	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	412959766	105519117	0	0
GntImpliesValid_A	412959766	105519117	0	0
GrantKnown_A	412959766	412162265	0	0
IdxKnown_A	412959766	412162265	0	0
IndexIsCorrect_A	412959766	105519117	0	0
NoReadyValidNoGrant_A	412959766	43251185	0	0
Priority_A	412959766	111551672	0	0
ReadyAndValidImplyGrant_A	412959766	105519117	0	0
ReqAndReadyImplyGrant_A	412959766	105519117	0	0
ReqImpliesValid_A	412959766	111551672	0	0
ValidKnown_A	412959766	412162265	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	105519117	0	0
T3	498265	237944	0	0
T4	69976	66463	0	0
T5	41411	17050	0	0
T6	90346	0	0	0
T7	0	13186	0	0
T8	109662	12475	0	0
T9	69747	1019	0	0
T16	515431	337298	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	14898	0	0
T33	2324	146	0	0
T54	0	83	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	105519117	0	0
T3	498265	237944	0	0
T4	69976	66463	0	0
T5	41411	17050	0	0
T6	90346	0	0	0
T7	0	13186	0	0
T8	109662	12475	0	0
T9	69747	1019	0	0
T16	515431	337298	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	14898	0	0
T33	2324	146	0	0
T54	0	83	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	105519117	0	0
T3	498265	237944	0	0
T4	69976	66463	0	0
T5	41411	17050	0	0
T6	90346	0	0	0
T7	0	13186	0	0
T8	109662	12475	0	0
T9	69747	1019	0	0
T16	515431	337298	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	14898	0	0
T33	2324	146	0	0
T54	0	83	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	43251185	0	0
T4	69976	272	0	0
T5	41411	188	0	0
T6	90346	0	0	0
T7	0	449978	0	0
T8	109662	36126	0	0
T9	69747	70	0	0
T13	1157	0	0	0
T16	515431	698	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	23478	0	0
T33	2324	219	0	0
T54	0	126	0	0
T60	0	524288	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	111551672	0	0
T3	498265	237944	0	0
T4	69976	66550	0	0
T5	41411	17050	0	0
T6	90346	0	0	0
T7	0	92664	0	0
T8	109662	13749	0	0
T9	69747	1019	0	0
T16	515431	337298	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	17299	0	0
T33	2324	146	0	0
T54	0	89	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	105519117	0	0
T3	498265	237944	0	0
T4	69976	66463	0	0
T5	41411	17050	0	0
T6	90346	0	0	0
T7	0	13186	0	0
T8	109662	12475	0	0
T9	69747	1019	0	0
T16	515431	337298	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	14898	0	0
T33	2324	146	0	0
T54	0	83	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	105519117	0	0
T3	498265	237944	0	0
T4	69976	66463	0	0
T5	41411	17050	0	0
T6	90346	0	0	0
T7	0	13186	0	0
T8	109662	12475	0	0
T9	69747	1019	0	0
T16	515431	337298	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	14898	0	0
T33	2324	146	0	0
T54	0	83	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	111551672	0	0
T3	498265	237944	0	0
T4	69976	66550	0	0
T5	41411	17050	0	0
T6	90346	0	0	0
T7	0	92664	0	0
T8	109662	13749	0	0
T9	69747	1019	0	0
T16	515431	337298	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	17299	0	0
T33	2324	146	0	0
T54	0	89	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0