Unified Coverage Report :: Module :: prim_arbiter_tree_dup

Module : prim_arbiter_tree_dup

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	95.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc	80.00	100.00	40.00			100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb	96.67	90.00	100.00			100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb	96.67	90.00	100.00			100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	100.00	40.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	94.51			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.55	100.00	89.66			100.00		u_scramble

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_input_bufs[0].gen_data_bufs[0].u_dat_buf	100.00	100.00
gen_input_bufs[0].gen_data_bufs[1].u_dat_buf	100.00	100.00
gen_input_bufs[0].gen_rr_arbiter.u_arb	97.86	100.00	97.67			100.00	93.75
gen_input_bufs[0].u_req_buf	100.00	100.00
gen_input_bufs[1].gen_data_bufs[0].u_dat_buf	100.00	100.00
gen_input_bufs[1].gen_data_bufs[1].u_dat_buf	100.00	100.00
gen_input_bufs[1].gen_rr_arbiter.u_arb	97.86	100.00	97.67			100.00	93.75
gen_input_bufs[1].u_req_buf	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	90.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.98	75.93	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.87	100.00	91.51		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_input_bufs[0].gen_data_bufs[0].u_dat_buf	0.00	0.00
gen_input_bufs[0].gen_data_bufs[1].u_dat_buf	0.00	0.00
gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
gen_input_bufs[0].u_req_buf	100.00	100.00
gen_input_bufs[1].gen_data_bufs[0].u_dat_buf	0.00	0.00
gen_input_bufs[1].gen_data_bufs[1].u_dat_buf	0.00	0.00
gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
gen_input_bufs[1].u_req_buf	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	90.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.98	75.93	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.55	100.00	84.91		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_input_bufs[0].gen_data_bufs[0].u_dat_buf	0.00	0.00
gen_input_bufs[0].gen_data_bufs[1].u_dat_buf	0.00	0.00
gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
gen_input_bufs[0].u_req_buf	100.00	100.00
gen_input_bufs[1].gen_data_bufs[0].u_dat_buf	0.00	0.00
gen_input_bufs[1].gen_data_bufs[1].u_dat_buf	0.00	0.00
gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
gen_input_bufs[1].u_req_buf	100.00	100.00

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.80	100.00	93.46			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.55	100.00	89.66			100.00		u_scramble

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_input_bufs[0].gen_data_bufs[0].u_dat_buf	100.00	100.00
gen_input_bufs[0].gen_data_bufs[1].u_dat_buf	100.00	100.00
gen_input_bufs[0].gen_rr_arbiter.u_arb	95.50	100.00	88.24			100.00	93.75
gen_input_bufs[0].u_req_buf	100.00	100.00
gen_input_bufs[1].gen_data_bufs[0].u_dat_buf	100.00	100.00
gen_input_bufs[1].gen_data_bufs[1].u_dat_buf	100.00	100.00
gen_input_bufs[1].gen_rr_arbiter.u_arb	97.95	100.00	98.04			100.00	93.75
gen_input_bufs[1].u_req_buf	100.00	100.00

Line Coverage for Module : prim_arbiter_tree_dup ( parameter N=2,DW=16,EnDataPort=1,FixedArb=0,IdxW=1,ArbInstances=2 + N=2,DW=129,EnDataPort=1,FixedArb=0,IdxW=1,ArbInstances=2 )
Line Coverage for Module self-instances :

SCORE	LINE
80.00	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc

SCORE	LINE
100.00	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op

	Line No.	Total	Covered	Percent
TOTAL		10	10	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	139	3	3	100.00
CONT_ASSIGN	146	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
123	1	1
124	1	1
125	1	1
126	1	1
132	1	1
137	1	1
139	1	1
140	1	1
142	1	1
146	1	1

---

Line Coverage for Module : prim_arbiter_tree_dup ( parameter N=2,DW=2,EnDataPort=0,FixedArb=1,IdxW=1,ArbInstances=2 )
Line Coverage for Module self-instances :

SCORE	LINE
96.67	90.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb

SCORE	LINE
96.67	90.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb

	Line No.	Total	Covered	Percent
TOTAL		10	9	90.00
CONT_ASSIGN	100	0	0
CONT_ASSIGN	100	0	0
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	0	0.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	139	3	3	100.00
CONT_ASSIGN	146	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100		unreachable
123	1	1
124	1	1
125	1	1
126	0	1
132	1	1
137	1	1
139	1	1
140	1	1
142	1	1
146	1	1

---

Cond Coverage for Module : prim_arbiter_tree_dup

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       132
 EXPRESSION (arb_output_buf[(ArbInstances - 1)] != arb_output_buf[0])
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T54,T49,T78

 LINE       142
 EXPRESSION (err_d | err_q)
             --1--   --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T54,T49,T78
1	0	Covered	T54,T49,T78

---

Branch Coverage for Module : prim_arbiter_tree_dup

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	139	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc

	Line No.	Total	Covered	Percent
TOTAL		10	10	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	139	3	3	100.00
CONT_ASSIGN	146	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
123	1	1
124	1	1
125	1	1
126	1	1
132	1	1
137	1	1
139	1	1
140	1	1
142	1	1
146	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc

	Total	Covered	Percent
Conditions	5	2	40.00
Logical	5	2	40.00
Non-Logical	0	0
Event	0	0

 LINE       132
 EXPRESSION (arb_output_buf[(ArbInstances - 1)] != arb_output_buf[0])
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       142
 EXPRESSION (err_d | err_q)
             --1--   --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	139	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb

	Line No.	Total	Covered	Percent
TOTAL		10	9	90.00
CONT_ASSIGN	100	0	0
CONT_ASSIGN	100	0	0
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	0	0.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	139	3	3	100.00
CONT_ASSIGN	146	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100		unreachable
123	1	1
124	1	1
125	1	1
126	0	1
132	1	1
137	1	1
139	1	1
140	1	1
142	1	1
146	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       132
 EXPRESSION (arb_output_buf[(ArbInstances - 1)] != arb_output_buf[0])
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T49

 LINE       142
 EXPRESSION (err_d | err_q)
             --1--   --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T49
1	0	Covered	T49

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	139	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb

	Line No.	Total	Covered	Percent
TOTAL		10	9	90.00
CONT_ASSIGN	100	0	0
CONT_ASSIGN	100	0	0
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	0	0.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	139	3	3	100.00
CONT_ASSIGN	146	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100		unreachable
123	1	1
124	1	1
125	1	1
126	0	1
132	1	1
137	1	1
139	1	1
140	1	1
142	1	1
146	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       132
 EXPRESSION (arb_output_buf[(ArbInstances - 1)] != arb_output_buf[0])
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T54,T78

 LINE       142
 EXPRESSION (err_d | err_q)
             --1--   --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T54,T78
1	0	Covered	T54,T78

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	139	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op

	Line No.	Total	Covered	Percent
TOTAL		10	10	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	139	3	3	100.00
CONT_ASSIGN	146	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
123	1	1
124	1	1
125	1	1
126	1	1
132	1	1
137	1	1
139	1	1
140	1	1
142	1	1
146	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       132
 EXPRESSION (arb_output_buf[(ArbInstances - 1)] != arb_output_buf[0])
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T76,T77

 LINE       142
 EXPRESSION (err_d | err_q)
             --1--   --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T76,T77
1	0	Covered	T76,T77

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	139	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3