Unified Coverage Report :: Module :: prim_arbiter_tree

Module : prim_arbiter_tree

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.49	96.15	97.80			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random	94.17	92.31	97.69			100.00	86.67
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random	94.17	92.31	97.69			100.00	86.67
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb	95.50	100.00	88.24			100.00	93.75
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb	97.86	100.00	97.67			100.00	93.75
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb	97.86	100.00	97.67			100.00	93.75
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb	97.95	100.00	98.04			100.00	93.75

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.17	92.31	97.69			100.00	86.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.17	92.31	97.69			100.00	86.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.74	100.00	90.97			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.17	92.31	97.69			100.00	86.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.17	92.31	97.69			100.00	86.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.52	100.00	90.09			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.50	100.00	88.24			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.50	100.00	88.24			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_prim_arbiter_tree_op

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86	100.00	97.67			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86	100.00	97.67			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00	40.00			100.00		u_prim_arbiter_tree_calc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86	100.00	97.67			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86	100.00	97.67			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00	40.00			100.00		u_prim_arbiter_tree_calc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.95	100.00	98.04			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.95	100.00	98.04			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_prim_arbiter_tree_op

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Line Coverage for Module self-instances :

SCORE	LINE
94.17	92.31

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORE	LINE
94.17	92.31

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
TOTAL		52	48	92.31
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	4	4
118	4	4
122	0	4
126	4	4
128	4	4
148	3	3
150	3	3
151	3	3
155	3	3
156	3	3
160	3	3
161	3	3
163	1	1(2 unreachable)
164	3	3
174	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Line Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Line Coverage for Module self-instances :

SCORE	LINE
97.86	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	LINE
97.86	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

SCORE	LINE
95.50	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	LINE
97.95	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126	2	2
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :

SCORE	COND
97.86	97.67

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	COND
97.86	97.67

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	43	42	97.67
Logical	43	42	97.67
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T54
1	1	Covered	T5,T8,T54

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T8,T34,T51
1	1	0	Covered	T1,T2,T3
1	1	1	Unreachable	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T8,T34,T51
1	1	0	Covered	T5,T8,T54
1	1	1	Unreachable	T5,T8,T54

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T54
1	0	Unreachable	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T54
0	1	Covered	T5,T8,T54
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T5,T8,T54
1	1	Covered	T5,T8,T54

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T34,T51
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T8,T34,T51
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T8,T54

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T54
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T54

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :

SCORE	COND
95.50	88.24

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	COND
97.95	98.04

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	51	50	98.04
Logical	51	50	98.04
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T77
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T24
1	1	Covered	T5,T8,T24

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T76,T77
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T77
1	0	1	Covered	T76,T77
1	1	0	Covered	T5,T8,T24
1	1	1	Covered	T5,T8,T24

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T24
0	1	Covered	T5,T8,T24
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T24
1	1	Covered	T5,T8,T24

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T76,T77
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T76,T77
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T8,T24

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T24
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T24

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Cond Coverage for Module self-instances :

SCORE	COND
94.17	97.69

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORE	COND
94.17	97.69

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Total	Covered	Percent
Conditions	130	127	97.69
Logical	130	127	97.69
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T16,T23
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T16,T23
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T16
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T9,T34
1	1	Covered	T4,T5,T8

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T8
1	1	0	Covered	T4,T5,T8
1	1	1	Covered	T4,T5,T8

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T8
1	1	0	Covered	T4,T5,T8
1	1	1	Covered	T4,T5,T8

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T8
1	1	0	Covered	T4,T5,T8
1	1	1	Covered	T4,T5,T8

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T8
1	1	0	Covered	T4,T5,T8
1	1	1	Covered	T4,T5,T8

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T8

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T8

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T8

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T24,T34
1	0	Covered	T8,T24,T34

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T24,T34
1	0	Covered	T4,T5,T8

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T24,T7
1	0	Covered	T4,T5,T8

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T8

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T8

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T8
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T23
1	0	Covered	T4,T5,T8
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

---

Branch Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
94.17	100.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORE	BRANCH
94.17	100.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
97.86	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	BRANCH
97.86	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

SCORE	BRANCH
95.50	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	BRANCH
97.95	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_tree

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	6372	6372	0	0
GntImpliesReady_A	2147483647	70913228	0	0
GntImpliesValid_A	2147483647	70913228	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	70913228	0	0
LockArbDecision_A	2147483647	65190844	0	0
NoReadyValidNoGrant_A	2147483647	2129465356	0	0
ReadyAndValidImplyGrant_A	2147483647	70913228	0	0
ReqAndReadyImplyGrant_A	2147483647	70913228	0	0
ReqImpliesValid_A	2147483647	333456117	0	0
ReqStaysHighUntilGranted0_M	2147483647	65190656	0	0
RoundRobin_A	2147483647	56655	0	6336
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	1651839064	65190921	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	23154	19506	0	0
T2	7134	5532	0	0
T3	2989590	2989536	0	0
T4	419856	419256	0	0
T5	248466	248088	0	0
T6	542076	541578	0	0
T8	657972	656886	0	0
T9	418482	418056	0	0
T16	3092586	3092004	0	0
T17	13422	12846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6372	6372	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T6	6	6	0	0
T8	6	6	0	0
T9	6	6	0	0
T16	6	6	0	0
T17	6	6	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70913228	0	0
T1	15436	464	0	0
T2	4756	268	0	0
T3	1993060	128	0	0
T4	419856	361	0	0
T5	248466	3132	0	0
T6	542076	1152	0	0
T7	0	23480	0	0
T8	657972	126543	0	0
T9	418482	199	0	0
T13	2314	0	0	0
T16	3092586	662	0	0
T17	13422	128	0	0
T23	8334	136	0	0
T24	0	25116	0	0
T33	4648	69	0	0
T54	0	141	0	0
T55	0	392	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70913228	0	0
T1	15436	464	0	0
T2	4756	268	0	0
T3	1993060	128	0	0
T4	419856	361	0	0
T5	248466	3132	0	0
T6	542076	1152	0	0
T7	0	23480	0	0
T8	657972	126543	0	0
T9	418482	199	0	0
T13	2314	0	0	0
T16	3092586	662	0	0
T17	13422	128	0	0
T23	8334	136	0	0
T24	0	25116	0	0
T33	4648	69	0	0
T54	0	141	0	0
T55	0	392	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	23154	19506	0	0
T2	7134	5532	0	0
T3	2989590	2989536	0	0
T4	419856	419256	0	0
T5	248466	248088	0	0
T6	542076	541578	0	0
T8	657972	656886	0	0
T9	418482	418056	0	0
T16	3092586	3092004	0	0
T17	13422	12846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	23154	19506	0	0
T2	7134	5532	0	0
T3	2989590	2989536	0	0
T4	419856	419256	0	0
T5	248466	248088	0	0
T6	542076	541578	0	0
T8	657972	656886	0	0
T9	418482	418056	0	0
T16	3092586	3092004	0	0
T17	13422	12846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70913228	0	0
T1	15436	464	0	0
T2	4756	268	0	0
T3	1993060	128	0	0
T4	419856	361	0	0
T5	248466	3132	0	0
T6	542076	1152	0	0
T7	0	23480	0	0
T8	657972	126543	0	0
T9	418482	199	0	0
T13	2314	0	0	0
T16	3092586	662	0	0
T17	13422	128	0	0
T23	8334	136	0	0
T24	0	25116	0	0
T33	4648	69	0	0
T54	0	141	0	0
T55	0	392	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	65190844	0	0
T1	15436	464	0	0
T2	4756	268	0	0
T3	1993060	128	0	0
T4	279904	128	0	0
T5	165644	2944	0	0
T6	361384	1152	0	0
T8	438648	101274	0	0
T9	278988	128	0	0
T16	2061724	128	0	0
T17	8948	128	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2129465356	0	0
T1	23154	18462	0	0
T2	7134	4929	0	0
T3	2989590	2989505	0	0
T4	419856	345648	0	0
T5	248466	174887	0	0
T6	542076	539242	0	0
T8	657972	236352	0	0
T9	418482	344942	0	0
T16	3092586	2598845	0	0
T17	13422	12558	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70913228	0	0
T1	15436	464	0	0
T2	4756	268	0	0
T3	1993060	128	0	0
T4	419856	361	0	0
T5	248466	3132	0	0
T6	542076	1152	0	0
T7	0	23480	0	0
T8	657972	126543	0	0
T9	418482	199	0	0
T13	2314	0	0	0
T16	3092586	662	0	0
T17	13422	128	0	0
T23	8334	136	0	0
T24	0	25116	0	0
T33	4648	69	0	0
T54	0	141	0	0
T55	0	392	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70913228	0	0
T1	15436	464	0	0
T2	4756	268	0	0
T3	1993060	128	0	0
T4	419856	361	0	0
T5	248466	3132	0	0
T6	542076	1152	0	0
T7	0	23480	0	0
T8	657972	126543	0	0
T9	418482	199	0	0
T13	2314	0	0	0
T16	3092586	662	0	0
T17	13422	128	0	0
T23	8334	136	0	0
T24	0	25116	0	0
T33	4648	69	0	0
T54	0	141	0	0
T55	0	392	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	333456117	0	0
T1	15436	928	0	0
T2	4756	536	0	0
T3	1993060	256	0	0
T4	419856	73563	0	0
T5	248466	73161	0	0
T6	542076	2304	0	0
T7	0	1698808	0	0
T8	657972	420484	0	0
T9	418482	73074	0	0
T13	2314	0	0	0
T16	3092586	493099	0	0
T17	13422	256	0	0
T23	8334	3244	0	0
T24	0	214829	0	0
T33	4648	1803	0	0
T54	0	24393	0	0
T55	0	383730	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	65190656	0	0
T1	15436	464	0	0
T2	4756	268	0	0
T3	1993060	128	0	0
T4	279904	128	0	0
T5	165644	2944	0	0
T6	361384	1152	0	0
T8	438648	101274	0	0
T9	278988	128	0	0
T16	2061724	128	0	0
T17	8948	128	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	56655	0	6336
T4	139952	106	0	2
T5	82822	0	0	2
T6	180692	0	0	2
T8	219324	0	0	2
T9	139494	11	0	2
T13	2314	0	0	2
T16	1030862	0	0	2
T17	4474	0	0	2
T23	8334	0	0	2
T33	4648	0	0	2
T50	0	1246	0	0
T51	0	1230	0	0
T57	0	1064	0	0
T61	0	1212	0	0
T100	0	573	0	0
T101	0	1077	0	0
T103	0	601	0	0
T215	0	1446	0	0
T226	0	242	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	23154	19506	0	0
T2	7134	5532	0	0
T3	2989590	2989536	0	0
T4	419856	419256	0	0
T5	248466	248088	0	0
T6	542076	541578	0	0
T8	657972	656886	0	0
T9	418482	418056	0	0
T16	3092586	3092004	0	0
T17	13422	12846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651839064	65190921	0	0
T1	15436	464	0	0
T2	4756	268	0	0
T3	1993060	128	0	0
T4	279904	128	0	0
T5	165644	2944	0	0
T6	361384	1152	0	0
T8	438648	101274	0	0
T9	278988	128	0	0
T16	2061724	128	0	0
T17	8948	128	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
TOTAL		52	48	92.31
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	4	4
118	4	4
122	0	4
126	4	4
128	4	4
148	3	3
150	3	3
151	3	3
155	3	3
156	3	3
160	3	3
161	3	3
163	1	1(2 unreachable)
164	3	3
174	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Total	Covered	Percent
Conditions	130	127	97.69
Logical	130	127	97.69
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T23,T54
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T23,T54
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T16
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T9,T34
1	1	Covered	T4,T5,T8

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T8
1	1	0	Covered	T4,T5,T8
1	1	1	Covered	T4,T5,T8

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T8
1	1	0	Covered	T4,T5,T8
1	1	1	Covered	T4,T5,T8

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T8
1	1	0	Covered	T4,T5,T8
1	1	1	Covered	T4,T5,T8

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T8
1	1	0	Covered	T4,T5,T8
1	1	1	Covered	T4,T5,T8

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T8

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T8

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T8

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T24,T34
1	0	Covered	T8,T24,T34

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T24,T34
1	0	Covered	T4,T5,T8

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T24,T7
1	0	Covered	T4,T5,T8

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T8

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T8

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T8
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T23
1	0	Covered	T4,T5,T8
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	13	86.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	13	86.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412959766	412162265	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	412959766	3017517	0	0
GntImpliesValid_A	412959766	3017517	0	0
GrantKnown_A	412959766	412162265	0	0
IdxKnown_A	412959766	412162265	0	0
IndexIsCorrect_A	412959766	3017517	0	0
LockArbDecision_A	412959766	0	0	0
NoReadyValidNoGrant_A	412959766	298235203	0	0
ReadyAndValidImplyGrant_A	412959766	3017517	0	0
ReqAndReadyImplyGrant_A	412959766	3017517	0	0
ReqImpliesValid_A	412959766	108530037	0	0
ReqStaysHighUntilGranted0_M	412959766	0	0	0
RoundRobin_A	412959766	30187	0	1056
ValidKnown_A	412959766	412162265	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	3017517	0	0
T4	69976	112	0	0
T5	41411	154	0	0
T6	90346	0	0	0
T7	0	13104	0	0
T8	109662	14920	0	0
T9	69747	50	0	0
T13	1157	0	0	0
T16	515431	309	0	0
T17	2237	0	0	0
T23	4167	136	0	0
T24	0	13451	0	0
T33	2324	0	0	0
T54	0	75	0	0
T55	0	161	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	3017517	0	0
T4	69976	112	0	0
T5	41411	154	0	0
T6	90346	0	0	0
T7	0	13104	0	0
T8	109662	14920	0	0
T9	69747	50	0	0
T13	1157	0	0	0
T16	515431	309	0	0
T17	2237	0	0	0
T23	4167	136	0	0
T24	0	13451	0	0
T33	2324	0	0	0
T54	0	75	0	0
T55	0	161	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	3017517	0	0
T4	69976	112	0	0
T5	41411	154	0	0
T6	90346	0	0	0
T7	0	13104	0	0
T8	109662	14920	0	0
T9	69747	50	0	0
T13	1157	0	0	0
T16	515431	309	0	0
T17	2237	0	0	0
T23	4167	136	0	0
T24	0	13451	0	0
T33	2324	0	0	0
T54	0	75	0	0
T55	0	161	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	298235203	0	0
T1	3859	3135	0	0
T2	1189	855	0	0
T3	498265	498253	0	0
T4	69976	410	0	0
T5	41411	379	0	0
T6	90346	90231	0	0
T8	109662	464	0	0
T9	69747	66050	0	0
T16	515431	135975	0	0
T17	2237	2109	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	3017517	0	0
T4	69976	112	0	0
T5	41411	154	0	0
T6	90346	0	0	0
T7	0	13104	0	0
T8	109662	14920	0	0
T9	69747	50	0	0
T13	1157	0	0	0
T16	515431	309	0	0
T17	2237	0	0	0
T23	4167	136	0	0
T24	0	13451	0	0
T33	2324	0	0	0
T54	0	75	0	0
T55	0	161	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	3017517	0	0
T4	69976	112	0	0
T5	41411	154	0	0
T6	90346	0	0	0
T7	0	13104	0	0
T8	109662	14920	0	0
T9	69747	50	0	0
T13	1157	0	0	0
T16	515431	309	0	0
T17	2237	0	0	0
T23	4167	136	0	0
T24	0	13451	0	0
T33	2324	0	0	0
T54	0	75	0	0
T55	0	161	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	108530037	0	0
T4	69976	69429	0	0
T5	41411	40933	0	0
T6	90346	0	0	0
T7	0	849560	0	0
T8	109662	108971	0	0
T9	69747	3590	0	0
T13	1157	0	0	0
T16	515431	379319	0	0
T17	2237	0	0	0
T23	4167	3244	0	0
T24	0	107409	0	0
T33	2324	0	0	0
T54	0	12237	0	0
T55	0	224887	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	30187	0	1056
T4	69976	40	0	1
T5	41411	0	0	1
T6	90346	0	0	1
T8	109662	0	0	1
T9	69747	11	0	1
T13	1157	0	0	1
T16	515431	0	0	1
T17	2237	0	0	1
T23	4167	0	0	1
T33	2324	0	0	1
T50	0	361	0	0
T51	0	31	0	0
T57	0	688	0	0
T61	0	868	0	0
T100	0	544	0	0
T101	0	916	0	0
T103	0	250	0	0
T215	0	380	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
TOTAL		52	48	92.31
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	4	4
118	4	4
122	0	4
126	4	4
128	4	4
148	3	3
150	3	3
151	3	3
155	3	3
156	3	3
160	3	3
161	3	3
163	1	1(2 unreachable)
164	3	3
174	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Total	Covered	Percent
Conditions	130	127	97.69
Logical	130	127	97.69
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T16,T54
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T16,T54
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T16,T54
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T34,T57
1	1	Covered	T4,T5,T8

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T8
1	1	0	Covered	T4,T5,T8
1	1	1	Covered	T4,T5,T8

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T8
1	1	0	Covered	T4,T5,T8
1	1	1	Covered	T4,T5,T8

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T8
1	1	0	Covered	T4,T5,T8
1	1	1	Covered	T4,T5,T8

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T4,T5,T8
1	1	0	Covered	T4,T5,T8
1	1	1	Covered	T4,T5,T8

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T8

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T8

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T8

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T24,T34
1	0	Covered	T8,T24,T34

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T24,T34
1	0	Covered	T4,T5,T8

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T24,T7
1	0	Covered	T4,T5,T8

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T8

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T8

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T8
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T24,T7
1	0	Covered	T4,T5,T8
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	13	86.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	13	86.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412959766	412162265	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	412959766	2704790	0	0
GntImpliesValid_A	412959766	2704790	0	0
GrantKnown_A	412959766	412162265	0	0
IdxKnown_A	412959766	412162265	0	0
IndexIsCorrect_A	412959766	2704790	0	0
LockArbDecision_A	412959766	0	0	0
NoReadyValidNoGrant_A	412959766	312963049	0	0
ReadyAndValidImplyGrant_A	412959766	2704790	0	0
ReqAndReadyImplyGrant_A	412959766	2704790	0	0
ReqImpliesValid_A	412959766	94544201	0	0
ReqStaysHighUntilGranted0_M	412959766	0	0	0
RoundRobin_A	412959766	26468	0	1056
ValidKnown_A	412959766	412162265	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	2704790	0	0
T4	69976	121	0	0
T5	41411	34	0	0
T6	90346	0	0	0
T7	0	10376	0	0
T8	109662	10349	0	0
T9	69747	21	0	0
T13	1157	0	0	0
T16	515431	225	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	11665	0	0
T33	2324	69	0	0
T54	0	66	0	0
T55	0	231	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	2704790	0	0
T4	69976	121	0	0
T5	41411	34	0	0
T6	90346	0	0	0
T7	0	10376	0	0
T8	109662	10349	0	0
T9	69747	21	0	0
T13	1157	0	0	0
T16	515431	225	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	11665	0	0
T33	2324	69	0	0
T54	0	66	0	0
T55	0	231	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	2704790	0	0
T4	69976	121	0	0
T5	41411	34	0	0
T6	90346	0	0	0
T7	0	10376	0	0
T8	109662	10349	0	0
T9	69747	21	0	0
T13	1157	0	0	0
T16	515431	225	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	11665	0	0
T33	2324	69	0	0
T54	0	66	0	0
T55	0	231	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	312963049	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	65990	0	0
T5	41411	15004	0	0
T6	90346	90263	0	0
T8	109662	514	0	0
T9	69747	444	0	0
T16	515431	401790	0	0
T17	2237	2141	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	2704790	0	0
T4	69976	121	0	0
T5	41411	34	0	0
T6	90346	0	0	0
T7	0	10376	0	0
T8	109662	10349	0	0
T9	69747	21	0	0
T13	1157	0	0	0
T16	515431	225	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	11665	0	0
T33	2324	69	0	0
T54	0	66	0	0
T55	0	231	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	2704790	0	0
T4	69976	121	0	0
T5	41411	34	0	0
T6	90346	0	0	0
T7	0	10376	0	0
T8	109662	10349	0	0
T9	69747	21	0	0
T13	1157	0	0	0
T16	515431	225	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	11665	0	0
T33	2324	69	0	0
T54	0	66	0	0
T55	0	231	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	94544201	0	0
T4	69976	3878	0	0
T5	41411	26340	0	0
T6	90346	0	0	0
T7	0	849248	0	0
T8	109662	108963	0	0
T9	69747	69228	0	0
T13	1157	0	0	0
T16	515431	113524	0	0
T17	2237	0	0	0
T23	4167	0	0	0
T24	0	107420	0	0
T33	2324	1803	0	0
T54	0	12156	0	0
T55	0	158843	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	26468	0	1056
T4	69976	66	0	1
T5	41411	0	0	1
T6	90346	0	0	1
T8	109662	0	0	1
T9	69747	0	0	1
T13	1157	0	0	1
T16	515431	0	0	1
T17	2237	0	0	1
T23	4167	0	0	1
T33	2324	0	0	1
T50	0	885	0	0
T51	0	1199	0	0
T57	0	376	0	0
T61	0	344	0	0
T100	0	29	0	0
T101	0	161	0	0
T103	0	351	0	0
T215	0	1066	0	0
T226	0	242	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126	2	2
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	51	45	88.24
Logical	51	45	88.24
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T24
1	1	Covered	T5,T8,T24

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T77
1	0	1	Not Covered
1	1	0	Covered	T5,T8,T24
1	1	1	Covered	T5,T8,T24

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T24
0	1	Covered	T5,T8,T24
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T24
1	1	Covered	T5,T8,T24

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T8,T24

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T24
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T24

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412959766	412162265	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	412959766	15949397	0	0
GntImpliesValid_A	412959766	15949397	0	0
GrantKnown_A	412959766	412162265	0	0
IdxKnown_A	412959766	412162265	0	0
IndexIsCorrect_A	412959766	15949397	0	0
LockArbDecision_A	412959609	15949397	0	0
NoReadyValidNoGrant_A	412959766	380263385	0	0
ReadyAndValidImplyGrant_A	412959766	15949397	0	0
ReqAndReadyImplyGrant_A	412959766	15949397	0	0
ReqImpliesValid_A	412959766	31898804	0	0
ReqStaysHighUntilGranted0_M	412854639	15949303	0	0
RoundRobin_A	412959766	0	0	1056
ValidKnown_A	412959766	412162265	0	0
gen_data_port_assertion.DataFlow_A	412959766	15949397	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	15949397	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25318	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	15949397	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25318	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	15949397	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25318	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959609	15949397	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25318	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	380263385	0	0
T1	3859	3019	0	0
T2	1189	788	0	0
T3	498265	498249	0	0
T4	69976	69812	0	0
T5	41411	39876	0	0
T6	90346	89687	0	0
T8	109662	58844	0	0
T9	69747	69612	0	0
T16	515431	515270	0	0
T17	2237	2077	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	15949397	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25318	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	15949397	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25318	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	31898804	0	0
T1	3859	232	0	0
T2	1189	134	0	0
T3	498265	64	0	0
T4	69976	64	0	0
T5	41411	1472	0	0
T6	90346	576	0	0
T8	109662	50637	0	0
T9	69747	64	0	0
T16	515431	64	0	0
T17	2237	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412854639	15949303	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25318	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	0	0	1056

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	15949397	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25318	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126		unreachable
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	43	42	97.67
Logical	43	42	97.67
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T54
1	1	Covered	T5,T8,T54

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T8,T34,T51
1	1	0	Covered	T1,T2,T3
1	1	1	Unreachable	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T8,T34,T51
1	1	0	Covered	T5,T8,T54
1	1	1	Unreachable	T5,T8,T54

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T54
1	0	Unreachable	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T54
0	1	Covered	T5,T8,T54
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T5,T8,T54
1	1	Covered	T5,T8,T54

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T34,T51
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T8,T34,T51
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T8,T54

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T54
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T54

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412959766	412162265	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	412959766	16646026	0	0
GntImpliesValid_A	412959766	16646026	0	0
GrantKnown_A	412959766	412162265	0	0
IdxKnown_A	412959766	412162265	0	0
IndexIsCorrect_A	412959766	16646026	0	0
LockArbDecision_A	412959767	16646025	0	0
NoReadyValidNoGrant_A	412959766	378870205	0	0
ReadyAndValidImplyGrant_A	412959766	16646026	0	0
ReqAndReadyImplyGrant_A	412959766	16646026	0	0
ReqImpliesValid_A	412959766	33292060	0	0
ReqStaysHighUntilGranted0_M	412959767	16646025	0	0
RoundRobin_A	412959766	0	0	1056
ValidKnown_A	412959766	412162265	0	0
gen_data_port_assertion.DataFlow_A	412959766	16646026	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	16646026	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25319	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	16646026	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25319	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	16646026	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25319	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959767	16646025	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25319	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	378870205	0	0
T1	3859	3019	0	0
T2	1189	788	0	0
T3	498265	498249	0	0
T4	69976	69812	0	0
T5	41411	39876	0	0
T6	90346	89687	0	0
T8	109662	58843	0	0
T9	69747	69612	0	0
T16	515431	515270	0	0
T17	2237	2077	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	16646026	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25319	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	16646026	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25319	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	33292060	0	0
T1	3859	232	0	0
T2	1189	134	0	0
T3	498265	64	0	0
T4	69976	64	0	0
T5	41411	1472	0	0
T6	90346	576	0	0
T8	109662	50638	0	0
T9	69747	64	0	0
T16	515431	64	0	0
T17	2237	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959767	16646025	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25319	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	0	0	1056

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	16646026	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25319	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126		unreachable
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	43	42	97.67
Logical	43	42	97.67
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T54
1	1	Covered	T5,T8,T54

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T8,T34,T51
1	1	0	Covered	T1,T2,T3
1	1	1	Unreachable	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T8,T34,T51
1	1	0	Covered	T5,T8,T54
1	1	1	Unreachable	T5,T8,T54

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T54
1	0	Unreachable	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T54
0	1	Covered	T5,T8,T54
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T5,T8,T54
1	1	Covered	T5,T8,T54

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T34,T51
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T8,T34,T51
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T8,T54

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T54
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T54

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412959766	412162265	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	412959766	16646026	0	0
GntImpliesValid_A	412959766	16646026	0	0
GrantKnown_A	412959766	412162265	0	0
IdxKnown_A	412959766	412162265	0	0
IndexIsCorrect_A	412959766	16646026	0	0
LockArbDecision_A	412959767	16646025	0	0
NoReadyValidNoGrant_A	412959766	378870205	0	0
ReadyAndValidImplyGrant_A	412959766	16646026	0	0
ReqAndReadyImplyGrant_A	412959766	16646026	0	0
ReqImpliesValid_A	412959766	33292060	0	0
ReqStaysHighUntilGranted0_M	412959767	16646025	0	0
RoundRobin_A	412959766	0	0	1056
ValidKnown_A	412959766	412162265	0	0
gen_data_port_assertion.DataFlow_A	412959766	16646026	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	16646026	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25319	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	16646026	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25319	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	16646026	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25319	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959767	16646025	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25319	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	378870205	0	0
T1	3859	3019	0	0
T2	1189	788	0	0
T3	498265	498249	0	0
T4	69976	69812	0	0
T5	41411	39876	0	0
T6	90346	89687	0	0
T8	109662	58843	0	0
T9	69747	69612	0	0
T16	515431	515270	0	0
T17	2237	2077	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	16646026	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25319	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	16646026	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25319	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	33292060	0	0
T1	3859	232	0	0
T2	1189	134	0	0
T3	498265	64	0	0
T4	69976	64	0	0
T5	41411	1472	0	0
T6	90346	576	0	0
T8	109662	50638	0	0
T9	69747	64	0	0
T16	515431	64	0	0
T17	2237	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959767	16646025	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25319	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	0	0	1056

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	16646026	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25319	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126	2	2
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	51	50	98.04
Logical	51	50	98.04
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T77
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T24
1	1	Covered	T5,T8,T24

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T76,T77
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T77
1	0	1	Covered	T76,T77
1	1	0	Covered	T5,T8,T24
1	1	1	Covered	T5,T8,T24

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T24
0	1	Covered	T5,T8,T24
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T24
1	1	Covered	T5,T8,T24

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T76,T77
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T76,T77
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T8,T24

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T24
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T24

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412959766	412162265	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	412959766	15949472	0	0
GntImpliesValid_A	412959766	15949472	0	0
GrantKnown_A	412959766	412162265	0	0
IdxKnown_A	412959766	412162265	0	0
IndexIsCorrect_A	412959766	15949472	0	0
LockArbDecision_A	412959609	15949397	0	0
NoReadyValidNoGrant_A	412959766	380263309	0	0
ReadyAndValidImplyGrant_A	412959766	15949472	0	0
ReqAndReadyImplyGrant_A	412959766	15949472	0	0
ReqImpliesValid_A	412959766	31898955	0	0
ReqStaysHighUntilGranted0_M	412854639	15949303	0	0
RoundRobin_A	412959766	0	0	1056
ValidKnown_A	412959766	412162265	0	0
gen_data_port_assertion.DataFlow_A	412959766	15949472	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	15949472	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25318	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	15949472	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25318	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	15949472	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25318	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959609	15949397	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25318	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	380263309	0	0
T1	3859	3019	0	0
T2	1189	788	0	0
T3	498265	498249	0	0
T4	69976	69812	0	0
T5	41411	39876	0	0
T6	90346	89687	0	0
T8	109662	58844	0	0
T9	69747	69612	0	0
T16	515431	515270	0	0
T17	2237	2077	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	15949472	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25318	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	15949472	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25318	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	31898955	0	0
T1	3859	232	0	0
T2	1189	134	0	0
T3	498265	64	0	0
T4	69976	64	0	0
T5	41411	1472	0	0
T6	90346	576	0	0
T8	109662	50637	0	0
T9	69747	64	0	0
T16	515431	64	0	0
T17	2237	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412854639	15949303	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25318	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	0	0	1056

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	412162265	0	0
T1	3859	3251	0	0
T2	1189	922	0	0
T3	498265	498256	0	0
T4	69976	69876	0	0
T5	41411	41348	0	0
T6	90346	90263	0	0
T8	109662	109481	0	0
T9	69747	69676	0	0
T16	515431	515334	0	0
T17	2237	2141	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412959766	15949472	0	0
T1	3859	116	0	0
T2	1189	67	0	0
T3	498265	32	0	0
T4	69976	32	0	0
T5	41411	736	0	0
T6	90346	288	0	0
T8	109662	25318	0	0
T9	69747	32	0	0
T16	515431	32	0	0
T17	2237	32	0	0