Unified Coverage Report :: Module :: flash_phy_rd_buffers

Module : flash_phy_rd_buffers

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.31			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.31			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.31			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.31			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.47	100.00	89.87			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.47	100.00	89.87			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.47	100.00	89.87			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.47	100.00	89.87			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_phy_rd_buffers

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Module : flash_phy_rd_buffers

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T75,T76,T39

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T37,T40,T19

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Module : flash_phy_rd_buffers

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T75,T76,T39
0	0	1	-	-	Covered	T37,T40,T19
0	0	0	1	-	Covered	T2,T3,T4
0	0	0	0	1	Covered	T2,T3,T4
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd_buffers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	2147483647	5745974	0	0
UpdateCheck_A	2147483647	5745961	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5745974	0	0
T2	2288776	44869	0	0
T3	6232024	22723	0	0
T4	2101120	43965	0	0
T5	7928	0	0	0
T9	28896	0	0	0
T14	6578440	23454	0	0
T15	32104	104	0	0
T16	368016	19756	0	0
T17	878512	17361	0	0
T19	0	52	0	0
T31	0	73	0	0
T37	0	44838	0	0
T38	0	17221	0	0
T40	0	1744	0	0
T53	25704	0	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5745961	0	0
T2	2288776	44869	0	0
T3	6232024	22723	0	0
T4	2101120	43965	0	0
T5	7928	0	0	0
T9	28896	0	0	0
T14	6578440	23454	0	0
T15	32104	104	0	0
T16	368016	19756	0	0
T17	878512	17361	0	0
T19	0	52	0	0
T31	0	73	0	0
T37	0	44838	0	0
T38	0	17221	0	0
T40	0	1744	0	0
T53	25704	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T75,T76,T39

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T40,T30,T66

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T75,T76,T39
0	0	1	-	-	Covered	T40,T30,T66
0	0	0	1	-	Covered	T2,T3,T4
0	0	0	0	1	Covered	T2,T3,T4
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	425076783	726564	0	0
UpdateCheck_A	425076783	726563	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	726564	0	0
T2	286097	5498	0	0
T3	779003	2504	0	0
T4	262640	5782	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	3172	0	0
T15	4013	0	0	0
T16	46002	2247	0	0
T17	109814	2229	0	0
T31	0	19	0	0
T37	0	5612	0	0
T38	0	2169	0	0
T40	0	436	0	0
T53	3213	0	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	726563	0	0
T2	286097	5498	0	0
T3	779003	2504	0	0
T4	262640	5782	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	3172	0	0
T15	4013	0	0	0
T16	46002	2247	0	0
T17	109814	2229	0	0
T31	0	19	0	0
T37	0	5612	0	0
T38	0	2169	0	0
T40	0	436	0	0
T53	3213	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T75,T76,T39

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T40,T30,T34

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T75,T76,T39
0	0	1	-	-	Covered	T40,T30,T34
0	0	0	1	-	Covered	T2,T3,T4
0	0	0	0	1	Covered	T2,T3,T4
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	425076783	726217	0	0
UpdateCheck_A	425076783	726215	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	726217	0	0
T2	286097	5441	0	0
T3	779003	2506	0	0
T4	262640	5788	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	3158	0	0
T15	4013	0	0	0
T16	46002	2250	0	0
T17	109814	2224	0	0
T31	0	18	0	0
T37	0	5616	0	0
T38	0	2173	0	0
T40	0	436	0	0
T53	3213	0	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	726215	0	0
T2	286097	5441	0	0
T3	779003	2506	0	0
T4	262640	5788	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	3158	0	0
T15	4013	0	0	0
T16	46002	2250	0	0
T17	109814	2224	0	0
T31	0	18	0	0
T37	0	5616	0	0
T38	0	2173	0	0
T40	0	436	0	0
T53	3213	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T75,T76,T39

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T40,T30,T33

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T75,T76,T39
0	0	1	-	-	Covered	T40,T30,T33
0	0	0	1	-	Covered	T2,T3,T4
0	0	0	0	1	Covered	T2,T3,T4
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	425076783	726140	0	0
UpdateCheck_A	425076783	726138	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	726140	0	0
T2	286097	5483	0	0
T3	779003	2502	0	0
T4	262640	5791	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	3161	0	0
T15	4013	0	0	0
T16	46002	2248	0	0
T17	109814	2225	0	0
T31	0	18	0	0
T37	0	5603	0	0
T38	0	2175	0	0
T40	0	436	0	0
T53	3213	0	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	726138	0	0
T2	286097	5483	0	0
T3	779003	2502	0	0
T4	262640	5791	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	3161	0	0
T15	4013	0	0	0
T16	46002	2248	0	0
T17	109814	2225	0	0
T31	0	18	0	0
T37	0	5603	0	0
T38	0	2175	0	0
T40	0	436	0	0
T53	3213	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T76,T39,T77

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T40,T30,T66

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T76,T39,T77
0	0	1	-	-	Covered	T40,T30,T66
0	0	0	1	-	Covered	T2,T3,T4
0	0	0	0	1	Covered	T2,T3,T4
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	425076783	725575	0	0
UpdateCheck_A	425076783	725574	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	725575	0	0
T2	286097	5528	0	0
T3	779003	2502	0	0
T4	262640	5779	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	3164	0	0
T15	4013	0	0	0
T16	46002	2245	0	0
T17	109814	2232	0	0
T31	0	18	0	0
T37	0	5607	0	0
T38	0	2174	0	0
T40	0	436	0	0
T53	3213	0	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	725574	0	0
T2	286097	5528	0	0
T3	779003	2502	0	0
T4	262640	5779	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	3164	0	0
T15	4013	0	0	0
T16	46002	2245	0	0
T17	109814	2232	0	0
T31	0	18	0	0
T37	0	5607	0	0
T38	0	2174	0	0
T40	0	436	0	0
T53	3213	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T76,T77,T78

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T37,T19,T30

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T76,T77,T78
0	0	1	-	-	Covered	T37,T19,T30
0	0	0	1	-	Covered	T2,T3,T4
0	0	0	0	1	Covered	T2,T3,T4
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	425076783	710758	0	0
UpdateCheck_A	425076783	710757	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	710758	0	0
T2	286097	5757	0	0
T3	779003	3169	0	0
T4	262640	5207	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	2704	0	0
T15	4013	25	0	0
T16	46002	2692	0	0
T17	109814	2112	0	0
T19	0	14	0	0
T37	0	5597	0	0
T38	0	2137	0	0
T53	3213	0	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	710757	0	0
T2	286097	5757	0	0
T3	779003	3169	0	0
T4	262640	5207	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	2704	0	0
T15	4013	25	0	0
T16	46002	2692	0	0
T17	109814	2112	0	0
T19	0	14	0	0
T37	0	5597	0	0
T38	0	2137	0	0
T53	3213	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T76,T77,T79

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T37,T19,T30

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T76,T77,T79
0	0	1	-	-	Covered	T37,T19,T30
0	0	0	1	-	Covered	T2,T3,T4
0	0	0	0	1	Covered	T2,T3,T4
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	425076783	710481	0	0
UpdateCheck_A	425076783	710480	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	710481	0	0
T2	286097	5740	0	0
T3	779003	3180	0	0
T4	262640	5206	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	2687	0	0
T15	4013	28	0	0
T16	46002	2697	0	0
T17	109814	2111	0	0
T19	0	14	0	0
T37	0	5605	0	0
T38	0	2127	0	0
T53	3213	0	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	710480	0	0
T2	286097	5740	0	0
T3	779003	3180	0	0
T4	262640	5206	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	2687	0	0
T15	4013	28	0	0
T16	46002	2697	0	0
T17	109814	2111	0	0
T19	0	14	0	0
T37	0	5605	0	0
T38	0	2127	0	0
T53	3213	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T76,T77,T79

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T37,T30,T21

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T76,T77,T79
0	0	1	-	-	Covered	T37,T30,T21
0	0	0	1	-	Covered	T2,T3,T4
0	0	0	0	1	Covered	T2,T3,T4
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	425076783	710294	0	0
UpdateCheck_A	425076783	710290	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	710294	0	0
T2	286097	5688	0	0
T3	779003	3174	0	0
T4	262640	5205	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	2704	0	0
T15	4013	26	0	0
T16	46002	2692	0	0
T17	109814	2113	0	0
T19	0	12	0	0
T37	0	5602	0	0
T38	0	2133	0	0
T53	3213	0	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	710290	0	0
T2	286097	5688	0	0
T3	779003	3174	0	0
T4	262640	5205	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	2704	0	0
T15	4013	26	0	0
T16	46002	2692	0	0
T17	109814	2113	0	0
T19	0	12	0	0
T37	0	5602	0	0
T38	0	2133	0	0
T53	3213	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T76,T77,T79

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T37,T30,T68

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T76,T77,T79
0	0	1	-	-	Covered	T37,T30,T68
0	0	0	1	-	Covered	T2,T3,T4
0	0	0	0	1	Covered	T2,T3,T4
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	425076783	709945	0	0
UpdateCheck_A	425076783	709944	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	709945	0	0
T2	286097	5734	0	0
T3	779003	3186	0	0
T4	262640	5207	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	2704	0	0
T15	4013	25	0	0
T16	46002	2685	0	0
T17	109814	2115	0	0
T19	0	12	0	0
T37	0	5596	0	0
T38	0	2133	0	0
T53	3213	0	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	709944	0	0
T2	286097	5734	0	0
T3	779003	3186	0	0
T4	262640	5207	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	2704	0	0
T15	4013	25	0	0
T16	46002	2685	0	0
T17	109814	2115	0	0
T19	0	12	0	0
T37	0	5596	0	0
T38	0	2133	0	0
T53	3213	0	0	0