Unified Coverage Report :: Module :: flash_phy_rd

Module : flash_phy_rd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.58	100.00	90.31			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd	97.47	100.00	89.87			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd	97.58	100.00	90.31			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.47	100.00	89.87			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.57	99.17	93.18	100.00		99.28	96.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.55	100.00	84.91		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
u_bus_intg	100.00	100.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.58	100.00	90.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	99.17	93.34	100.00		99.28	96.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.06	100.00	92.45		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
u_bus_intg	100.00	100.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

Line Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
TOTAL		124	124	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	577	6	6	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	594	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	646	6	6	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	716	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
488	1	1
491	1	1
494	1	1
498	1	1
500	1	1
501	1	1
502	1	1
510	1	1
518	1	1
520	1	1
574	1	1
575	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
582	1	1
			MISSING_ELSE
587	1	1
591	1	1
594	1	1
601	1	1
605	1	1
613	1	1
630	1	1
635	1	1
640	4	4
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
651	1	1
			MISSING_ELSE
657	1	1
669	1	1
670	1	1
691	1	1
703	1	1
706	1	1
710	1	1
713	1	1
716	1	1

---

Cond Coverage for Module : flash_phy_rd

	Total	Covered	Percent
Conditions	454	410	90.31
Logical	454	410	90.31
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
139-706	90.62
706-710	66.67

---

Branch Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	510	3	3	100.00
TERNARY	601	3	3	100.00
TERNARY	605	3	3	100.00
TERNARY	630	3	3	100.00
TERNARY	657	2	2	100.00
TERNARY	691	2	2	100.00
TERNARY	670	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	577	4	4	100.00
IF	649	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	301	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T19,T31
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	510	(hint_descram) ? 
-2-:	510	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T126,T46,T207
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	(forward) ? 
-2-:	601	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	605	(forward) ? 
-2-:	605	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	630	(forward) ? 
-2-:	630	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	657	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	691	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	670	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	577	if ((!rst_ni))
-2-:	579	if (calc_req_start)
-3-:	581	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	850153566	1625179	0	0
ExclusiveOps_A	850153566	848389930	0	0
ExclusiveProgHazard_A	850153566	848389930	0	0
ExclusiveState_A	850153566	848389930	0	0
ForwardCheck_A	850153566	3971503	0	0
IdleCheck_A	850153566	104051148	0	0
MaxBufs_A	2124	2124	0	0
OneHotAlloc_A	850153566	848389930	0	0
OneHotMatch_A	850153566	848389930	0	0
OneHotRspMatch_A	850153566	848389930	0	0
OneHotUpdate_A	850153566	848389930	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850153566	1625179	0	0
T2	572194	2349	0	0
T3	1558006	4528	0	0
T4	525280	1474	0	0
T5	1982	0	0	0
T9	7224	0	0	0
T14	1644610	5890	0	0
T15	8026	115	0	0
T16	92004	1798	0	0
T17	219628	501	0	0
T19	0	36	0	0
T31	0	73	0	0
T37	0	2514	0	0
T38	0	250	0	0
T40	0	1880	0	0
T53	6426	0	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850153566	848389930	0	0
T1	3058	2566	0	0
T2	572194	572062	0	0
T3	1558006	1557746	0	0
T4	525280	525178	0	0
T5	1982	1830	0	0
T9	7224	5954	0	0
T14	1644610	1644310	0	0
T15	8026	7806	0	0
T16	92004	91866	0	0
T17	219628	219438	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850153566	848389930	0	0
T1	3058	2566	0	0
T2	572194	572062	0	0
T3	1558006	1557746	0	0
T4	525280	525178	0	0
T5	1982	1830	0	0
T9	7224	5954	0	0
T14	1644610	1644310	0	0
T15	8026	7806	0	0
T16	92004	91866	0	0
T17	219628	219438	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850153566	848389930	0	0
T1	3058	2566	0	0
T2	572194	572062	0	0
T3	1558006	1557746	0	0
T4	525280	525178	0	0
T5	1982	1830	0	0
T9	7224	5954	0	0
T14	1644610	1644310	0	0
T15	8026	7806	0	0
T16	92004	91866	0	0
T17	219628	219438	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850153566	3971503	0	0
T2	572194	35608	0	0
T3	1558006	22723	0	0
T4	525280	43965	0	0
T5	1982	0	0	0
T9	7224	0	0	0
T14	1644610	23454	0	0
T15	8026	5	0	0
T16	92004	19756	0	0
T17	219628	14859	0	0
T19	0	17	0	0
T25	0	32	0	0
T26	0	32	0	0
T37	0	44838	0	0
T38	0	79	0	0
T53	6426	0	0	0
T62	0	12	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850153566	104051148	0	0
T1	1529	268	0	0
T2	572194	168552	0	0
T3	1558006	1165522	0	0
T4	525280	152222	0	0
T5	1982	128	0	0
T9	7224	672	0	0
T14	1644610	1204196	0	0
T15	8026	777	0	0
T16	92004	41438	0	0
T17	219628	68208	0	0
T19	0	210	0	0
T37	0	73178	0	0
T38	0	43259	0	0
T53	3213	0	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2124	2124	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T9	2	2	0	0
T14	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850153566	848389930	0	0
T1	3058	2566	0	0
T2	572194	572062	0	0
T3	1558006	1557746	0	0
T4	525280	525178	0	0
T5	1982	1830	0	0
T9	7224	5954	0	0
T14	1644610	1644310	0	0
T15	8026	7806	0	0
T16	92004	91866	0	0
T17	219628	219438	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850153566	848389930	0	0
T1	3058	2566	0	0
T2	572194	572062	0	0
T3	1558006	1557746	0	0
T4	525280	525178	0	0
T5	1982	1830	0	0
T9	7224	5954	0	0
T14	1644610	1644310	0	0
T15	8026	7806	0	0
T16	92004	91866	0	0
T17	219628	219438	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850153566	848389930	0	0
T1	3058	2566	0	0
T2	572194	572062	0	0
T3	1558006	1557746	0	0
T4	525280	525178	0	0
T5	1982	1830	0	0
T9	7224	5954	0	0
T14	1644610	1644310	0	0
T15	8026	7806	0	0
T16	92004	91866	0	0
T17	219628	219438	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850153566	848389930	0	0
T1	3058	2566	0	0
T2	572194	572062	0	0
T3	1558006	1557746	0	0
T4	525280	525178	0	0
T5	1982	1830	0	0
T9	7224	5954	0	0
T14	1644610	1644310	0	0
T15	8026	7806	0	0
T16	92004	91866	0	0
T17	219628	219438	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		124	124	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	577	6	6	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	594	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	646	6	6	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	716	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
488	1	1
491	1	1
494	1	1
498	1	1
500	1	1
501	1	1
502	1	1
510	1	1
518	1	1
520	1	1
574	1	1
575	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
582	1	1
			MISSING_ELSE
587	1	1
591	1	1
594	1	1
601	1	1
605	1	1
613	1	1
630	1	1
635	1	1
640	4	4
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
651	1	1
			MISSING_ELSE
657	1	1
669	1	1
670	1	1
691	1	1
703	1	1
706	1	1
710	1	1
713	1	1
716	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Covered	Percent
Conditions	454	408	89.87
Logical	454	408	89.87
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
139-706	89.80
710	100.00

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	510	3	3	100.00
TERNARY	601	3	3	100.00
TERNARY	605	3	3	100.00
TERNARY	630	3	3	100.00
TERNARY	657	2	2	100.00
TERNARY	691	2	2	100.00
TERNARY	670	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	577	4	4	100.00
IF	649	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	301	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T19,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	510	(hint_descram) ? 
-2-:	510	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T15,T17
0	1	Covered	T126,T46,T127
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	(forward) ? 
-2-:	601	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T15,T17
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	605	(forward) ? 
-2-:	605	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	630	(forward) ? 
-2-:	630	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T15,T17
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	657	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	691	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T15,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	670	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T19,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	577	if ((!rst_ni))
-2-:	579	if (calc_req_start)
-3-:	581	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T15,T17
0	0	1	Covered	T2,T15,T17
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	425076783	786462	0	0
ExclusiveOps_A	425076783	424194965	0	0
ExclusiveProgHazard_A	425076783	424194965	0	0
ExclusiveState_A	425076783	424194965	0	0
ForwardCheck_A	425076783	1938960	0	0
IdleCheck_A	425076783	50310647	0	0
MaxBufs_A	1062	1062	0	0
OneHotAlloc_A	425076783	424194965	0	0
OneHotMatch_A	425076783	424194965	0	0
OneHotRspMatch_A	425076783	424194965	0	0
OneHotUpdate_A	425076783	424194965	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	786462	0	0
T2	286097	1571	0	0
T3	779003	2797	0	0
T4	262640	306	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	2276	0	0
T15	4013	115	0	0
T16	46002	939	0	0
T17	109814	257	0	0
T19	0	36	0	0
T37	0	1630	0	0
T38	0	86	0	0
T53	3213	0	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	1938960	0	0
T2	286097	20796	0	0
T3	779003	12709	0	0
T4	262640	20825	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	10799	0	0
T15	4013	5	0	0
T16	46002	10766	0	0
T17	109814	6099	0	0
T19	0	17	0	0
T37	0	22400	0	0
T53	3213	0	0	0
T62	0	12	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	50310647	0	0
T2	286097	79103	0	0
T3	779003	650956	0	0
T4	262640	70260	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	553025	0	0
T15	4013	521	0	0
T16	46002	22471	0	0
T17	109814	21787	0	0
T19	0	210	0	0
T37	0	73178	0	0
T38	0	43259	0	0
T53	3213	0	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		124	124	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	577	6	6	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	594	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	646	6	6	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	716	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
488	1	1
491	1	1
494	1	1
498	1	1
500	1	1
501	1	1
502	1	1
510	1	1
518	1	1
520	1	1
574	1	1
575	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
582	1	1
			MISSING_ELSE
587	1	1
591	1	1
594	1	1
601	1	1
605	1	1
613	1	1
630	1	1
635	1	1
640	4	4
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
651	1	1
			MISSING_ELSE
657	1	1
669	1	1
670	1	1
691	1	1
703	1	1
706	1	1
710	1	1
713	1	1
716	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Covered	Percent
Conditions	454	410	90.31
Logical	454	410	90.31
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
139-706	90.62
706-710	66.67

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	510	3	3	100.00
TERNARY	601	3	3	100.00
TERNARY	605	3	3	100.00
TERNARY	630	3	3	100.00
TERNARY	657	2	2	100.00
TERNARY	691	2	2	100.00
TERNARY	670	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	577	4	4	100.00
IF	649	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	301	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T31,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	510	(hint_descram) ? 
-2-:	510	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T126,T46,T207
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	(forward) ? 
-2-:	601	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	605	(forward) ? 
-2-:	605	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	630	(forward) ? 
-2-:	630	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	657	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	691	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	670	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T70
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	577	if ((!rst_ni))
-2-:	579	if (calc_req_start)
-3-:	581	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	425076783	838717	0	0
ExclusiveOps_A	425076783	424194965	0	0
ExclusiveProgHazard_A	425076783	424194965	0	0
ExclusiveState_A	425076783	424194965	0	0
ForwardCheck_A	425076783	2032543	0	0
IdleCheck_A	425076783	53740501	0	0
MaxBufs_A	1062	1062	0	0
OneHotAlloc_A	425076783	424194965	0	0
OneHotMatch_A	425076783	424194965	0	0
OneHotRspMatch_A	425076783	424194965	0	0
OneHotUpdate_A	425076783	424194965	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	838717	0	0
T2	286097	778	0	0
T3	779003	1731	0	0
T4	262640	1168	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	3614	0	0
T15	4013	0	0	0
T16	46002	859	0	0
T17	109814	244	0	0
T31	0	73	0	0
T37	0	884	0	0
T38	0	164	0	0
T40	0	1880	0	0
T53	3213	0	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	2032543	0	0
T2	286097	14812	0	0
T3	779003	10014	0	0
T4	262640	23140	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	12655	0	0
T15	4013	0	0	0
T16	46002	8990	0	0
T17	109814	8760	0	0
T25	0	32	0	0
T26	0	32	0	0
T37	0	22438	0	0
T38	0	79	0	0
T53	3213	0	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	53740501	0	0
T1	1529	268	0	0
T2	286097	89449	0	0
T3	779003	514566	0	0
T4	262640	81962	0	0
T5	991	128	0	0
T9	3612	672	0	0
T14	822305	651171	0	0
T15	4013	256	0	0
T16	46002	18967	0	0
T17	109814	46421	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0