Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_disable_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.34 97.12 92.80 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_disable_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.56 97.67 92.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.06 100.00 92.45 100.00 97.83 100.00 gen_flash_cores[0].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.55 100.00 84.91 100.00 97.83 100.00 gen_flash_cores[1].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=8,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_disable_buf

Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 8 8


Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=3,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_eflash.u_disable_buf

Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 3 3


Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=4,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf

SCORELINE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf

Line No.TotalCoveredPercent
TOTAL55100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 4 4


Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 4248 4248 0 0
OutputsKnown_A 1700307132 1696779860 0 0
gen_no_flops.OutputDelay_A 1700307132 1696779860 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 4248 4248 0 0
T1 4 4 0 0
T2 4 4 0 0
T3 4 4 0 0
T4 4 4 0 0
T5 4 4 0 0
T9 4 4 0 0
T14 4 4 0 0
T15 4 4 0 0
T16 4 4 0 0
T17 4 4 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1700307132 1696779860 0 0
T1 6116 5132 0 0
T2 1144388 1144124 0 0
T3 3116012 3115492 0 0
T4 1050560 1050356 0 0
T5 3964 3660 0 0
T9 14448 11908 0 0
T14 3289220 3288620 0 0
T15 16052 15612 0 0
T16 184008 183732 0 0
T17 439256 438876 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1700307132 1696779860 0 0
T1 6116 5132 0 0
T2 1144388 1144124 0 0
T3 3116012 3115492 0 0
T4 1050560 1050356 0 0
T5 3964 3660 0 0
T9 14448 11908 0 0
T14 3289220 3288620 0 0
T15 16052 15612 0 0
T16 184008 183732 0 0
T17 439256 438876 0 0

Line Coverage for Instance : tb.dut.u_disable_buf
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 8 8


Assert Coverage for Instance : tb.dut.u_disable_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1062 1062 0 0
OutputsKnown_A 425076783 424194965 0 0
gen_no_flops.OutputDelay_A 425076783 424194965 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_disable_buf
Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 3 3


Assert Coverage for Instance : tb.dut.u_eflash.u_disable_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1062 1062 0 0
OutputsKnown_A 425076783 424194965 0 0
gen_no_flops.OutputDelay_A 425076783 424194965 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf
Line No.TotalCoveredPercent
TOTAL55100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 4 4


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1062 1062 0 0
OutputsKnown_A 425076783 424194965 0 0
gen_no_flops.OutputDelay_A 425076783 424194965 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf
Line No.TotalCoveredPercent
TOTAL55100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 4 4


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1062 1062 0 0
OutputsKnown_A 425076783 424194965 0 0
gen_no_flops.OutputDelay_A 425076783 424194965 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%