Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : flash_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.34 97.12 92.80 98.44 100.00 98.33

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 97.34 97.12 92.80 98.44 100.00 98.33



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.34 97.12 92.80 98.44 100.00 98.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.27 95.84 94.13 98.85 92.52 98.24 98.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
flash_ctrl_core_csr_assert 100.00 100.00
gen_alert_senders[0].u_alert_sender 100.00 100.00
gen_alert_senders[1].u_alert_sender 100.00 100.00
gen_alert_senders[2].u_alert_sender 100.00 100.00
gen_alert_senders[3].u_alert_sender 100.00 100.00
gen_alert_senders[4].u_alert_sender 77.78 77.78
tlul_assert_device 99.65 100.00 100.00 98.95
u_ctrl_arb 100.00 100.00 100.00 100.00 100.00 100.00
u_disable_buf 100.00 100.00 100.00
u_eflash 97.62 98.50 93.26 99.49 97.62 99.38 97.49
u_exec_en_buf 100.00 100.00
u_flash_ctrl_erase 100.00 100.00 100.00 100.00
u_flash_ctrl_prog 97.88 100.00 97.06 100.00 94.44
u_flash_ctrl_rd 94.44 83.02 93.94 100.00 100.00 95.24
u_flash_hw_if 96.18 99.02 93.52 95.83 92.11 96.62 100.00
u_flash_mp 99.54 100.00 98.16 100.00 100.00
u_intr_corr_err 93.75 100.00 75.00 100.00 100.00
u_intr_op_done 93.75 100.00 75.00 100.00 100.00
u_intr_prog_empty 86.94 90.00 77.78 80.00 100.00
u_intr_prog_lvl 86.94 90.00 77.78 80.00 100.00
u_intr_rd_full 86.94 90.00 77.78 80.00 100.00
u_intr_rd_lvl 86.94 90.00 77.78 80.00 100.00
u_lc_escalation_en_sync 100.00 100.00 100.00 100.00
u_lc_seed_hw_rd_en_sync 100.00 100.00 100.00 100.00
u_lfsr 100.00 100.00
u_prog_fifo 97.73 100.00 90.91 100.00 100.00
u_prog_tl_gate 86.16 100.00 89.29 57.14 96.88 87.50
u_reg_core 99.29 99.00 98.55 100.00 98.92 100.00
u_reg_idle 100.00 100.00 100.00
u_region_cfg 87.91 63.73 100.00 100.00
u_sw_rd_fifo 93.67 95.12 88.64 90.91 100.00
u_tl_adapter_eflash 94.24 92.83 83.76 100.00 94.62 100.00
u_tl_gate 85.54 100.00 89.29 57.14 93.75 87.50
u_to_prog_fifo 79.55 89.52 65.48 82.56 80.65
u_to_rd_fifo 91.16 89.08 77.29 100.00 89.41 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl
Line No.TotalCoveredPercent
TOTAL13913597.12
CONT_ASSIGN41111100.00
CONT_ASSIGN41211100.00
CONT_ASSIGN41311100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN41611100.00
CONT_ASSIGN41711100.00
CONT_ASSIGN41811100.00
CONT_ASSIGN41911100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN42111100.00
CONT_ASSIGN42211100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN57311100.00
CONT_ASSIGN57711100.00
CONT_ASSIGN57911100.00
CONT_ASSIGN62311100.00
CONT_ASSIGN62811100.00
ALWAYS63255100.00
CONT_ASSIGN67111100.00
CONT_ASSIGN67211100.00
CONT_ASSIGN67311100.00
CONT_ASSIGN69311100.00
CONT_ASSIGN69711100.00
CONT_ASSIGN72811100.00
ALWAYS74977100.00
CONT_ASSIGN78211100.00
CONT_ASSIGN78311100.00
CONT_ASSIGN85411100.00
CONT_ASSIGN85611100.00
CONT_ASSIGN85711100.00
CONT_ASSIGN85811100.00
CONT_ASSIGN85911100.00
CONT_ASSIGN86011100.00
CONT_ASSIGN86111100.00
CONT_ASSIGN86211100.00
CONT_ASSIGN86311100.00
CONT_ASSIGN86411100.00
CONT_ASSIGN86511100.00
CONT_ASSIGN86711100.00
CONT_ASSIGN87011100.00
CONT_ASSIGN87311100.00
CONT_ASSIGN87611100.00
CONT_ASSIGN878100.00
CONT_ASSIGN880100.00
CONT_ASSIGN88411100.00
CONT_ASSIGN88511100.00
CONT_ASSIGN88611100.00
CONT_ASSIGN88711100.00
CONT_ASSIGN88811100.00
CONT_ASSIGN88911100.00
CONT_ASSIGN89011100.00
CONT_ASSIGN89111100.00
CONT_ASSIGN89211100.00
CONT_ASSIGN89311100.00
CONT_ASSIGN89411100.00
CONT_ASSIGN89511100.00
CONT_ASSIGN89611100.00
CONT_ASSIGN89711100.00
CONT_ASSIGN89811100.00
CONT_ASSIGN89911100.00
CONT_ASSIGN90111100.00
CONT_ASSIGN902100.00
CONT_ASSIGN90311100.00
CONT_ASSIGN90411100.00
CONT_ASSIGN90511100.00
CONT_ASSIGN91111100.00
CONT_ASSIGN93511100.00
CONT_ASSIGN94011100.00
CONT_ASSIGN94311100.00
CONT_ASSIGN94611100.00
CONT_ASSIGN94811100.00
CONT_ASSIGN95611100.00
CONT_ASSIGN100911100.00
CONT_ASSIGN101311100.00
CONT_ASSIGN102511100.00
CONT_ASSIGN102611100.00
CONT_ASSIGN104011100.00
CONT_ASSIGN105411100.00
CONT_ASSIGN105511100.00
CONT_ASSIGN107311100.00
CONT_ASSIGN107411100.00
CONT_ASSIGN107511100.00
CONT_ASSIGN107611100.00
CONT_ASSIGN107711100.00
CONT_ASSIGN107811100.00
CONT_ASSIGN107911100.00
CONT_ASSIGN1080100.00
CONT_ASSIGN108111100.00
CONT_ASSIGN108211100.00
CONT_ASSIGN110311100.00
CONT_ASSIGN110411100.00
CONT_ASSIGN110511100.00
CONT_ASSIGN110611100.00
CONT_ASSIGN110711100.00
CONT_ASSIGN110811100.00
CONT_ASSIGN110911100.00
CONT_ASSIGN111011100.00
CONT_ASSIGN111111100.00
CONT_ASSIGN111211100.00
CONT_ASSIGN111311100.00
CONT_ASSIGN111411100.00
CONT_ASSIGN112611100.00
CONT_ASSIGN112811100.00
CONT_ASSIGN112911100.00
CONT_ASSIGN113011100.00
CONT_ASSIGN113111100.00
CONT_ASSIGN113211100.00
CONT_ASSIGN113311100.00
CONT_ASSIGN113411100.00
CONT_ASSIGN113511100.00
CONT_ASSIGN113911100.00
CONT_ASSIGN113911100.00
CONT_ASSIGN114011100.00
CONT_ASSIGN114011100.00
CONT_ASSIGN114411100.00
CONT_ASSIGN114411100.00
CONT_ASSIGN114511100.00
CONT_ASSIGN114511100.00
CONT_ASSIGN115011100.00
CONT_ASSIGN115211100.00
CONT_ASSIGN115311100.00
CONT_ASSIGN115511100.00
CONT_ASSIGN115711100.00
CONT_ASSIGN115811100.00
CONT_ASSIGN126111100.00
CONT_ASSIGN126211100.00
CONT_ASSIGN127811100.00
CONT_ASSIGN139011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv' or '../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
411 1 1
412 1 1
413 1 1
414 1 1
415 1 1
416 1 1
417 1 1
418 1 1
419 1 1
420 1 1
421 1 1
422 1 1
507 1 1
573 1 1
577 1 1
579 1 1
623 1 1
628 1 1
632 1 1
633 1 1
634 1 1
636 1 1
637 1 1
671 1 1
672 1 1
673 1 1
693 1 1
697 1 1
728 1 1
749 1 1
751 1 1
752 1 1
755 1 1
756 1 1
759 1 1
760 1 1
782 1 1
783 1 1
854 1 1
856 1 1
857 1 1
858 1 1
859 1 1
860 1 1
861 1 1
862 1 1
863 1 1
864 1 1
865 1 1
867 1 1
870 1 1
873 1 1
876 1 1
878 0 1
880 0 1
884 1 1
885 1 1
886 1 1
887 1 1
888 1 1
889 1 1
890 1 1
891 1 1
892 1 1
893 1 1
894 1 1
895 1 1
896 1 1
897 1 1
898 1 1
899 1 1
901 1 1
902 0 1
903 1 1
904 1 1
905 1 1
911 1 1
935 1 1
940 1 1
943 1 1
946 1 1
948 1 1
956 1 1
1009 1 1
1013 1 1
1025 1 1
1026 1 1
1040 1 1
1054 1 1
1055 1 1
1073 1 1
1074 1 1
1075 1 1
1076 1 1
1077 1 1
1078 1 1
1079 1 1
1080 0 1
1081 1 1
1082 1 1
1103 1 1
1104 1 1
1105 1 1
1106 1 1
1107 1 1
1108 1 1
1109 1 1
1110 1 1
1111 1 1
1112 1 1
1113 1 1
1114 1 1
1126 1 1
1128 1 1
1129 1 1
1130 1 1
1131 1 1
1132 1 1
1133 1 1
1134 1 1
1135 1 1
1139 2 2
1140 2 2
1144 2 2
1145 2 2
1150 1 1
1152 1 1
1153 1 1
1155 1 1
1157 1 1
1158 1 1
1261 1 1
1262 1 1
1278 1 1
1390 1 1


Cond Coverage for Module : flash_ctrl
TotalCoveredPercent
Conditions12511692.80
Logical12511692.80
Non-Logical00
Event00

 LINE       337
 EXPRESSION (sw_wvalid & prog_op_valid)
             ----1----   ------2------
-1--2-StatusTests
01CoveredT2,T4,T5
10CoveredT32,T130,T184
11CoveredT2,T4,T5

 LINE       419
 EXPRESSION (op_type == FlashOpRead)
            ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       420
 EXPRESSION (op_type == FlashOpProgram)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       421
 EXPRESSION (op_type == FlashOpErase)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T40,T10

 LINE       422
 EXPRESSION (if_sel == SwSel)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       429
 EXPRESSION (((~sw_sel)) & rd_ctrl_wen)
             -----1-----   -----2-----
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       507
 EXPRESSION (op_start & prog_op)
             ----1---   ---2---
-1--2-StatusTests
01CoveredT2,T4,T5
10CoveredT1,T2,T3
11CoveredT2,T4,T5

 LINE       559
 EXPRESSION (reg2hw.fifo_rst.q | fifo_clr | sw_ctrl_done)
             --------1--------   ----2---   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT2,T3,T4
010CoveredT1,T2,T3
100Not Covered

 LINE       577
 EXPRESSION (flash_phy_rsp.prog_type_avail[FlashProgNormal] & reg2hw.prog_type_en.normal.q)
             -----------------------1----------------------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT178,T179,T180
11CoveredT1,T2,T3

 LINE       579
 EXPRESSION (flash_phy_rsp.prog_type_avail[FlashProgRepair] & reg2hw.prog_type_en.repair.q)
             -----------------------1----------------------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT178,T179,T180
11CoveredT1,T2,T3

 LINE       623
 EXPRESSION (reg2hw.control.start.q & (reg2hw.control.op.q == FlashOpRead))
             -----------1----------   ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T5
11CoveredT2,T3,T4

 LINE       623
 SUB-EXPRESSION (reg2hw.control.op.q == FlashOpRead)
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       636
 EXPRESSION (adapter_req & sw_rfifo_rvalid)
             -----1-----   -------2-------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T4,T16
11CoveredT2,T3,T4

 LINE       649
 EXPRESSION (sw_rfifo_rvalid | rd_no_op_d)
             -------1-------   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T38,T39
10CoveredT2,T3,T4

 LINE       649
 EXPRESSION (adapter_rvalid | rd_no_op_q)
             -------1------   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T38,T39
10CoveredT2,T3,T4

 LINE       671
 EXPRESSION (sw_sel & rd_ctrl_wen)
             ---1--   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       697
 EXPRESSION (op_start & rd_op)
             ----1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T5
11CoveredT1,T2,T3

 LINE       698
 EXPRESSION (sw_sel ? sw_rfifo_wready : lcmgr_rready)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       728
 EXPRESSION (op_start & erase_op)
             ----1---   ----2---
-1--2-StatusTests
01CoveredT15,T40,T25
10CoveredT1,T2,T3
11CoveredT15,T40,T10

 LINE       792
 EXPRESSION (rd_flash_ovfl | prog_flash_ovfl)
             ------1------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       792
 EXPRESSION (erase_op & (erase_flash_type == FlashErasePage))
             ----1---   ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T66,T67
11CoveredT15,T40,T10

 LINE       792
 SUB-EXPRESSION (erase_flash_type == FlashErasePage)
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       792
 EXPRESSION (erase_op & (erase_flash_type == FlashEraseBank))
             ----1---   ------------------2-----------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT15,T40,T10
11CoveredT30,T66,T67

 LINE       792
 SUB-EXPRESSION (erase_flash_type == FlashEraseBank)
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       865
 EXPRESSION (flash_phy_busy | ctrl_init_busy)
             -------1------   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       867
 EXPRESSION (ctrl_initialized & ((~flash_phy_busy)))
             --------1-------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT128,T129,T130
11CoveredT1,T2,T3

 LINE       873
 EXPRESSION (sw_sel ? ((!op_start)) : 1'b1)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       911
 SUB-EXPRESSION (flash_phy_req.req & (flash_phy_req.prog | flash_phy_req.pg_erase | flash_phy_req.bk_erase))
                 --------1--------   -----------------------------------2----------------------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T4,T5

 LINE       911
 SUB-EXPRESSION (flash_phy_req.prog | flash_phy_req.pg_erase | flash_phy_req.bk_erase)
                 ---------1--------   -----------2----------   -----------3----------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT30,T66,T67
010CoveredT40,T10,T25
100CoveredT2,T4,T5

 LINE       935
 EXPRESSION ((sw_ctrl_done & ((|sw_ctrl_err))) | flash_phy_rsp.macro_err | update_err)
             ----------------1----------------   -----------2-----------   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Not Covered
100CoveredT2,T4,T15

 LINE       935
 SUB-EXPRESSION (sw_ctrl_done & ((|sw_ctrl_err)))
                 ------1-----   --------2-------
-1--2-StatusTests
01CoveredT2,T4,T17
10CoveredT2,T3,T4
11CoveredT2,T4,T15

 LINE       956
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_flash_alert.q & reg2hw.alert_test.recov_prim_flash_alert.qe)
                 ---------------------1--------------------   ---------------------2---------------------
-1--2-StatusTests
01CoveredT53,T102,T185
10CoveredT1,T2,T3
11CoveredT53,T102,T185

 LINE       956
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_flash_alert.q & reg2hw.alert_test.fatal_prim_flash_alert.qe)
                 ---------------------1--------------------   ---------------------2---------------------
-1--2-StatusTests
01CoveredT53,T102,T185
10CoveredT1,T2,T3
11CoveredT53,T102,T185

 LINE       956
 SUB-EXPRESSION (reg2hw.alert_test.fatal_err.q & reg2hw.alert_test.fatal_err.qe)
                 --------------1--------------   ---------------2--------------
-1--2-StatusTests
01CoveredT53,T102,T185
10CoveredT1,T2,T3
11CoveredT53,T102,T185

 LINE       956
 SUB-EXPRESSION (reg2hw.alert_test.fatal_std_err.q & reg2hw.alert_test.fatal_std_err.qe)
                 ----------------1----------------   -----------------2----------------
-1--2-StatusTests
01CoveredT53,T102,T185
10CoveredT1,T2,T3
11CoveredT53,T102,T185

 LINE       956
 SUB-EXPRESSION (reg2hw.alert_test.recov_err.q & reg2hw.alert_test.recov_err.qe)
                 --------------1--------------   ---------------2--------------
-1--2-StatusTests
01CoveredT53,T102,T185
10CoveredT1,T2,T3
11CoveredT53,T102,T185

 LINE       1082
 EXPRESSION (sw_ctrl_err.mp_err | sw_ctrl_err.rd_err | sw_ctrl_err.prog_err)
             ---------1--------   ---------2--------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT2,T19,T21
100CoveredT2,T4,T15

 LINE       1126
 EXPRESSION (intg_err | eflash_cmd_intg_err | tl_gate_intg_err | tl_prog_gate_intg_err)
             ----1---   ---------2---------   --------3-------   ----------4----------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT12,T13,T36
0010CoveredT12,T13,T36
0100CoveredT18,T41,T42
1000CoveredT12,T13,T36

 LINE       1134
 EXPRESSION (rd_cnt_err | prog_cnt_err)
             -----1----   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T13,T36
10CoveredT12,T13,T36

 LINE       1135
 EXPRESSION (flash_phy_rsp.fifo_err | adapter_fifo_err)
             -----------1----------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T13,T36
10CoveredT12,T13,T36

 LINE       1140
 EXPRESSION (((&reg2hw.ecc_single_err_cnt[0].q)) ? reg2hw.ecc_single_err_cnt[0].q : ((reg2hw.ecc_single_err_cnt[0].q + 1'b1)))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T57,T48

 LINE       1140
 EXPRESSION (((&reg2hw.ecc_single_err_cnt[1].q)) ? reg2hw.ecc_single_err_cnt[1].q : ((reg2hw.ecc_single_err_cnt[1].q + 1'b1)))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T57,T48

 LINE       1390
 EXPRESSION (prog_op_valid | rd_op_valid | erase_op_valid)
             ------1------   -----2-----   -------3------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT15,T40,T10
010CoveredT1,T2,T3
100CoveredT2,T4,T5

Toggle Coverage for Module : flash_ctrl
TotalCoveredPercent
Totals 122 111 90.98
Total Bits 2750 2707 98.44
Total Bits 0->1 1375 1354 98.47
Total Bits 1->0 1375 1353 98.40

Ports 122 111 90.98
Port Bits 2750 2707 98.44
Port Bits 0->1 1375 1354 98.47
Port Bits 1->0 1375 1353 98.40

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T3,T14 Yes T1,T2,T3 INPUT
rst_shadowed_ni Yes Yes T1,T3,T14 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T1,T3,T14 Yes T1,T2,T3 INPUT
lc_creator_seed_sw_rw_en_i[3:0] Yes Yes T2,T5,T16 Yes T1,T2,T3 INPUT
lc_owner_seed_sw_rw_en_i[3:0] Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
lc_iso_part_sw_rd_en_i[3:0] Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
lc_iso_part_sw_wr_en_i[3:0] Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
lc_seed_hw_rd_en_i[3:0] Yes Yes T40,T186,T71 Yes T40,T186,T71 INPUT
lc_escalate_en_i[0] No No Yes T75,T142,T187 INPUT
lc_escalate_en_i[1] No Yes *T75,*T142,*T171 No INPUT
lc_escalate_en_i[2] No No Yes T78,T171,T188 INPUT
lc_escalate_en_i[3] No Yes T75,T78,T171 No INPUT
lc_nvm_debug_en_i[3:0] Yes Yes T40,T186,T189 Yes T40,T186,T190 INPUT
core_tl_i.d_ready Yes Yes T1,T3,T14 Yes T1,T2,T3 INPUT
core_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
core_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
core_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
core_tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_error Yes Yes T1,T2,T3 Yes T1,T3,T14 OUTPUT
core_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_user.rsp_intg[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
prim_tl_i.d_ready Yes Yes T1,T3,T14 Yes T1,T2,T3 INPUT
prim_tl_i.a_user.data_intg[6:0] Yes Yes T53,T10,T124 Yes T3,T4,T10 INPUT
prim_tl_i.a_user.cmd_intg[6:0] Yes Yes T3,T10,T28 Yes T53,T28,T126 INPUT
prim_tl_i.a_user.instr_type[3:0] Yes Yes T37,T10,T126 Yes T2,T126,T185 INPUT
prim_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
prim_tl_i.a_data[31:0] Yes Yes T3,T37,T28 Yes T2,T10,T28 INPUT
prim_tl_i.a_mask[3:0] Yes Yes T2,T53,T37 Yes T3,T10,T38 INPUT
prim_tl_i.a_address[31:0] Yes Yes T3,T10,T28 Yes T2,T53,T37 INPUT
prim_tl_i.a_source[7:0] Yes Yes T2,T3,T25 Yes T3,T4,T37 INPUT
prim_tl_i.a_size[1:0] Yes Yes T3,T10,T25 Yes T53,T126,T58 INPUT
prim_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
prim_tl_i.a_opcode[2:0] Yes Yes T3,T37,T10 Yes T28,T102,T126 INPUT
prim_tl_i.a_valid Yes Yes T63,T191,T65 Yes T63,T191,T65 INPUT
prim_tl_o.a_ready Yes Yes T63,T191,T65 Yes T63,T191,T65 OUTPUT
prim_tl_o.d_error Yes Yes T63,T65,T192 Yes T63,T65,T192 OUTPUT
prim_tl_o.d_user.data_intg[6:0] Yes Yes T63,T191,T65 Yes T63,T191,T65 OUTPUT
prim_tl_o.d_user.rsp_intg[5:0] Yes Yes T63,*T191,T65 Yes T63,T191,T65 OUTPUT
prim_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_data[31:0] Yes Yes T63,T191,T65 Yes T63,T191,T65 OUTPUT
prim_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_source[7:0] Yes Yes T63,T191,T65 Yes T63,T191,T65 OUTPUT
prim_tl_o.d_size[1:0] Yes Yes T63,T191,T65 Yes T63,T191,T65 OUTPUT
prim_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_opcode[0] Yes Yes *T63,*T191,*T65 Yes T63,T191,T65 OUTPUT
prim_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_valid Yes Yes T63,T191,T65 Yes T63,T191,T65 OUTPUT
mem_tl_i.d_ready Yes Yes T1,T3,T14 Yes T1,T2,T3 INPUT
mem_tl_i.a_user.data_intg[6:0] Yes Yes T9,T5,T15 Yes T1,T9,T15 INPUT
mem_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
mem_tl_i.a_user.instr_type[3:0] Yes Yes T1,T9,T15 Yes T1,T9,T15 INPUT
mem_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
mem_tl_i.a_data[31:0] Yes Yes T1,T9,T15 Yes T9,T5,T15 INPUT
mem_tl_i.a_mask[3:0] Yes Yes T1,T9,T15 Yes T1,T9,T5 INPUT
mem_tl_i.a_address[31:0] Yes Yes T9,T15,T16 Yes T1,T9,T15 INPUT
mem_tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
mem_tl_i.a_size[1:0] Yes Yes T1,T9,T5 Yes T1,T9,T15 INPUT
mem_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
mem_tl_i.a_opcode[2:0] Yes Yes T1,T9,T15 Yes T1,T9,T15 INPUT
mem_tl_i.a_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
mem_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mem_tl_o.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mem_tl_o.d_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
mem_tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mem_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
mem_tl_o.d_data[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
mem_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
mem_tl_o.d_source[7:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
mem_tl_o.d_size[1:0] Yes Yes T63,T65,T192 Yes T63,T65,T192 OUTPUT
mem_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
mem_tl_o.d_opcode[0] Yes Yes *T63,*T65,*T192 Yes T63,T65,T192 OUTPUT
mem_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
mem_tl_o.d_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
otp_o.addr_req Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_o.data_req Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_i.seed_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
otp_i.rand_key[127:0] Yes Yes T1,T14,T15 Yes T1,T2,T14 INPUT
otp_i.key[127:0] Yes Yes T1,T4,T14 Yes T1,T2,T4 INPUT
otp_i.addr_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
otp_i.data_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rma_req_i[3:0] Yes Yes T9,T56,T70 Yes T9,T10,T56 INPUT
rma_seed_i[31:0] Yes Yes T56,T70,T173 Yes T9,T56,T70 INPUT
rma_ack_o[3:0] Yes Yes T76,T77,T164 Yes T56,T76,T122 OUTPUT
pwrmgr_o.flash_idle Yes Yes T2,T4,T5 Yes T2,T4,T5 OUTPUT
keymgr_o.seeds[0][0] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[0][1] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][2] Yes Yes T193,T40,T26 Yes T193,T40,T26 OUTPUT
keymgr_o.seeds[0][3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][4] Yes Yes T193,T40,T26 Yes T193,T40,T26 OUTPUT
keymgr_o.seeds[0][5] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][6] Yes Yes T40,T25,T26 Yes T40,T25,T26 OUTPUT
keymgr_o.seeds[0][9:7] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][10] Yes Yes T15,T40,T26 Yes T15,T40,T26 OUTPUT
keymgr_o.seeds[0][11] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][12] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[0][13] Yes Yes T40,T34,T70 Yes T40,T34,T70 OUTPUT
keymgr_o.seeds[0][14] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[0][17:15] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][18] Yes Yes T193,T40,T25 Yes T193,T40,T25 OUTPUT
keymgr_o.seeds[0][21:19] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][22] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][23] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][24] Yes Yes T40,T56,T34 Yes T40,T56,T34 OUTPUT
keymgr_o.seeds[0][25] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[0][26] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][27] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][28] Yes Yes T40,T19,T26 Yes T40,T19,T26 OUTPUT
keymgr_o.seeds[0][32:29] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][33] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[0][35:34] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][36] Yes Yes T40,T25,T62 Yes T40,T25,T62 OUTPUT
keymgr_o.seeds[0][37] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[0][38] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][40:39] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][41] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[0][42] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][43] Yes Yes T40,T62,T56 Yes T40,T62,T56 OUTPUT
keymgr_o.seeds[0][44] Yes Yes T15,T40,T26 Yes T15,T40,T26 OUTPUT
keymgr_o.seeds[0][45] Yes Yes T40,T62,T56 Yes T40,T62,T56 OUTPUT
keymgr_o.seeds[0][46] Yes Yes T40,T19,T26 Yes T40,T19,T26 OUTPUT
keymgr_o.seeds[0][47] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][48] Yes Yes T15,T40,T26 Yes T15,T40,T26 OUTPUT
keymgr_o.seeds[0][49] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][50] Yes Yes T193,T40,T62 Yes T193,T40,T62 OUTPUT
keymgr_o.seeds[0][52:51] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][53] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[0][54] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[0][55] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][56] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[0][57] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][58] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[0][60:59] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][61] Yes Yes T40,T25,T56 Yes T40,T25,T56 OUTPUT
keymgr_o.seeds[0][62] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][63] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][64] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[0][65] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][66] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[0][67] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][68] Yes Yes T40,T26,T56 Yes T40,T26,T56 OUTPUT
keymgr_o.seeds[0][69] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][70] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[0][71] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][72] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][73] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][74] Yes Yes T193,T40,T25 Yes T193,T40,T25 OUTPUT
keymgr_o.seeds[0][75] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[0][77:76] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][78] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[0][79] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][80] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[0][81] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][82] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][83] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][84] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][85] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][86] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[0][90:87] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][91] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][92] Yes Yes T193,T40,T26 Yes T193,T40,T26 OUTPUT
keymgr_o.seeds[0][98:93] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][99] Yes Yes T40,T26,T56 Yes T40,T26,T56 OUTPUT
keymgr_o.seeds[0][101:100] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][102] Yes Yes T40,T25,T56 Yes T40,T25,T56 OUTPUT
keymgr_o.seeds[0][103] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][104] Yes Yes T40,T19,T25 Yes T40,T19,T25 OUTPUT
keymgr_o.seeds[0][105] Yes Yes T193,T40,T25 Yes T193,T40,T25 OUTPUT
keymgr_o.seeds[0][106] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][107] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[0][108] Yes Yes T40,T62,T56 Yes T40,T62,T56 OUTPUT
keymgr_o.seeds[0][109] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[0][115:110] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][116] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[0][117] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[0][118] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][119] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][120] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][121] Yes Yes T40,T19,T62 Yes T40,T19,T62 OUTPUT
keymgr_o.seeds[0][123:122] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][124] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[0][125] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][129:126] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][130] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[0][131] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][132] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][133] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[0][138:134] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][139] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][140] Yes Yes T40,T19,T25 Yes T40,T19,T25 OUTPUT
keymgr_o.seeds[0][142:141] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][143] Yes Yes T40,T19,T25 Yes T40,T19,T25 OUTPUT
keymgr_o.seeds[0][147:144] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][148] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[0][150:149] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][151] Yes Yes T15,T40,T62 Yes T15,T40,T62 OUTPUT
keymgr_o.seeds[0][152] Yes Yes T193,T40,T26 Yes T193,T40,T26 OUTPUT
keymgr_o.seeds[0][154:153] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][155] Yes Yes T193,T40,T25 Yes T193,T40,T25 OUTPUT
keymgr_o.seeds[0][156] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[0][157] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[0][158] Yes Yes T193,T40,T26 Yes T193,T40,T26 OUTPUT
keymgr_o.seeds[0][159] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[0][160] Yes Yes T40,T19,T30 Yes T40,T19,T30 OUTPUT
keymgr_o.seeds[0][161] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[0][162] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][163] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][164] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][165] Yes Yes T193,T40,T62 Yes T193,T40,T62 OUTPUT
keymgr_o.seeds[0][166] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][167] Yes Yes T40,T19,T25 Yes T40,T19,T25 OUTPUT
keymgr_o.seeds[0][171:168] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][172] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][173] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][174] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][175] Yes Yes T15,T40,T56 Yes T15,T40,T56 OUTPUT
keymgr_o.seeds[0][176] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][177] Yes Yes T40,T26,T62 Yes T40,T26,T62 OUTPUT
keymgr_o.seeds[0][178] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][179] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][181:180] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][182] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][186:183] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][187] Yes Yes T40,T70,T21 Yes T40,T70,T21 OUTPUT
keymgr_o.seeds[0][188] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[0][190:189] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][191] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][192] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][193] Yes Yes T40,T19,T25 Yes T40,T19,T25 OUTPUT
keymgr_o.seeds[0][194] Yes Yes T40,T19,T25 Yes T40,T19,T25 OUTPUT
keymgr_o.seeds[0][195] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][196] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][197] Yes Yes T40,T25,T62 Yes T40,T25,T62 OUTPUT
keymgr_o.seeds[0][198] Yes Yes T15,T40,T56 Yes T15,T40,T56 OUTPUT
keymgr_o.seeds[0][200:199] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][201] Yes Yes T193,T40,T62 Yes T193,T40,T62 OUTPUT
keymgr_o.seeds[0][202] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][203] Yes Yes T193,T40,T56 Yes T193,T40,T56 OUTPUT
keymgr_o.seeds[0][204] Yes Yes T40,T26,T62 Yes T40,T26,T62 OUTPUT
keymgr_o.seeds[0][205] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][207:206] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][208] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][211:209] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][212] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[0][213] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][216:214] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][217] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[0][218] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][219] Yes Yes T40,T30,T34 Yes T40,T30,T34 OUTPUT
keymgr_o.seeds[0][220] Yes Yes T193,T40,T56 Yes T193,T40,T56 OUTPUT
keymgr_o.seeds[0][221] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][222] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][224:223] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][225] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][228:226] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][229] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[0][230] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][231] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[0][232] Yes Yes T193,T40,T25 Yes T193,T40,T25 OUTPUT
keymgr_o.seeds[0][233] Yes Yes T193,T40,T62 Yes T193,T40,T62 OUTPUT
keymgr_o.seeds[0][234] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[0][235] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][236] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][237] Yes Yes T15,T40,T26 Yes T15,T40,T26 OUTPUT
keymgr_o.seeds[0][238] Yes Yes T40,T19,T26 Yes T40,T19,T26 OUTPUT
keymgr_o.seeds[0][240:239] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][241] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][242] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][243] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][244] Yes Yes T40,T26,T62 Yes T40,T26,T62 OUTPUT
keymgr_o.seeds[0][245] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][246] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][247] Yes Yes T40,T19,T26 Yes T40,T19,T26 OUTPUT
keymgr_o.seeds[0][249:248] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][250] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][251] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[0][252] Yes Yes T193,T40,T56 Yes T193,T40,T56 OUTPUT
keymgr_o.seeds[0][254:253] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][255] Yes Yes T193,T40,T25 Yes T193,T40,T25 OUTPUT
keymgr_o.seeds[1][0] Yes Yes T15,T40,T62 Yes T15,T40,T62 OUTPUT
keymgr_o.seeds[1][3:1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][4] Yes Yes T40,T19,T26 Yes T40,T19,T26 OUTPUT
keymgr_o.seeds[1][6:5] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][7] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][13:8] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][14] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[1][19:15] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][20] Yes Yes T40,T62,T56 Yes T40,T62,T56 OUTPUT
keymgr_o.seeds[1][21] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][22] Yes Yes T40,T25,T26 Yes T40,T25,T26 OUTPUT
keymgr_o.seeds[1][23] Yes Yes T40,T62,T56 Yes T40,T62,T56 OUTPUT
keymgr_o.seeds[1][24] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][25] Yes Yes T193,T40,T26 Yes T193,T40,T26 OUTPUT
keymgr_o.seeds[1][26] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[1][28:27] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][29] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][30] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][31] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[1][32] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[1][34:33] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][35] Yes Yes T193,T40,T25 Yes T193,T40,T25 OUTPUT
keymgr_o.seeds[1][36] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][37] Yes Yes T193,T40,T25 Yes T193,T40,T25 OUTPUT
keymgr_o.seeds[1][44:38] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][45] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][46] Yes Yes T193,T40,T26 Yes T193,T40,T26 OUTPUT
keymgr_o.seeds[1][47] Yes Yes T193,T40,T25 Yes T193,T40,T25 OUTPUT
keymgr_o.seeds[1][48] Yes Yes T193,T40,T26 Yes T193,T40,T26 OUTPUT
keymgr_o.seeds[1][49] Yes Yes T193,T40,T26 Yes T193,T40,T26 OUTPUT
keymgr_o.seeds[1][50] Yes Yes T40,T25,T26 Yes T40,T25,T26 OUTPUT
keymgr_o.seeds[1][51] Yes Yes T193,T40,T25 Yes T193,T40,T25 OUTPUT
keymgr_o.seeds[1][52] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][53] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[1][54] Yes Yes T40,T19,T25 Yes T40,T19,T25 OUTPUT
keymgr_o.seeds[1][55] Yes Yes T40,T19,T56 Yes T40,T19,T56 OUTPUT
keymgr_o.seeds[1][57:56] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][58] Yes Yes T40,T19,T25 Yes T40,T19,T25 OUTPUT
keymgr_o.seeds[1][59] Yes Yes T193,T40,T26 Yes T193,T40,T26 OUTPUT
keymgr_o.seeds[1][61:60] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][62] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[1][63] Yes Yes T40,T25,T26 Yes T40,T25,T26 OUTPUT
keymgr_o.seeds[1][64] Yes Yes T193,T40,T62 Yes T193,T40,T62 OUTPUT
keymgr_o.seeds[1][65] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][66] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[1][67] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][68] Yes Yes T15,T40,T62 Yes T15,T40,T62 OUTPUT
keymgr_o.seeds[1][69] Yes Yes T40,T26,T62 Yes T40,T26,T62 OUTPUT
keymgr_o.seeds[1][70] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][71] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[1][72] Yes Yes T40,T19,T25 Yes T40,T19,T25 OUTPUT
keymgr_o.seeds[1][73] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][74] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][75] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[1][76] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][77] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][78] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][79] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[1][80] Yes Yes T40,T26,T62 Yes T40,T26,T62 OUTPUT
keymgr_o.seeds[1][81] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][82] Yes Yes T40,T19,T25 Yes T40,T19,T25 OUTPUT
keymgr_o.seeds[1][83] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][84] Yes Yes T15,T40,T56 Yes T15,T40,T56 OUTPUT
keymgr_o.seeds[1][87:85] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][88] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][89] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[1][91:90] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][92] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][93] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][94] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][95] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][96] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[1][97] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[1][98] Yes Yes T15,T40,T26 Yes T15,T40,T26 OUTPUT
keymgr_o.seeds[1][99] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][100] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][101] Yes Yes T40,T19,T25 Yes T40,T19,T25 OUTPUT
keymgr_o.seeds[1][102] Yes Yes T40,T19,T25 Yes T40,T19,T25 OUTPUT
keymgr_o.seeds[1][103] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][104] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[1][106:105] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][107] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][110:108] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][111] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][114:112] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][115] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][116] Yes Yes T193,T40,T25 Yes T193,T40,T25 OUTPUT
keymgr_o.seeds[1][120:117] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][121] Yes Yes T40,T19,T56 Yes T40,T19,T56 OUTPUT
keymgr_o.seeds[1][124:122] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][125] Yes Yes T40,T19,T70 Yes T40,T19,T70 OUTPUT
keymgr_o.seeds[1][126] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[1][129:127] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][130] Yes Yes T40,T25,T56 Yes T40,T25,T56 OUTPUT
keymgr_o.seeds[1][131] Yes Yes T193,T40,T25 Yes T193,T40,T25 OUTPUT
keymgr_o.seeds[1][132] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][133] Yes Yes T193,T40,T26 Yes T193,T40,T26 OUTPUT
keymgr_o.seeds[1][136:134] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][137] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][138] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][139] Yes Yes T193,T40,T25 Yes T193,T40,T25 OUTPUT
keymgr_o.seeds[1][142:140] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][143] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][144] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][145] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[1][148:146] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][149] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[1][152:150] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][153] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[1][154] Yes Yes T40,T62,T56 Yes T40,T62,T56 OUTPUT
keymgr_o.seeds[1][155] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][156] Yes Yes T193,T40,T25 Yes T193,T40,T25 OUTPUT
keymgr_o.seeds[1][157] Yes Yes T15,T40,T26 Yes T15,T40,T26 OUTPUT
keymgr_o.seeds[1][158] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][159] Yes Yes T40,T25,T62 Yes T40,T25,T62 OUTPUT
keymgr_o.seeds[1][160] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][161] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[1][162] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[1][163] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][169:164] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][170] Yes Yes T40,T25,T26 Yes T40,T25,T26 OUTPUT
keymgr_o.seeds[1][172:171] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][173] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[1][175:174] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][176] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][177] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][178] Yes Yes T40,T26,T62 Yes T40,T26,T62 OUTPUT
keymgr_o.seeds[1][179] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][181:180] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][182] Yes Yes T40,T25,T26 Yes T40,T25,T26 OUTPUT
keymgr_o.seeds[1][183] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][184] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[1][185] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][186] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][187] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[1][188] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][189] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][190] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][191] Yes Yes T40,T25,T62 Yes T40,T25,T62 OUTPUT
keymgr_o.seeds[1][192] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][193] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][194] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][195] Yes Yes T40,T19,T25 Yes T40,T19,T25 OUTPUT
keymgr_o.seeds[1][196] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][202:197] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][203] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[1][205:204] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][206] Yes Yes T40,T62,T56 Yes T40,T62,T56 OUTPUT
keymgr_o.seeds[1][208:207] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][209] Yes Yes T40,T25,T26 Yes T40,T25,T26 OUTPUT
keymgr_o.seeds[1][210] Yes Yes T40,T19,T25 Yes T40,T19,T25 OUTPUT
keymgr_o.seeds[1][211] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[1][212] Yes Yes T40,T19,T25 Yes T40,T19,T25 OUTPUT
keymgr_o.seeds[1][214:213] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][215] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][216] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[1][217] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][218] Yes Yes T40,T56,T30 Yes T40,T56,T30 OUTPUT
keymgr_o.seeds[1][219] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[1][225:220] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][226] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[1][227] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[1][229:228] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][230] Yes Yes T40,T19,T25 Yes T40,T19,T25 OUTPUT
keymgr_o.seeds[1][231] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][232] Yes Yes T40,T25,T26 Yes T40,T25,T26 OUTPUT
keymgr_o.seeds[1][233] Yes Yes T15,T193,T40 Yes T15,T193,T40 OUTPUT
keymgr_o.seeds[1][234] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[1][238:235] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][239] Yes Yes T193,T40,T19 Yes T193,T40,T19 OUTPUT
keymgr_o.seeds[1][242:240] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][243] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[1][244] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][245] Yes Yes T15,T40,T19 Yes T15,T40,T19 OUTPUT
keymgr_o.seeds[1][247:246] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][248] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[1][249] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][250] Yes Yes T40,T19,T70 Yes T40,T19,T70 OUTPUT
keymgr_o.seeds[1][251] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][252] Yes Yes T40,T19,T25 Yes T40,T19,T25 OUTPUT
keymgr_o.seeds[1][253] Yes Yes T15,T40,T25 Yes T15,T40,T25 OUTPUT
keymgr_o.seeds[1][255:254] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cio_tck_i No No No INPUT
cio_tms_i No No No INPUT
cio_tdi_i No No No INPUT
cio_tdo_en_o No No No OUTPUT
cio_tdo_o No No Yes T194,T195,T196 OUTPUT
intr_corr_err_o Yes Yes T19,T21,T33 Yes T19,T21,T33 OUTPUT
intr_prog_empty_o Yes Yes T15,T19,T21 Yes T15,T19,T21 OUTPUT
intr_prog_lvl_o Yes Yes T15,T19,T20 Yes T15,T19,T20 OUTPUT
intr_rd_full_o Yes Yes T3,T28,T29 Yes T3,T28,T29 OUTPUT
intr_rd_lvl_o Yes Yes T3,T14,T28 Yes T3,T14,T28 OUTPUT
intr_op_done_o Yes Yes T3,T14,T15 Yes T3,T14,T15 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T2,T4,T15 Yes T2,T4,T15 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T1,T53,T10 Yes T1,T53,T10 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[2].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[2].ack_p Yes Yes T2,T53,T10 Yes T2,T53,T10 INPUT
alert_rx_i[2].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[2].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[3].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[3].ack_p Yes Yes T53,T102,T185 Yes T53,T102,T185 INPUT
alert_rx_i[3].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[3].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[4].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[4].ack_p Yes Yes T53,T102,T185 Yes T53,T102,T185 INPUT
alert_rx_i[4].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[4].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T2,T4,T15 Yes T2,T4,T15 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T1,T53,T10 Yes T1,T53,T10 OUTPUT
alert_tx_o[2].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[2].alert_p Yes Yes T2,T53,T10 Yes T2,T53,T10 OUTPUT
alert_tx_o[3].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[3].alert_p Yes Yes T53,T102,T185 Yes T53,T102,T185 OUTPUT
alert_tx_o[4].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[4].alert_p Yes Yes T53,T102,T185 Yes T53,T102,T185 OUTPUT
obs_ctrl_i.obmen[3:0] No No No INPUT
obs_ctrl_i.obmsl[3:0] No No No INPUT
obs_ctrl_i.obgsl[3:0] No No No INPUT
fla_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
scan_en_i Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
flash_bist_enable_i[3:0] Unreachable Unreachable Unreachable INPUT
flash_power_down_h_i Yes Yes T1,T2,T3 Yes T1,T3,T14 INPUT
flash_power_ready_h_i Yes Yes T128,T129,T130 Yes T128,T129,T130 INPUT
flash_test_mode_a_io[1:0] No No No INOUT
flash_test_voltage_h_io No No No INOUT

*Tests covering at least one bit in the range

Branch Coverage for Module : flash_ctrl
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 873 2 2 100.00
TERNARY 1140 2 2 100.00
TERNARY 1140 2 2 100.00
TERNARY 698 2 2 100.00
IF 632 2 2 100.00
CASE 749 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv' or '../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 873 (sw_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 1140 ((®2hw.ecc_single_err_cnt[0].q)) ?

Branches:
-1-StatusTests
1 Covered T2,T57,T48
0 Covered T1,T2,T3


LineNo. Expression -1-: 1140 ((®2hw.ecc_single_err_cnt[1].q)) ?

Branches:
-1-StatusTests
1 Covered T2,T57,T48
0 Covered T1,T2,T3


LineNo. Expression -1-: 698 (sw_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 632 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 749 case (op_type)

Branches:
-1-StatusTests
FlashOpRead Covered T1,T2,T3
FlashOpProgram Covered T2,T4,T5
FlashOpErase Covered T15,T40,T10
default Covered T1,T2,T3


Assert Coverage for Module : flash_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 60 60 100.00 59 98.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 60 60 100.00 59 98.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FifoDepthCheck_A 1062 1062 0 0
FlashAddrKnown_A 425076783 308037641 0 0
FlashAddrKnown_AKnownEnable 425076783 424194965 0 0
FlashKnownO_A 425076783 424194965 0 0
FlashProgKnown_A 425076783 187379117 0 0
FlashProgKnown_AKnownEnable 425076783 424194965 0 0
FpvSecCmAddrCntAlertCheck_A 425076783 50 0 0
FpvSecCmArbFsmCheck_A 425076783 50 0 0
FpvSecCmLcCtrlFsmCheck_A 425076783 50 0 0
FpvSecCmLcCtrlRmaFsmCheck_A 425076783 50 0 0
FpvSecCmPageCntAlertCheck_A 425076783 50 0 0
FpvSecCmProgCnt_A 425076783 50 0 0
FpvSecCmRdCnt_A 425076783 50 0 0
FpvSecCmRdFifoRptrCheck_A 425076783 50 0 0
FpvSecCmRdFifoWptrCheck_A 425076783 50 0 0
FpvSecCmRegWeOnehotCheck_A 425076783 50 0 0
FpvSecCmSeedCntAlertCheck_A 425076783 50 0 0
FpvSecCmTlLcGateFsm_A 425076783 50 0 0
FpvSecCmTlProgLcGateFsm_A 425076783 50 0 0
FpvSecCmWipeIdx_A 425076783 50 0 0
FpvSecCmWordCntAlertCheck_A 425076783 50 0 0
IntrErrO_A 425076783 424194965 0 0
IntrOpDoneKnownO_A 425076783 424194965 0 0
IntrProgEmptyKnownO_A 425076783 424194965 0 0
IntrProgLvlKnownO_A 425076783 424194965 0 0
IntrProgRdFullKnownO_A 425076783 424194965 0 0
IntrRdLvlKnownO_A 425076783 424194965 0 0
MemRspPayLoad_A 425076783 5514784 0 0
MemRspPayLoad_AKnownEnable 425076783 424194965 0 0
MemTlAReadyKnownO_A 425076783 424194965 0 0
MemTlDValidKnownO_A 425076783 424194965 0 0
PrimRspPayLoad_A 425076783 0 0 0
PrimRspPayLoad_AKnownEnable 425076783 424194965 0 0
PrimTlAReadyKnownO_A 425076783 424194965 0 0
PrimTlDValidKnownO_A 425076783 424194965 0 0
RspPayLoad_A 424850133 46041641 0 0
RspPayLoad_AKnownEnable 425076783 424194965 0 0
TdoEnIsOne_A 425076783 424194965 0 0
TdoKnown_A 425076783 424194965 0 0
TlAReadyKnownO_A 425076783 424194965 0 0
TlDValidKnownO_A 425076783 424194965 0 0
gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A 425076783 50 0 0
gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A 425076783 50 0 0
gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A 425076783 50 0 0
gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A 425076783 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A 425076783 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A 425076783 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A 425076783 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A 425076783 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A 425076783 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A 425076783 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A 425076783 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A 425076783 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A 425076783 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A 425076783 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A 425076783 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A 425076783 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A 425076783 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A 425076783 50 0 0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A 425076783 18 0 0


FifoDepthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

FlashAddrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 308037641 0 0
T1 1529 332 0 0
T2 286097 218485 0 0
T3 779003 762478 0 0
T4 262640 231576 0 0
T5 991 399 0 0
T9 3612 841 0 0
T14 822305 802144 0 0
T15 4013 1001 0 0
T16 46002 30582 0 0
T17 109814 94255 0 0

FlashAddrKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

FlashKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

FlashProgKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 187379117 0 0
T2 286097 193773 0 0
T3 779003 0 0 0
T4 262640 204070 0 0
T5 991 239 0 0
T9 3612 0 0 0
T10 0 5 0 0
T14 822305 0 0 0
T15 4013 0 0 0
T16 46002 0 0 0
T17 109814 85826 0 0
T19 0 396 0 0
T25 0 28256 0 0
T37 0 253960 0 0
T38 0 111231 0 0
T40 0 30622 0 0
T53 3213 0 0 0

FlashProgKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

FpvSecCmAddrCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

FpvSecCmArbFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

FpvSecCmLcCtrlFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

FpvSecCmLcCtrlRmaFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

FpvSecCmPageCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

FpvSecCmProgCnt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

FpvSecCmRdCnt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

FpvSecCmRdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

FpvSecCmRdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

FpvSecCmSeedCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

FpvSecCmTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

FpvSecCmTlProgLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

FpvSecCmWipeIdx_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

FpvSecCmWordCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

IntrErrO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

IntrOpDoneKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

IntrProgEmptyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

IntrProgLvlKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

IntrProgRdFullKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

IntrRdLvlKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

MemRspPayLoad_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 5514784 0 0
T2 286097 41562 0 0
T3 779003 16579 0 0
T4 262640 41208 0 0
T5 991 0 0 0
T9 3612 0 0 0
T14 822305 16288 0 0
T15 4013 19 0 0
T16 46002 16654 0 0
T17 109814 16507 0 0
T19 0 5 0 0
T37 0 40796 0 0
T38 0 16751 0 0
T53 3213 0 0 0

MemRspPayLoad_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

MemTlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

MemTlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

PrimRspPayLoad_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 0 0 0

PrimRspPayLoad_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

PrimTlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

PrimTlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

RspPayLoad_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424850133 46041641 0 0
T1 1529 106 0 0
T2 286097 141188 0 0
T3 779003 16996 0 0
T4 262640 126782 0 0
T5 991 239 0 0
T9 3612 506 0 0
T14 822305 20572 0 0
T15 4013 1060 0 0
T16 46002 17022 0 0
T17 109814 53183 0 0

RspPayLoad_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

TdoEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

TdoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 424194965 0 0
T1 1529 1283 0 0
T2 286097 286031 0 0
T3 779003 778873 0 0
T4 262640 262589 0 0
T5 991 915 0 0
T9 3612 2977 0 0
T14 822305 822155 0 0
T15 4013 3903 0 0
T16 46002 45933 0 0
T17 109814 109719 0 0

gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 50 0 0
T12 132684 10 0 0
T13 0 10 0 0
T36 0 10 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 10 0 0
T198 0 10 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 425076783 18 0 0
T12 132684 4 0 0
T13 0 5 0 0
T36 0 3 0 0
T46 63066 0 0 0
T72 3993 0 0 0
T74 3732 0 0 0
T156 3693 0 0 0
T161 3405 0 0 0
T195 1086 0 0 0
T197 0 4 0 0
T198 0 2 0 0
T199 834770 0 0 0
T200 51209 0 0 0
T201 4008 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%