Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : flash_ctrl_core_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.82 100.00 99.27 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl_core_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_core 99.82 100.00 99.27 100.00 100.00



Module Instance : tb.dut.u_reg_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.82 100.00 99.27 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.29 99.00 98.55 100.00 98.92 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.34 97.12 92.80 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_addr 100.00 100.00 100.00 100.00
u_alert_test_fatal_err 100.00 100.00
u_alert_test_fatal_prim_flash_alert 100.00 100.00
u_alert_test_fatal_std_err 100.00 100.00
u_alert_test_recov_err 100.00 100.00
u_alert_test_recov_prim_flash_alert 100.00 100.00
u_bank0_info0_page_cfg_0_ecc_en_0 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_0_en_0 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_0_erase_en_0 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_0_he_en_0 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_0_prog_en_0 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_0_rd_en_0 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_0_scramble_en_0 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_1_ecc_en_1 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_1_en_1 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_1_erase_en_1 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_1_he_en_1 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_1_prog_en_1 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_1_rd_en_1 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_1_scramble_en_1 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_2_ecc_en_2 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_2_en_2 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_2_erase_en_2 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_2_he_en_2 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_2_prog_en_2 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_2_rd_en_2 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_2_scramble_en_2 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_3_ecc_en_3 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_3_en_3 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_3_erase_en_3 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_3_he_en_3 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_3_prog_en_3 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_3_rd_en_3 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_3_scramble_en_3 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_4_ecc_en_4 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_4_en_4 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_4_erase_en_4 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_4_he_en_4 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_4_prog_en_4 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_4_rd_en_4 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_4_scramble_en_4 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_5_ecc_en_5 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_5_en_5 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_5_erase_en_5 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_5_he_en_5 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_5_prog_en_5 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_5_rd_en_5 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_5_scramble_en_5 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_6_ecc_en_6 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_6_en_6 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_6_erase_en_6 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_6_he_en_6 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_6_prog_en_6 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_6_rd_en_6 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_6_scramble_en_6 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_7_ecc_en_7 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_7_en_7 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_7_erase_en_7 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_7_he_en_7 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_7_prog_en_7 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_7_rd_en_7 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_7_scramble_en_7 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_8_ecc_en_8 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_8_en_8 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_8_erase_en_8 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_8_he_en_8 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_8_prog_en_8 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_8_rd_en_8 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_8_scramble_en_8 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_9_ecc_en_9 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_9_en_9 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_9_erase_en_9 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_9_he_en_9 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_9_prog_en_9 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_9_rd_en_9 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_9_scramble_en_9 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_0 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_1 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_2 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_3 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_4 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_5 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_6 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_7 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_8 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_9 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_ecc_en_0 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_en_0 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_erase_en_0 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_he_en_0 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_prog_en_0 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_rd_en_0 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_scramble_en_0 100.00 100.00 100.00 100.00
u_bank0_info1_regwen 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_0_ecc_en_0 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_0_en_0 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_0_erase_en_0 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_0_he_en_0 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_0_prog_en_0 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_0_rd_en_0 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_0_scramble_en_0 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_1_ecc_en_1 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_1_en_1 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_1_erase_en_1 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_1_he_en_1 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_1_prog_en_1 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_1_rd_en_1 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_1_scramble_en_1 100.00 100.00 100.00 100.00
u_bank0_info2_regwen_0 100.00 100.00 100.00 100.00
u_bank0_info2_regwen_1 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_0_ecc_en_0 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_0_en_0 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_0_erase_en_0 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_0_he_en_0 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_0_prog_en_0 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_0_rd_en_0 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_0_scramble_en_0 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_1_ecc_en_1 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_1_en_1 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_1_erase_en_1 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_1_he_en_1 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_1_prog_en_1 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_1_rd_en_1 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_1_scramble_en_1 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_2_ecc_en_2 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_2_en_2 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_2_erase_en_2 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_2_he_en_2 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_2_prog_en_2 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_2_rd_en_2 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_2_scramble_en_2 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_3_ecc_en_3 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_3_en_3 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_3_erase_en_3 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_3_he_en_3 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_3_prog_en_3 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_3_rd_en_3 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_3_scramble_en_3 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_4_ecc_en_4 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_4_en_4 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_4_erase_en_4 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_4_he_en_4 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_4_prog_en_4 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_4_rd_en_4 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_4_scramble_en_4 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_5_ecc_en_5 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_5_en_5 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_5_erase_en_5 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_5_he_en_5 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_5_prog_en_5 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_5_rd_en_5 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_5_scramble_en_5 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_6_ecc_en_6 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_6_en_6 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_6_erase_en_6 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_6_he_en_6 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_6_prog_en_6 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_6_rd_en_6 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_6_scramble_en_6 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_7_ecc_en_7 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_7_en_7 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_7_erase_en_7 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_7_he_en_7 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_7_prog_en_7 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_7_rd_en_7 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_7_scramble_en_7 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_8_ecc_en_8 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_8_en_8 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_8_erase_en_8 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_8_he_en_8 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_8_prog_en_8 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_8_rd_en_8 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_8_scramble_en_8 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_9_ecc_en_9 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_9_en_9 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_9_erase_en_9 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_9_he_en_9 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_9_prog_en_9 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_9_rd_en_9 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_9_scramble_en_9 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_0 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_1 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_2 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_3 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_4 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_5 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_6 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_7 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_8 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_9 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_ecc_en_0 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_en_0 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_erase_en_0 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_he_en_0 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_prog_en_0 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_rd_en_0 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_scramble_en_0 100.00 100.00 100.00 100.00
u_bank1_info1_regwen 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_0_ecc_en_0 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_0_en_0 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_0_erase_en_0 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_0_he_en_0 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_0_prog_en_0 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_0_rd_en_0 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_0_scramble_en_0 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_1_ecc_en_1 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_1_en_1 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_1_erase_en_1 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_1_he_en_1 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_1_prog_en_1 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_1_rd_en_1 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_1_scramble_en_1 100.00 100.00 100.00 100.00
u_bank1_info2_regwen_0 100.00 100.00 100.00 100.00
u_bank1_info2_regwen_1 100.00 100.00 100.00 100.00
u_bank_cfg_regwen 100.00 100.00 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_control_erase_sel 100.00 100.00 100.00 100.00
u_control_info_sel 100.00 100.00 100.00 100.00
u_control_num 100.00 100.00 100.00 100.00
u_control_op 100.00 100.00 100.00 100.00
u_control_partition_sel 100.00 100.00 100.00 100.00
u_control_prog_sel 100.00 100.00 100.00 100.00
u_control_start 100.00 100.00 100.00 100.00
u_ctrl_regwen 100.00 100.00
u_curr_fifo_lvl_prog 100.00 100.00
u_curr_fifo_lvl_rd 100.00 100.00
u_debug_state 100.00 100.00
u_default_region_ecc_en 100.00 100.00 100.00 100.00
u_default_region_erase_en 100.00 100.00 100.00 100.00
u_default_region_he_en 100.00 100.00 100.00 100.00
u_default_region_prog_en 100.00 100.00 100.00 100.00
u_default_region_rd_en 100.00 100.00 100.00 100.00
u_default_region_scramble_en 100.00 100.00 100.00 100.00
u_dis 100.00 100.00 100.00 100.00
u_ecc_single_err_addr_0 100.00 100.00 100.00 100.00
u_ecc_single_err_addr_1 100.00 100.00 100.00 100.00
u_ecc_single_err_cnt_ecc_single_err_cnt_0 100.00 100.00 100.00 100.00
u_ecc_single_err_cnt_ecc_single_err_cnt_1 100.00 100.00 100.00 100.00
u_erase_suspend 100.00 100.00 100.00 100.00
u_err_addr 100.00 100.00 100.00 100.00
u_err_code_macro_err 88.89 100.00 66.67 100.00
u_err_code_mp_err 100.00 100.00 100.00 100.00
u_err_code_op_err 100.00 100.00 100.00 100.00
u_err_code_prog_err 100.00 100.00 100.00 100.00
u_err_code_prog_type_err 100.00 100.00 100.00 100.00
u_err_code_prog_win_err 100.00 100.00 100.00 100.00
u_err_code_rd_err 100.00 100.00 100.00 100.00
u_err_code_update_err 88.89 100.00 66.67 100.00
u_exec 100.00 100.00 100.00 100.00
u_fault_status_arb_err 96.30 88.89 100.00 100.00
u_fault_status_host_gnt_err 96.30 88.89 100.00 100.00
u_fault_status_mp_err 96.30 88.89 100.00 100.00
u_fault_status_op_err 96.30 88.89 100.00 100.00
u_fault_status_phy_relbl_err 97.22 100.00 91.67 100.00
u_fault_status_phy_storage_err 97.22 100.00 91.67 100.00
u_fault_status_prog_err 96.30 88.89 100.00 100.00
u_fault_status_prog_type_err 96.30 88.89 100.00 100.00
u_fault_status_prog_win_err 96.30 88.89 100.00 100.00
u_fault_status_rd_err 96.30 88.89 100.00 100.00
u_fault_status_seed_err 96.30 88.89 100.00 100.00
u_fault_status_spurious_ack 96.30 88.89 100.00 100.00
u_fifo_lvl_prog 100.00 100.00 100.00 100.00
u_fifo_lvl_rd 100.00 100.00 100.00 100.00
u_fifo_rst 100.00 100.00 100.00 100.00
u_hw_info_cfg_override_ecc_dis 100.00 100.00 100.00 100.00
u_hw_info_cfg_override_scramble_dis 100.00 100.00 100.00 100.00
u_init 100.00 100.00 100.00 100.00
u_intr_enable_corr_err 100.00 100.00 100.00 100.00
u_intr_enable_op_done 100.00 100.00 100.00 100.00
u_intr_enable_prog_empty 100.00 100.00 100.00 100.00
u_intr_enable_prog_lvl 100.00 100.00 100.00 100.00
u_intr_enable_rd_full 100.00 100.00 100.00 100.00
u_intr_enable_rd_lvl 100.00 100.00 100.00 100.00
u_intr_state_corr_err 100.00 100.00 100.00 100.00
u_intr_state_op_done 100.00 100.00 100.00 100.00
u_intr_state_prog_empty 62.59 77.78 50.00 60.00
u_intr_state_prog_lvl 62.59 77.78 50.00 60.00
u_intr_state_rd_full 62.59 77.78 50.00 60.00
u_intr_state_rd_lvl 62.59 77.78 50.00 60.00
u_intr_test_corr_err 100.00 100.00
u_intr_test_op_done 100.00 100.00
u_intr_test_prog_empty 100.00 100.00
u_intr_test_prog_lvl 100.00 100.00
u_intr_test_rd_full 100.00 100.00
u_intr_test_rd_lvl 100.00 100.00
u_mp_bank_cfg_shadowed_erase_en_0 96.88 100.00 87.50 100.00 100.00
u_mp_bank_cfg_shadowed_erase_en_1 96.88 100.00 87.50 100.00 100.00
u_mp_region_0_base_0 100.00 100.00 100.00 100.00
u_mp_region_0_size_0 100.00 100.00 100.00 100.00
u_mp_region_1_base_1 100.00 100.00 100.00 100.00
u_mp_region_1_size_1 100.00 100.00 100.00 100.00
u_mp_region_2_base_2 100.00 100.00 100.00 100.00
u_mp_region_2_size_2 100.00 100.00 100.00 100.00
u_mp_region_3_base_3 100.00 100.00 100.00 100.00
u_mp_region_3_size_3 100.00 100.00 100.00 100.00
u_mp_region_4_base_4 100.00 100.00 100.00 100.00
u_mp_region_4_size_4 100.00 100.00 100.00 100.00
u_mp_region_5_base_5 100.00 100.00 100.00 100.00
u_mp_region_5_size_5 100.00 100.00 100.00 100.00
u_mp_region_6_base_6 100.00 100.00 100.00 100.00
u_mp_region_6_size_6 100.00 100.00 100.00 100.00
u_mp_region_7_base_7 100.00 100.00 100.00 100.00
u_mp_region_7_size_7 100.00 100.00 100.00 100.00
u_mp_region_cfg_0_ecc_en_0 100.00 100.00 100.00 100.00
u_mp_region_cfg_0_en_0 100.00 100.00 100.00 100.00
u_mp_region_cfg_0_erase_en_0 100.00 100.00 100.00 100.00
u_mp_region_cfg_0_he_en_0 100.00 100.00 100.00 100.00
u_mp_region_cfg_0_prog_en_0 100.00 100.00 100.00 100.00
u_mp_region_cfg_0_rd_en_0 100.00 100.00 100.00 100.00
u_mp_region_cfg_0_scramble_en_0 100.00 100.00 100.00 100.00
u_mp_region_cfg_1_ecc_en_1 100.00 100.00 100.00 100.00
u_mp_region_cfg_1_en_1 100.00 100.00 100.00 100.00
u_mp_region_cfg_1_erase_en_1 100.00 100.00 100.00 100.00
u_mp_region_cfg_1_he_en_1 100.00 100.00 100.00 100.00
u_mp_region_cfg_1_prog_en_1 100.00 100.00 100.00 100.00
u_mp_region_cfg_1_rd_en_1 100.00 100.00 100.00 100.00
u_mp_region_cfg_1_scramble_en_1 100.00 100.00 100.00 100.00
u_mp_region_cfg_2_ecc_en_2 100.00 100.00 100.00 100.00
u_mp_region_cfg_2_en_2 100.00 100.00 100.00 100.00
u_mp_region_cfg_2_erase_en_2 100.00 100.00 100.00 100.00
u_mp_region_cfg_2_he_en_2 100.00 100.00 100.00 100.00
u_mp_region_cfg_2_prog_en_2 100.00 100.00 100.00 100.00
u_mp_region_cfg_2_rd_en_2 100.00 100.00 100.00 100.00
u_mp_region_cfg_2_scramble_en_2 100.00 100.00 100.00 100.00
u_mp_region_cfg_3_ecc_en_3 100.00 100.00 100.00 100.00
u_mp_region_cfg_3_en_3 100.00 100.00 100.00 100.00
u_mp_region_cfg_3_erase_en_3 100.00 100.00 100.00 100.00
u_mp_region_cfg_3_he_en_3 100.00 100.00 100.00 100.00
u_mp_region_cfg_3_prog_en_3 100.00 100.00 100.00 100.00
u_mp_region_cfg_3_rd_en_3 100.00 100.00 100.00 100.00
u_mp_region_cfg_3_scramble_en_3 100.00 100.00 100.00 100.00
u_mp_region_cfg_4_ecc_en_4 100.00 100.00 100.00 100.00
u_mp_region_cfg_4_en_4 100.00 100.00 100.00 100.00
u_mp_region_cfg_4_erase_en_4 100.00 100.00 100.00 100.00
u_mp_region_cfg_4_he_en_4 100.00 100.00 100.00 100.00
u_mp_region_cfg_4_prog_en_4 100.00 100.00 100.00 100.00
u_mp_region_cfg_4_rd_en_4 100.00 100.00 100.00 100.00
u_mp_region_cfg_4_scramble_en_4 100.00 100.00 100.00 100.00
u_mp_region_cfg_5_ecc_en_5 100.00 100.00 100.00 100.00
u_mp_region_cfg_5_en_5 100.00 100.00 100.00 100.00
u_mp_region_cfg_5_erase_en_5 100.00 100.00 100.00 100.00
u_mp_region_cfg_5_he_en_5 100.00 100.00 100.00 100.00
u_mp_region_cfg_5_prog_en_5 100.00 100.00 100.00 100.00
u_mp_region_cfg_5_rd_en_5 100.00 100.00 100.00 100.00
u_mp_region_cfg_5_scramble_en_5 100.00 100.00 100.00 100.00
u_mp_region_cfg_6_ecc_en_6 100.00 100.00 100.00 100.00
u_mp_region_cfg_6_en_6 100.00 100.00 100.00 100.00
u_mp_region_cfg_6_erase_en_6 100.00 100.00 100.00 100.00
u_mp_region_cfg_6_he_en_6 100.00 100.00 100.00 100.00
u_mp_region_cfg_6_prog_en_6 100.00 100.00 100.00 100.00
u_mp_region_cfg_6_rd_en_6 100.00 100.00 100.00 100.00
u_mp_region_cfg_6_scramble_en_6 100.00 100.00 100.00 100.00
u_mp_region_cfg_7_ecc_en_7 100.00 100.00 100.00 100.00
u_mp_region_cfg_7_en_7 100.00 100.00 100.00 100.00
u_mp_region_cfg_7_erase_en_7 100.00 100.00 100.00 100.00
u_mp_region_cfg_7_he_en_7 100.00 100.00 100.00 100.00
u_mp_region_cfg_7_prog_en_7 100.00 100.00 100.00 100.00
u_mp_region_cfg_7_rd_en_7 100.00 100.00 100.00 100.00
u_mp_region_cfg_7_scramble_en_7 100.00 100.00 100.00 100.00
u_op_status_done 100.00 100.00 100.00 100.00
u_op_status_err 100.00 100.00 100.00 100.00
u_phy_alert_cfg_alert_ack 65.34 88.89 50.00 57.14
u_phy_alert_cfg_alert_trig 65.34 88.89 50.00 57.14
u_phy_status_init_wip 62.59 77.78 50.00 60.00
u_phy_status_prog_normal_avail 58.89 66.67 50.00 60.00
u_phy_status_prog_repair_avail 58.89 66.67 50.00 60.00
u_prim_reg_we_check 100.00 100.00 100.00
u_prog_type_en_normal 100.00 100.00 100.00 100.00
u_prog_type_en_repair 100.00 100.00 100.00 100.00
u_reg_if 98.49 98.72 95.24 100.00 100.00
u_region_cfg_regwen_0 100.00 100.00 100.00 100.00
u_region_cfg_regwen_1 100.00 100.00 100.00 100.00
u_region_cfg_regwen_2 100.00 100.00 100.00 100.00
u_region_cfg_regwen_3 100.00 100.00 100.00 100.00
u_region_cfg_regwen_4 100.00 100.00 100.00 100.00
u_region_cfg_regwen_5 100.00 100.00 100.00 100.00
u_region_cfg_regwen_6 100.00 100.00 100.00 100.00
u_region_cfg_regwen_7 100.00 100.00 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_scratch 100.00 100.00 100.00 100.00
u_socket 94.37 96.05 89.53 91.89 100.00
u_status_init_wip 62.59 77.78 50.00 60.00
u_status_initialized 62.59 77.78 50.00 60.00
u_status_prog_empty 100.00 100.00 100.00 100.00
u_status_prog_full 100.00 100.00 100.00 100.00
u_status_rd_empty 100.00 100.00 100.00 100.00
u_status_rd_full 100.00 100.00 100.00 100.00
u_std_fault_status_arb_fsm_err 96.30 88.89 100.00 100.00
u_std_fault_status_ctrl_cnt_err 96.30 88.89 100.00 100.00
u_std_fault_status_fifo_err 96.30 88.89 100.00 100.00
u_std_fault_status_lcmgr_err 96.30 88.89 100.00 100.00
u_std_fault_status_lcmgr_intg_err 96.30 88.89 100.00 100.00
u_std_fault_status_phy_fsm_err 96.30 88.89 100.00 100.00
u_std_fault_status_prog_intg_err 96.30 88.89 100.00 100.00
u_std_fault_status_reg_intg_err 96.30 88.89 100.00 100.00
u_std_fault_status_storage_err 62.59 77.78 50.00 60.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl_core_reg_top
Line No.TotalCoveredPercent
TOTAL11551155100.00
ALWAYS7744100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
ALWAYS13633100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN135211100.00
CONT_ASSIGN136711100.00
CONT_ASSIGN138311100.00
CONT_ASSIGN139911100.00
CONT_ASSIGN141511100.00
CONT_ASSIGN143111100.00
CONT_ASSIGN144711100.00
CONT_ASSIGN145311100.00
CONT_ASSIGN146811100.00
CONT_ASSIGN148411100.00
CONT_ASSIGN150011100.00
CONT_ASSIGN151611100.00
CONT_ASSIGN153211100.00
CONT_ASSIGN163811100.00
CONT_ASSIGN183211100.00
CONT_ASSIGN186311100.00
CONT_ASSIGN218311100.00
CONT_ASSIGN237811100.00
CONT_ASSIGN257311100.00
CONT_ASSIGN276811100.00
CONT_ASSIGN296311100.00
CONT_ASSIGN315811100.00
CONT_ASSIGN335311100.00
CONT_ASSIGN354811100.00
CONT_ASSIGN374311100.00
CONT_ASSIGN380311100.00
CONT_ASSIGN386311100.00
CONT_ASSIGN392311100.00
CONT_ASSIGN398311100.00
CONT_ASSIGN404311100.00
CONT_ASSIGN410311100.00
CONT_ASSIGN416311100.00
CONT_ASSIGN467711100.00
CONT_ASSIGN487211100.00
CONT_ASSIGN506711100.00
CONT_ASSIGN526211100.00
CONT_ASSIGN545711100.00
CONT_ASSIGN565211100.00
CONT_ASSIGN584711100.00
CONT_ASSIGN604211100.00
CONT_ASSIGN623711100.00
CONT_ASSIGN643211100.00
CONT_ASSIGN665611100.00
CONT_ASSIGN690911100.00
CONT_ASSIGN710411100.00
CONT_ASSIGN758911100.00
CONT_ASSIGN778411100.00
CONT_ASSIGN797911100.00
CONT_ASSIGN817411100.00
CONT_ASSIGN836911100.00
CONT_ASSIGN856411100.00
CONT_ASSIGN875911100.00
CONT_ASSIGN895411100.00
CONT_ASSIGN914911100.00
CONT_ASSIGN934411100.00
CONT_ASSIGN956811100.00
CONT_ASSIGN982111100.00
CONT_ASSIGN1001611100.00
CONT_ASSIGN1029511100.00
ALWAYS11823109109100.00
CONT_ASSIGN1193411100.00
ALWAYS1193811100.00
CONT_ASSIGN1205011100.00
CONT_ASSIGN1205211100.00
CONT_ASSIGN1205411100.00
CONT_ASSIGN1205511100.00
CONT_ASSIGN1205711100.00
CONT_ASSIGN1205911100.00
CONT_ASSIGN1206111100.00
CONT_ASSIGN1206311100.00
CONT_ASSIGN1206511100.00
CONT_ASSIGN1206711100.00
CONT_ASSIGN1206811100.00
CONT_ASSIGN1207011100.00
CONT_ASSIGN1207211100.00
CONT_ASSIGN1207411100.00
CONT_ASSIGN1207611100.00
CONT_ASSIGN1207811100.00
CONT_ASSIGN1208011100.00
CONT_ASSIGN1208111100.00
CONT_ASSIGN1208311100.00
CONT_ASSIGN1208511100.00
CONT_ASSIGN1208711100.00
CONT_ASSIGN1208911100.00
CONT_ASSIGN1209111100.00
CONT_ASSIGN1209211100.00
CONT_ASSIGN1209411100.00
CONT_ASSIGN1209511100.00
CONT_ASSIGN1209711100.00
CONT_ASSIGN1209811100.00
CONT_ASSIGN1210011100.00
CONT_ASSIGN1210111100.00
CONT_ASSIGN1210211100.00
CONT_ASSIGN1210411100.00
CONT_ASSIGN1210611100.00
CONT_ASSIGN1210811100.00
CONT_ASSIGN1211011100.00
CONT_ASSIGN1211211100.00
CONT_ASSIGN1211411100.00
CONT_ASSIGN1211611100.00
CONT_ASSIGN1211711100.00
CONT_ASSIGN1211911100.00
CONT_ASSIGN1212011100.00
CONT_ASSIGN1212211100.00
CONT_ASSIGN1212411100.00
CONT_ASSIGN1212511100.00
CONT_ASSIGN1212711100.00
CONT_ASSIGN1212811100.00
CONT_ASSIGN1213011100.00
CONT_ASSIGN1213111100.00
CONT_ASSIGN1213311100.00
CONT_ASSIGN1213411100.00
CONT_ASSIGN1213611100.00
CONT_ASSIGN1213711100.00
CONT_ASSIGN1213911100.00
CONT_ASSIGN1214011100.00
CONT_ASSIGN1214211100.00
CONT_ASSIGN1214311100.00
CONT_ASSIGN1214511100.00
CONT_ASSIGN1214611100.00
CONT_ASSIGN1214811100.00
CONT_ASSIGN1214911100.00
CONT_ASSIGN1215111100.00
CONT_ASSIGN1215211100.00
CONT_ASSIGN1215411100.00
CONT_ASSIGN1215611100.00
CONT_ASSIGN1215811100.00
CONT_ASSIGN1216011100.00
CONT_ASSIGN1216211100.00
CONT_ASSIGN1216411100.00
CONT_ASSIGN1216611100.00
CONT_ASSIGN1216711100.00
CONT_ASSIGN1216911100.00
CONT_ASSIGN1217111100.00
CONT_ASSIGN1217311100.00
CONT_ASSIGN1217511100.00
CONT_ASSIGN1217711100.00
CONT_ASSIGN1217911100.00
CONT_ASSIGN1218111100.00
CONT_ASSIGN1218211100.00
CONT_ASSIGN1218411100.00
CONT_ASSIGN1218611100.00
CONT_ASSIGN1218811100.00
CONT_ASSIGN1219011100.00
CONT_ASSIGN1219211100.00
CONT_ASSIGN1219411100.00
CONT_ASSIGN1219611100.00
CONT_ASSIGN1219711100.00
CONT_ASSIGN1219911100.00
CONT_ASSIGN1220111100.00
CONT_ASSIGN1220311100.00
CONT_ASSIGN1220511100.00
CONT_ASSIGN1220711100.00
CONT_ASSIGN1220911100.00
CONT_ASSIGN1221111100.00
CONT_ASSIGN1221211100.00
CONT_ASSIGN1221411100.00
CONT_ASSIGN1221611100.00
CONT_ASSIGN1221811100.00
CONT_ASSIGN1222011100.00
CONT_ASSIGN1222211100.00
CONT_ASSIGN1222411100.00
CONT_ASSIGN1222611100.00
CONT_ASSIGN1222711100.00
CONT_ASSIGN1222911100.00
CONT_ASSIGN1223111100.00
CONT_ASSIGN1223311100.00
CONT_ASSIGN1223511100.00
CONT_ASSIGN1223711100.00
CONT_ASSIGN1223911100.00
CONT_ASSIGN1224111100.00
CONT_ASSIGN1224211100.00
CONT_ASSIGN1224411100.00
CONT_ASSIGN1224611100.00
CONT_ASSIGN1224811100.00
CONT_ASSIGN1225011100.00
CONT_ASSIGN1225211100.00
CONT_ASSIGN1225411100.00
CONT_ASSIGN1225611100.00
CONT_ASSIGN1225711100.00
CONT_ASSIGN1225911100.00
CONT_ASSIGN1226111100.00
CONT_ASSIGN1226311100.00
CONT_ASSIGN1226511100.00
CONT_ASSIGN1226711100.00
CONT_ASSIGN1226911100.00
CONT_ASSIGN1227111100.00
CONT_ASSIGN1227211100.00
CONT_ASSIGN1227411100.00
CONT_ASSIGN1227611100.00
CONT_ASSIGN1227711100.00
CONT_ASSIGN1227911100.00
CONT_ASSIGN1228111100.00
CONT_ASSIGN1228211100.00
CONT_ASSIGN1228411100.00
CONT_ASSIGN1228611100.00
CONT_ASSIGN1228711100.00
CONT_ASSIGN1228911100.00
CONT_ASSIGN1229111100.00
CONT_ASSIGN1229211100.00
CONT_ASSIGN1229411100.00
CONT_ASSIGN1229611100.00
CONT_ASSIGN1229711100.00
CONT_ASSIGN1229911100.00
CONT_ASSIGN1230111100.00
CONT_ASSIGN1230211100.00
CONT_ASSIGN1230411100.00
CONT_ASSIGN1230611100.00
CONT_ASSIGN1230711100.00
CONT_ASSIGN1230911100.00
CONT_ASSIGN1231111100.00
CONT_ASSIGN1231211100.00
CONT_ASSIGN1231411100.00
CONT_ASSIGN1231611100.00
CONT_ASSIGN1231811100.00
CONT_ASSIGN1232011100.00
CONT_ASSIGN1232211100.00
CONT_ASSIGN1232411100.00
CONT_ASSIGN1232511100.00
CONT_ASSIGN1232711100.00
CONT_ASSIGN1232811100.00
CONT_ASSIGN1233011100.00
CONT_ASSIGN1233111100.00
CONT_ASSIGN1233311100.00
CONT_ASSIGN1233411100.00
CONT_ASSIGN1233611100.00
CONT_ASSIGN1233711100.00
CONT_ASSIGN1233911100.00
CONT_ASSIGN1234011100.00
CONT_ASSIGN1234211100.00
CONT_ASSIGN1234311100.00
CONT_ASSIGN1234511100.00
CONT_ASSIGN1234611100.00
CONT_ASSIGN1234811100.00
CONT_ASSIGN1234911100.00
CONT_ASSIGN1235111100.00
CONT_ASSIGN1235211100.00
CONT_ASSIGN1235411100.00
CONT_ASSIGN1235511100.00
CONT_ASSIGN1235711100.00
CONT_ASSIGN1235911100.00
CONT_ASSIGN1236111100.00
CONT_ASSIGN1236311100.00
CONT_ASSIGN1236511100.00
CONT_ASSIGN1236711100.00
CONT_ASSIGN1236911100.00
CONT_ASSIGN1237011100.00
CONT_ASSIGN1237211100.00
CONT_ASSIGN1237411100.00
CONT_ASSIGN1237611100.00
CONT_ASSIGN1237811100.00
CONT_ASSIGN1238011100.00
CONT_ASSIGN1238211100.00
CONT_ASSIGN1238411100.00
CONT_ASSIGN1238511100.00
CONT_ASSIGN1238711100.00
CONT_ASSIGN1238911100.00
CONT_ASSIGN1239111100.00
CONT_ASSIGN1239311100.00
CONT_ASSIGN1239511100.00
CONT_ASSIGN1239711100.00
CONT_ASSIGN1239911100.00
CONT_ASSIGN1240011100.00
CONT_ASSIGN1240211100.00
CONT_ASSIGN1240411100.00
CONT_ASSIGN1240611100.00
CONT_ASSIGN1240811100.00
CONT_ASSIGN1241011100.00
CONT_ASSIGN1241211100.00
CONT_ASSIGN1241411100.00
CONT_ASSIGN1241511100.00
CONT_ASSIGN1241711100.00
CONT_ASSIGN1241911100.00
CONT_ASSIGN1242111100.00
CONT_ASSIGN1242311100.00
CONT_ASSIGN1242511100.00
CONT_ASSIGN1242711100.00
CONT_ASSIGN1242911100.00
CONT_ASSIGN1243011100.00
CONT_ASSIGN1243211100.00
CONT_ASSIGN1243411100.00
CONT_ASSIGN1243611100.00
CONT_ASSIGN1243811100.00
CONT_ASSIGN1244011100.00
CONT_ASSIGN1244211100.00
CONT_ASSIGN1244411100.00
CONT_ASSIGN1244511100.00
CONT_ASSIGN1244711100.00
CONT_ASSIGN1244911100.00
CONT_ASSIGN1245111100.00
CONT_ASSIGN1245311100.00
CONT_ASSIGN1245511100.00
CONT_ASSIGN1245711100.00
CONT_ASSIGN1245911100.00
CONT_ASSIGN1246011100.00
CONT_ASSIGN1246211100.00
CONT_ASSIGN1246411100.00
CONT_ASSIGN1246611100.00
CONT_ASSIGN1246811100.00
CONT_ASSIGN1247011100.00
CONT_ASSIGN1247211100.00
CONT_ASSIGN1247411100.00
CONT_ASSIGN1247511100.00
CONT_ASSIGN1247711100.00
CONT_ASSIGN1247911100.00
CONT_ASSIGN1248111100.00
CONT_ASSIGN1248311100.00
CONT_ASSIGN1248511100.00
CONT_ASSIGN1248711100.00
CONT_ASSIGN1248911100.00
CONT_ASSIGN1249011100.00
CONT_ASSIGN1249211100.00
CONT_ASSIGN1249411100.00
CONT_ASSIGN1249611100.00
CONT_ASSIGN1249811100.00
CONT_ASSIGN1250011100.00
CONT_ASSIGN1250211100.00
CONT_ASSIGN1250411100.00
CONT_ASSIGN1250511100.00
CONT_ASSIGN1250711100.00
CONT_ASSIGN1250811100.00
CONT_ASSIGN1251011100.00
CONT_ASSIGN1251211100.00
CONT_ASSIGN1251411100.00
CONT_ASSIGN1251611100.00
CONT_ASSIGN1251811100.00
CONT_ASSIGN1252011100.00
CONT_ASSIGN1252211100.00
CONT_ASSIGN1252311100.00
CONT_ASSIGN1252511100.00
CONT_ASSIGN1252611100.00
CONT_ASSIGN1252811100.00
CONT_ASSIGN1252911100.00
CONT_ASSIGN1253111100.00
CONT_ASSIGN1253311100.00
CONT_ASSIGN1253511100.00
CONT_ASSIGN1253711100.00
CONT_ASSIGN1253911100.00
CONT_ASSIGN1254111100.00
CONT_ASSIGN1254311100.00
CONT_ASSIGN1254411100.00
CONT_ASSIGN1254611100.00
CONT_ASSIGN1254811100.00
CONT_ASSIGN1255011100.00
CONT_ASSIGN1255211100.00
CONT_ASSIGN1255411100.00
CONT_ASSIGN1255611100.00
CONT_ASSIGN1255811100.00
CONT_ASSIGN1255911100.00
CONT_ASSIGN1256111100.00
CONT_ASSIGN1256211100.00
CONT_ASSIGN1256411100.00
CONT_ASSIGN1256511100.00
CONT_ASSIGN1256711100.00
CONT_ASSIGN1256811100.00
CONT_ASSIGN1257011100.00
CONT_ASSIGN1257111100.00
CONT_ASSIGN1257311100.00
CONT_ASSIGN1257411100.00
CONT_ASSIGN1257611100.00
CONT_ASSIGN1257711100.00
CONT_ASSIGN1257911100.00
CONT_ASSIGN1258011100.00
CONT_ASSIGN1258211100.00
CONT_ASSIGN1258311100.00
CONT_ASSIGN1258511100.00
CONT_ASSIGN1258611100.00
CONT_ASSIGN1258811100.00
CONT_ASSIGN1258911100.00
CONT_ASSIGN1259111100.00
CONT_ASSIGN1259311100.00
CONT_ASSIGN1259511100.00
CONT_ASSIGN1259711100.00
CONT_ASSIGN1259911100.00
CONT_ASSIGN1260111100.00
CONT_ASSIGN1260311100.00
CONT_ASSIGN1260411100.00
CONT_ASSIGN1260611100.00
CONT_ASSIGN1260811100.00
CONT_ASSIGN1261011100.00
CONT_ASSIGN1261211100.00
CONT_ASSIGN1261411100.00
CONT_ASSIGN1261611100.00
CONT_ASSIGN1261811100.00
CONT_ASSIGN1261911100.00
CONT_ASSIGN1262111100.00
CONT_ASSIGN1262311100.00
CONT_ASSIGN1262511100.00
CONT_ASSIGN1262711100.00
CONT_ASSIGN1262911100.00
CONT_ASSIGN1263111100.00
CONT_ASSIGN1263311100.00
CONT_ASSIGN1263411100.00
CONT_ASSIGN1263611100.00
CONT_ASSIGN1263811100.00
CONT_ASSIGN1264011100.00
CONT_ASSIGN1264211100.00
CONT_ASSIGN1264411100.00
CONT_ASSIGN1264611100.00
CONT_ASSIGN1264811100.00
CONT_ASSIGN1264911100.00
CONT_ASSIGN1265111100.00
CONT_ASSIGN1265311100.00
CONT_ASSIGN1265511100.00
CONT_ASSIGN1265711100.00
CONT_ASSIGN1265911100.00
CONT_ASSIGN1266111100.00
CONT_ASSIGN1266311100.00
CONT_ASSIGN1266411100.00
CONT_ASSIGN1266611100.00
CONT_ASSIGN1266811100.00
CONT_ASSIGN1267011100.00
CONT_ASSIGN1267211100.00
CONT_ASSIGN1267411100.00
CONT_ASSIGN1267611100.00
CONT_ASSIGN1267811100.00
CONT_ASSIGN1267911100.00
CONT_ASSIGN1268111100.00
CONT_ASSIGN1268311100.00
CONT_ASSIGN1268511100.00
CONT_ASSIGN1268711100.00
CONT_ASSIGN1268911100.00
CONT_ASSIGN1269111100.00
CONT_ASSIGN1269311100.00
CONT_ASSIGN1269411100.00
CONT_ASSIGN1269611100.00
CONT_ASSIGN1269811100.00
CONT_ASSIGN1270011100.00
CONT_ASSIGN1270211100.00
CONT_ASSIGN1270411100.00
CONT_ASSIGN1270611100.00
CONT_ASSIGN1270811100.00
CONT_ASSIGN1270911100.00
CONT_ASSIGN1271111100.00
CONT_ASSIGN1271311100.00
CONT_ASSIGN1271511100.00
CONT_ASSIGN1271711100.00
CONT_ASSIGN1271911100.00
CONT_ASSIGN1272111100.00
CONT_ASSIGN1272311100.00
CONT_ASSIGN1272411100.00
CONT_ASSIGN1272611100.00
CONT_ASSIGN1272811100.00
CONT_ASSIGN1273011100.00
CONT_ASSIGN1273211100.00
CONT_ASSIGN1273411100.00
CONT_ASSIGN1273611100.00
CONT_ASSIGN1273811100.00
CONT_ASSIGN1273911100.00
CONT_ASSIGN1274111100.00
CONT_ASSIGN1274211100.00
CONT_ASSIGN1274411100.00
CONT_ASSIGN1274611100.00
CONT_ASSIGN1274811100.00
CONT_ASSIGN1275011100.00
CONT_ASSIGN1275211100.00
CONT_ASSIGN1275411100.00
CONT_ASSIGN1275611100.00
CONT_ASSIGN1275711100.00
CONT_ASSIGN1275911100.00
CONT_ASSIGN1276011100.00
CONT_ASSIGN1276211100.00
CONT_ASSIGN1276311100.00
CONT_ASSIGN1276511100.00
CONT_ASSIGN1276711100.00
CONT_ASSIGN1276911100.00
CONT_ASSIGN1277111100.00
CONT_ASSIGN1277311100.00
CONT_ASSIGN1277511100.00
CONT_ASSIGN1277711100.00
CONT_ASSIGN1277811100.00
CONT_ASSIGN1278011100.00
CONT_ASSIGN1278211100.00
CONT_ASSIGN1278411100.00
CONT_ASSIGN1278611100.00
CONT_ASSIGN1278811100.00
CONT_ASSIGN1279011100.00
CONT_ASSIGN1279211100.00
CONT_ASSIGN1279311100.00
CONT_ASSIGN1279511100.00
CONT_ASSIGN1279711100.00
CONT_ASSIGN1279811100.00
CONT_ASSIGN1280011100.00
CONT_ASSIGN1280111100.00
CONT_ASSIGN1280211100.00
CONT_ASSIGN1280411100.00
CONT_ASSIGN1280611100.00
CONT_ASSIGN1280711100.00
CONT_ASSIGN1280911100.00
CONT_ASSIGN1281111100.00
CONT_ASSIGN1281211100.00
CONT_ASSIGN1281311100.00
CONT_ASSIGN1281511100.00
CONT_ASSIGN1281711100.00
CONT_ASSIGN1281911100.00
CONT_ASSIGN1282111100.00
CONT_ASSIGN1282311100.00
CONT_ASSIGN1282511100.00
CONT_ASSIGN1282711100.00
CONT_ASSIGN1282911100.00
CONT_ASSIGN1283011100.00
CONT_ASSIGN1283211100.00
CONT_ASSIGN1283411100.00
CONT_ASSIGN1283511100.00
CONT_ASSIGN1283711100.00
CONT_ASSIGN1283911100.00
CONT_ASSIGN1284011100.00
CONT_ASSIGN1284211100.00
CONT_ASSIGN1284411100.00
CONT_ASSIGN1284511100.00
CONT_ASSIGN1284711100.00
CONT_ASSIGN1284811100.00
CONT_ASSIGN1285011100.00
CONT_ASSIGN1285211100.00
CONT_ASSIGN1285311100.00
CONT_ASSIGN1285511100.00
CONT_ASSIGN1285611100.00
ALWAYS12860109109100.00
ALWAYS12973393393100.00
ALWAYS1370133100.00
ALWAYS1370933100.00
CONT_ASSIGN1371711100.00
CONT_ASSIGN1372011100.00
CONT_ASSIGN1372411100.00
CONT_ASSIGN1373011100.00
CONT_ASSIGN1373811100.00
CONT_ASSIGN1373911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl_core_reg_top.sv' or '../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl_core_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
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MISSING_ELSE
86 1 1
104 1 1
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136 1 1
143 1 1
144 1 1
MISSING_ELSE
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13496 1 1
13497 1 1
13498 1 1
13499 1 1
13503 1 1
13504 1 1
13505 1 1
13506 1 1
13507 1 1
13508 1 1
13509 1 1
13513 1 1
13514 1 1
13515 1 1
13516 1 1
13517 1 1
13518 1 1
13519 1 1
13523 1 1
13524 1 1
13525 1 1
13526 1 1
13527 1 1
13528 1 1
13529 1 1
13533 1 1
13537 1 1
13538 1 1
13539 1 1
13540 1 1
13541 1 1
13542 1 1
13543 1 1
13547 1 1
13551 1 1
13555 1 1
13556 1 1
13557 1 1
13558 1 1
13559 1 1
13560 1 1
13561 1 1
13565 1 1
13566 1 1
13567 1 1
13568 1 1
13569 1 1
13570 1 1
13571 1 1
13575 1 1
13576 1 1
13580 1 1
13584 1 1
13585 1 1
13589 1 1
13590 1 1
13594 1 1
13595 1 1
13596 1 1
13597 1 1
13598 1 1
13599 1 1
13603 1 1
13607 1 1
13608 1 1
13609 1 1
13610 1 1
13611 1 1
13612 1 1
13613 1 1
13614 1 1
13618 1 1
13619 1 1
13620 1 1
13621 1 1
13622 1 1
13623 1 1
13624 1 1
13625 1 1
13626 1 1
13630 1 1
13631 1 1
13632 1 1
13633 1 1
13634 1 1
13635 1 1
13636 1 1
13637 1 1
13638 1 1
13639 1 1
13640 1 1
13641 1 1
13645 1 1
13649 1 1
13650 1 1
13654 1 1
13658 1 1
13662 1 1
13663 1 1
13667 1 1
13668 1 1
13669 1 1
13673 1 1
13677 1 1
13678 1 1
13682 1 1
13686 1 1
13687 1 1
13701 1 1
13702 1 1
13704 1 1
13709 1 1
13710 1 1
13712 1 1
13717 1 1
13720 1 1
13724 1 1
13730 1 1
13738 1 1
13739 1 1


Cond Coverage for Module : flash_ctrl_core_reg_top
TotalCoveredPercent
Conditions1228121999.27
Logical1228121999.27
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
67-1193899.59
11938-1225799.77
12272-1371798.02

Branch Coverage for Module : flash_ctrl_core_reg_top
Line No.TotalCoveredPercent
Branches 123 123 100.00
TERNARY 11934 2 2 100.00
IF 77 3 3 100.00
TERNARY 136 3 3 100.00
IF 143 2 2 100.00
CASE 12974 109 109 100.00
IF 13701 2 2 100.00
IF 13709 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl_core_reg_top.sv' or '../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl_core_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 11934 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 77 if ((!rst_ni)) -2-: 79 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T12,T13,T36
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 136 ((tl_i.a_address[(AW - 1):0] inside {[432:435]})) ? -2-: 136 ((tl_i.a_address[(AW - 1):0] inside {[436:439]})) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T4,T9
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 143 if (intg_err)

Branches:
-1-StatusTests
1 Covered T63,T65,T192
0 Covered T1,T2,T3


LineNo. Expression -1-: 12974 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T2,T3,T4
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T2,T3,T4
addr_hit[10] Covered T1,T2,T3
addr_hit[11] Covered T1,T2,T3
addr_hit[12] Covered T1,T2,T3
addr_hit[13] Covered T1,T2,T3
addr_hit[14] Covered T1,T2,T3
addr_hit[15] Covered T2,T3,T4
addr_hit[16] Covered T2,T3,T4
addr_hit[17] Covered T1,T2,T3
addr_hit[18] Covered T1,T2,T3
addr_hit[19] Covered T2,T3,T4
addr_hit[20] Covered T1,T2,T3
addr_hit[21] Covered T1,T2,T3
addr_hit[22] Covered T1,T2,T3
addr_hit[23] Covered T1,T2,T3
addr_hit[24] Covered T1,T2,T3
addr_hit[25] Covered T1,T2,T3
addr_hit[26] Covered T1,T2,T3
addr_hit[27] Covered T1,T2,T3
addr_hit[28] Covered T1,T2,T3
addr_hit[29] Covered T1,T2,T3
addr_hit[30] Covered T1,T2,T3
addr_hit[31] Covered T1,T2,T3
addr_hit[32] Covered T1,T2,T3
addr_hit[33] Covered T1,T2,T3
addr_hit[34] Covered T1,T2,T3
addr_hit[35] Covered T1,T2,T3
addr_hit[36] Covered T1,T2,T3
addr_hit[37] Covered T2,T3,T4
addr_hit[38] Covered T2,T3,T4
addr_hit[39] Covered T2,T3,T4
addr_hit[40] Covered T1,T2,T3
addr_hit[41] Covered T1,T2,T3
addr_hit[42] Covered T1,T2,T3
addr_hit[43] Covered T2,T3,T4
addr_hit[44] Covered T2,T3,T4
addr_hit[45] Covered T1,T2,T3
addr_hit[46] Covered T1,T2,T3
addr_hit[47] Covered T1,T2,T3
addr_hit[48] Covered T1,T2,T3
addr_hit[49] Covered T1,T2,T3
addr_hit[50] Covered T1,T2,T3
addr_hit[51] Covered T1,T2,T3
addr_hit[52] Covered T1,T2,T3
addr_hit[53] Covered T1,T2,T3
addr_hit[54] Covered T1,T2,T3
addr_hit[55] Covered T1,T2,T3
addr_hit[56] Covered T1,T2,T3
addr_hit[57] Covered T2,T3,T4
addr_hit[58] Covered T1,T2,T3
addr_hit[59] Covered T1,T2,T3
addr_hit[60] Covered T1,T2,T3
addr_hit[61] Covered T1,T2,T3
addr_hit[62] Covered T1,T2,T3
addr_hit[63] Covered T1,T2,T3
addr_hit[64] Covered T2,T3,T4
addr_hit[65] Covered T1,T2,T3
addr_hit[66] Covered T2,T3,T4
addr_hit[67] Covered T1,T2,T3
addr_hit[68] Covered T1,T2,T3
addr_hit[69] Covered T2,T3,T4
addr_hit[70] Covered T2,T3,T4
addr_hit[71] Covered T2,T3,T4
addr_hit[72] Covered T1,T2,T3
addr_hit[73] Covered T1,T2,T3
addr_hit[74] Covered T1,T2,T3
addr_hit[75] Covered T1,T2,T3
addr_hit[76] Covered T1,T2,T3
addr_hit[77] Covered T1,T2,T3
addr_hit[78] Covered T1,T2,T3
addr_hit[79] Covered T1,T2,T3
addr_hit[80] Covered T1,T2,T3
addr_hit[81] Covered T1,T2,T3
addr_hit[82] Covered T1,T2,T3
addr_hit[83] Covered T2,T3,T4
addr_hit[84] Covered T1,T2,T3
addr_hit[85] Covered T2,T3,T4
addr_hit[86] Covered T1,T2,T3
addr_hit[87] Covered T1,T2,T3
addr_hit[88] Covered T1,T2,T3
addr_hit[89] Covered T1,T2,T3
addr_hit[90] Covered T1,T2,T3
addr_hit[91] Covered T1,T2,T3
addr_hit[92] Covered T2,T3,T4
addr_hit[93] Covered T1,T2,T3
addr_hit[94] Covered T1,T2,T3
addr_hit[95] Covered T2,T3,T4
addr_hit[96] Covered T1,T2,T3
addr_hit[97] Covered T1,T2,T3
addr_hit[98] Covered T2,T3,T4
addr_hit[99] Covered T2,T3,T4
addr_hit[100] Covered T2,T3,T4
addr_hit[101] Covered T2,T3,T4
addr_hit[102] Covered T1,T2,T3
addr_hit[103] Covered T1,T2,T3
addr_hit[104] Covered T1,T2,T3
addr_hit[105] Covered T2,T3,T4
addr_hit[106] Covered T1,T2,T3
addr_hit[107] Covered T2,T3,T4
default Covered T1,T2,T3


LineNo. Expression -1-: 13701 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 13709 if ((!rst_shadowed_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : flash_ctrl_core_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 428225956 29209136 0 0
reAfterRv 428225956 29209115 0 0
rePulse 428225956 26819080 0 0
wePulse 428225956 2390035 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 428225956 29209136 0 0
T1 1529 106 0 0
T2 286097 124884 0 0
T3 779003 6324 0 0
T4 262640 116268 0 0
T5 991 233 0 0
T9 3612 506 0 0
T14 822305 7516 0 0
T15 4013 860 0 0
T16 46002 12122 0 0
T17 109814 48877 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 428225956 29209115 0 0
T1 1529 106 0 0
T2 286097 124884 0 0
T3 779003 6324 0 0
T4 262640 116268 0 0
T5 991 233 0 0
T9 3612 506 0 0
T14 822305 7516 0 0
T15 4013 860 0 0
T16 46002 12122 0 0
T17 109814 48877 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 428225956 26819080 0 0
T1 1529 59 0 0
T2 286097 116220 0 0
T3 779003 3609 0 0
T4 262640 109976 0 0
T5 991 180 0 0
T9 3612 497 0 0
T14 822305 4205 0 0
T15 4013 615 0 0
T16 46002 9373 0 0
T17 109814 46167 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 428225956 2390035 0 0
T1 1529 47 0 0
T2 286097 8664 0 0
T3 779003 2715 0 0
T4 262640 6292 0 0
T5 991 53 0 0
T9 3612 9 0 0
T14 822305 3311 0 0
T15 4013 245 0 0
T16 46002 2749 0 0
T17 109814 2710 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%