Unified Coverage Report :: Module :: tlul_data_integ_enc

Module : tlul_data_integ_enc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_enc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc
tb.dut.u_flash_hw_if.u_bus_intg
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc
tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_instr
tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_data
tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_instr
tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_data
tb.dut.u_flash_ctrl_rd.u_bus_intg
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc
tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_instr
tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_data
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_bus_intg
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_bus_intg

---

Module Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_intg_gen

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_gen	100.00	100.00

---

Module Instance : tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.00	80.00					100.00	u_rsp_intg_gen

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_gen	100.00	100.00

---

Module Instance : tb.dut.u_flash_hw_if.u_bus_intg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.75	100.00	92.71		92.11	98.94	100.00	u_flash_hw_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_gen	100.00	100.00

---

Module Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_intg_gen

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_gen	100.00	100.00

---

Module Instance : tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_instr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.89	100.00	65.22			85.71	84.62	u_to_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_gen	0.00	0.00

---

Module Instance : tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.89	100.00	65.22			85.71	84.62	u_to_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_gen	0.00	0.00

---

Module Instance : tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_instr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	77.31			96.55	100.00	u_to_rd_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_gen	0.00	0.00

---

Module Instance : tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	77.31			96.55	100.00	u_to_rd_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_gen	0.00	0.00

---

Module Instance : tb.dut.u_flash_ctrl_rd.u_bus_intg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.29	100.00	93.94		100.00	95.24		u_flash_ctrl_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_gen	0.00	0.00

---

Module Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_intg_gen

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_gen	100.00	100.00

---

Module Instance : tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_instr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	100.00	85.00			96.55	100.00	u_tl_adapter_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_gen	0.00	0.00

---

Module Instance : tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	100.00	85.00			96.55	100.00	u_tl_adapter_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_gen	0.00	0.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_rsp_intg_gen

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_gen	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_bus_intg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.31			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_gen	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_bus_intg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.47	100.00	89.87			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_gen	100.00	100.00