Module Definition
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Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_creator_seed_sw_rw_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_owner_seed_sw_rw_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_iso_part_sw_rd_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_iso_part_sw_wr_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_seed_hw_rd_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_flash_init

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.47 100.00 73.96 89.47 98.94 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sync_rma_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.req_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 94.44 100.00 83.33 100.00 u_addr_sync_reqack


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.ack_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 94.44 100.00 83.33 100.00 u_addr_sync_reqack


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.req_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.22 97.22 100.00 91.67 100.00 u_data_sync_reqack


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.ack_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.22 97.22 100.00 91.67 100.00 u_data_sync_reqack


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_escalation_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00

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