Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : flash_ctrl_lcmgr
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.47 100.00 73.96 89.47 98.94 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_hw_if 92.47 100.00 73.96 89.47 98.94 100.00



Module Instance : tb.dut.u_flash_hw_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.47 100.00 73.96 89.47 98.94 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.23 99.27 76.85 90.48 89.47 97.30 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.73 97.12 86.40 98.44 100.00 41.67 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_addr_cnt 90.91 90.91
u_addr_sync_reqack 96.46 95.83 100.00 90.00 100.00
u_bus_intg 100.00 100.00
u_data_intg_chk 100.00 100.00 100.00
u_data_sync_reqack 98.23 97.92 100.00 95.00 100.00
u_page_cnt 75.76 75.76
u_prim_flop_err_sts 100.00 100.00 100.00
u_rma_state_regs 100.00 100.00 100.00 100.00
u_seed_cnt 87.50 87.50
u_state_regs 100.00 100.00 100.00 100.00
u_sync_flash_init 100.00 100.00 100.00
u_sync_rma_req 100.00 100.00 100.00 100.00
u_wipe_idx_cnt 90.00 90.00
u_word_cnt 80.77 80.77


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl_lcmgr
Line No.TotalCoveredPercent
TOTAL242242100.00
CONT_ASSIGN14911100.00
ALWAYS15233100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17111100.00
ALWAYS17477100.00
CONT_ASSIGN18511100.00
ALWAYS22755100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24711100.00
ALWAYS25133100.00
CONT_ASSIGN26111100.00
CONT_ASSIGN26211100.00
ALWAYS26466100.00
CONT_ASSIGN27811100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
ALWAYS35999100.00
CONT_ASSIGN38011100.00
ALWAYS3868585100.00
CONT_ASSIGN60711100.00
ALWAYS61333100.00
ALWAYS67377100.00
ALWAYS6881010100.00
ALWAYS70522100.00
CONT_ASSIGN71411100.00
CONT_ASSIGN71511100.00
CONT_ASSIGN73711100.00
CONT_ASSIGN74111100.00
CONT_ASSIGN74211100.00
CONT_ASSIGN75411100.00
ALWAYS7616666100.00
CONT_ASSIGN89111100.00
CONT_ASSIGN89211100.00
CONT_ASSIGN89311100.00
CONT_ASSIGN89400
CONT_ASSIGN89500
CONT_ASSIGN89611100.00
CONT_ASSIGN89711100.00
CONT_ASSIGN89811100.00
CONT_ASSIGN90011100.00
CONT_ASSIGN90211100.00
CONT_ASSIGN90511100.00
CONT_ASSIGN90611100.00
CONT_ASSIGN90811100.00
CONT_ASSIGN90911100.00
CONT_ASSIGN91111100.00
CONT_ASSIGN91411100.00
CONT_ASSIGN91811100.00
CONT_ASSIGN92111100.00
ALWAYS93200
CONT_ASSIGN93911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
149 1 1
152 3 3
170 1 1
171 1 1
174 1 1
175 1 1
176 1 1
177 1 1
179 1 1
180 1 1
181 1 1
185 1 1
227 1 1
228 1 1
229 1 1
231 1 1
232 1 1
243 1 1
247 1 1
251 1 1
252 1 1
254 1 1
261 1 1
262 1 1
264 1 1
265 1 1
266 1 1
268 1 1
270 1 1
271 1 1
MISSING_ELSE
278 1 1
279 1 1
280 1 1
359 1 1
360 1 1
361 1 1
363 1 1
364 1 1
365 1 1
MISSING_ELSE
368 1 1
369 1 1
370 1 1
MISSING_ELSE
380 1 1
386 1 1
389 1 1
390 1 1
391 1 1
392 1 1
395 1 1
396 1 1
397 1 1
398 1 1
399 1 1
402 1 1
404 1 1
405 1 1
406 1 1
409 1 1
411 1 1
412 1 1
415 1 1
416 1 1
419 1 1
420 1 1
423 1 1
425 1 1
427 1 1
433 1 1
434 1 1
435 1 1
436 1 1
MISSING_ELSE
441 1 1
442 1 1
443 1 1
444 1 1
445 1 1
446 1 1
MISSING_ELSE
451 1 1
452 1 1
453 1 1
454 1 1
455 1 1
457 1 1
MISSING_ELSE
464 1 1
467 1 1
468 1 1
469 1 1
472 1 1
473 1 1
474 1 1
475 1 1
476 1 1
477 1 1
478 1 1
MISSING_ELSE
483 1 1
484 1 1
485 1 1
487 1 1
488 1 1
489 1 1
491 1 1
497 1 1
498 1 1
499 1 1
MISSING_ELSE
505 1 1
506 1 1
507 1 1
==> MISSING_ELSE
512 1 1
513 1 1
514 1 1
516 1 1
520 1 1
521 1 1
522 1 1
MISSING_ELSE
531 1 1
532 1 1
533 1 1
534 1 1
536 1 1
543 1 1
544 1 1
545 1 1
549 1 1
550 1 1
551 1 1
552 1 1
569 1 1
572 1 1
MISSING_ELSE
607 1 1
613 3 3
673 1 1
674 1 1
675 1 1
676 1 1
678 1 1
679 1 1
680 1 1
688 1 1
689 1 1
690 1 1
691 1 1
692 1 1
693 1 1
694 1 1
MISSING_ELSE
696 1 1
697 1 1
698 1 1
MISSING_ELSE
MISSING_ELSE
705 1 1
706 1 1
MISSING_ELSE
714 1 1
715 1 1
737 1 1
741 1 1
742 1 1
754 1 1
761 1 1
762 1 1
763 1 1
764 1 1
765 1 1
766 1 1
767 1 1
768 1 1
769 1 1
770 1 1
771 1 1
772 1 1
773 1 1
774 1 1
775 1 1
777 1 1
784 1 1
785 1 1
786 1 1
787 1 1
788 1 1
MISSING_ELSE
793 1 1
794 1 1
795 1 1
796 1 1
798 1 1
799 1 1
800 1 1
805 1 1
806 1 1
807 1 1
808 1 1
809 1 1
MISSING_ELSE
814 1 1
815 1 1
819 1 1
820 1 1
821 1 1
822 1 1
824 1 1
825 1 1
826 1 1
831 1 1
832 1 1
833 1 1
835 1 1
836 1 1
MISSING_ELSE
841 1 1
842 1 1
844 1 1
845 1 1
846 1 1
847 1 1
MISSING_ELSE
852 1 1
853 1 1
854 1 1
856 1 1
857 1 1
858 1 1
859 1 1
MISSING_ELSE
862 1 1
863 1 1
MISSING_ELSE
868 1 1
872 1 1
873 1 1
874 1 1
891 1 1
892 1 1
893 1 1
894 unreachable
895 unreachable
896 1 1
897 1 1
898 1 1
900 1 1
902 1 1
905 1 1
906 1 1
908 1 1
909 1 1
911 1 1
914 1 1
918 1 1
921 1 1
932 unreachable
933 unreachable
==> MISSING_ELSE
939 1 1


Cond Coverage for Module : flash_ctrl_lcmgr
TotalCoveredPercent
Conditions967173.96
Logical967173.96
Non-Logical00
Event00

 LINE       170
 EXPRESSION (phase == PhaseSeed)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       171
 EXPRESSION (phase == PhaseRma)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T21,T29

 LINE       185
 EXPRESSION (seed_err_q | seed_err_d)
             -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T24,T86
10Not Covered

 LINE       231
 EXPRESSION (addr_cnt_err_q | addr_cnt_err_d)
             -------1------   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       232
 EXPRESSION (seed_cnt_err_q | seed_cnt_err_d)
             -------1------   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       247
 EXPRESSION (data_invalid_q | (rvalid_i & ((~data_intg_ok))))
             -------1------   ---------------2--------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT20,T84,T87
10CoveredT20,T84,T87

 LINE       247
 SUB-EXPRESSION (rvalid_i & ((~data_intg_ok)))
                 ----1---   --------2--------
-1--2-StatusTests
01CoveredT20,T84,T87
10CoveredT1,T2,T3
11CoveredT20,T84,T87

 LINE       266
 EXPRESSION (seed_phase && validate_q && rvalid_i)
             -----1----    -----2----    ----3---
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       270
 EXPRESSION (seed_phase && rvalid_i)
             -----1----    ----2---
-1--2-StatusTests
01CoveredT9,T21,T28
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       363
 EXPRESSION (addr_key_req_d && addr_key_ack_q)
             -------1------    -------2------
-1--2-StatusTests
01CoveredT88,T89,T90
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       368
 EXPRESSION (data_key_req_d && data_key_ack_q)
             -------1------    -------2------
-1--2-StatusTests
01CoveredT91,T92,T93
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       457
 EXPRESSION (provision_en_i ? StReadSeeds : StWait)
             -------1------
-1-StatusTests
0CoveredT94,T95,T96
1CoveredT1,T2,T3

 LINE       473
 EXPRESSION (seed_cnt_q == flash_ctrl_pkg::NumSeeds)
            --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       516
 EXPRESSION ((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done)
             --------------------------1-------------------------    ------2------
-1--2-StatusTests
01CoveredT9,T21,T28
10CoveredT9,T21,T28
11CoveredT9,T21,T28

 LINE       516
 SUB-EXPRESSION (rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0])
                --------------------------1-------------------------
-1-StatusTests
0CoveredT9,T21,T29
1CoveredT9,T21,T28

 LINE       678
 EXPRESSION (page_err_q | page_err_d)
             -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       679
 EXPRESSION (word_err_q | word_err_d)
             -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       680
 EXPRESSION (rma_idx_err_q | rma_idx_err_d)
             ------1------   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       693
 EXPRESSION (wvalid_o && wready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT9,T21,T97

 LINE       697
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT9,T21,T17
10Unreachable
11CoveredT9,T21,T28

 LINE       705
 EXPRESSION (prog_cnt_en && wvalid_o && wready_i)
             -----1-----    ----2---    ----3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT9,T21,T97

 LINE       835
 EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && wready_i)
             -----------------------1----------------------    ----2---
-1--2-StatusTests
01CoveredT9,T21,T97
10Not Covered
11CoveredT9,T21,T97

 LINE       835
 SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
                -----------------------1----------------------
-1-StatusTests
0CoveredT9,T21,T17
1CoveredT9,T21,T97

 LINE       856
 EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && done_i)
             -----------------------1----------------------    ---2--
-1--2-StatusTests
01Not Covered
10CoveredT9,T21,T28
11CoveredT9,T21,T28

 LINE       856
 SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
                -----------------------1----------------------
-1-StatusTests
0CoveredT9,T21,T17
1CoveredT9,T21,T28

 LINE       862
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT9,T21,T17
10Unreachable
11CoveredT9,T21,T28

 LINE       863
 EXPRESSION (prog_data[beat_cnt] != rdata_i[(flash_ctrl_pkg::BusWidth - 1):0])
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT9,T21,T17
1CoveredT28,T98,T99

 LINE       892
 EXPRESSION (seed_phase ? start : rma_start)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       893
 EXPRESSION (seed_phase ? op : rma_op)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       896
 EXPRESSION (seed_phase ? part_sel : rma_part_sel)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       897
 EXPRESSION (seed_phase ? info_sel : rma_info_sel)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       898
 EXPRESSION (seed_phase ? num_words : rma_num_words)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       900
 EXPRESSION (seed_phase ? ({addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}) : ({rma_addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       906
 EXPRESSION (seed_phase | rma_phase)
             -----1----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT9,T21,T29
10CoveredT1,T2,T3

 LINE       914
 EXPRESSION (page_err_q | word_err_q | fsm_err | state_err | rma_idx_err_q | addr_cnt_err_q | seed_cnt_err_q)
             -----1----   -----2----   ---3---   ----4----   ------5------   -------6------   -------7------
-1--2--3--4--5--6--7-StatusTests
0000000CoveredT1,T2,T3
0000001Not Covered
0000010Not Covered
0000100Not Covered
0001000CoveredT100,T101,T102
0010000Not Covered
0100000Not Covered
1000000Not Covered

FSM Coverage for Module : flash_ctrl_lcmgr
Summary for FSM :: state_q
TotalCoveredPercent
States 11 11 100.00 (Not included in score)
Transitions 25 22 88.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StDisabled 545 Covered T20,T29,T33
StEntropyReseed 499 Covered T9,T21,T29
StIdle 432 Covered T1,T2,T3
StInvalid 520 Covered T100,T101,T102
StReadEval 478 Covered T1,T2,T3
StReadSeeds 457 Covered T1,T2,T3
StReqAddrKey 436 Covered T1,T2,T3
StReqDataKey 446 Covered T1,T2,T3
StRmaRsp 520 Covered T9,T21,T28
StRmaWipe 434 Covered T9,T21,T29
StWait 457 Covered T1,T2,T3


transitionsLine No.CoveredTests
StEntropyReseed->StDisabled 572 Covered T93,T63,T95
StEntropyReseed->StRmaWipe 507 Covered T9,T21,T29
StIdle->StDisabled 572 Not Covered
StIdle->StReqAddrKey 436 Covered T1,T2,T3
StIdle->StRmaWipe 434 Covered T97,T103,T104
StInvalid->StDisabled 572 Not Covered
StReadEval->StDisabled 572 Covered T29,T105,T106
StReadEval->StReadSeeds 485 Covered T1,T2,T3
StReadSeeds->StDisabled 572 Covered T20,T83,T84
StReadSeeds->StReadEval 478 Covered T1,T2,T3
StReadSeeds->StWait 475 Covered T1,T2,T3
StReqAddrKey->StDisabled 572 Covered T107,T90,T63
StReqAddrKey->StReqDataKey 446 Covered T1,T2,T3
StReqAddrKey->StRmaWipe 444 Covered T88,T89,T108
StReqDataKey->StDisabled 572 Covered T29,T92,T94
StReqDataKey->StReadSeeds 457 Covered T1,T2,T3
StReqDataKey->StRmaWipe 454 Covered T91,T93,T106
StReqDataKey->StWait 457 Covered T94,T95,T96
StRmaRsp->StDisabled 572 Covered T109
StRmaRsp->StInvalid 534 Not Covered
StRmaWipe->StDisabled 572 Covered T29,T97,T107
StRmaWipe->StInvalid 520 Covered T100,T101,T102
StRmaWipe->StRmaRsp 520 Covered T9,T21,T28
StWait->StDisabled 572 Covered T33,T52,T45
StWait->StEntropyReseed 499 Covered T9,T21,T29


Summary for FSM :: rma_state_q
TotalCoveredPercent
States 10 9 90.00 (Not included in score)
Transitions 13 12 92.31
Sequences 0 0

State, Transition and Sequence Details for FSM :: rma_state_q
statesLine No.CoveredTests
StRmaDisabled 785 Covered T9,T20,T21
StRmaErase 796 Covered T9,T21,T29
StRmaEraseWait 809 Covered T9,T21,T29
StRmaIdle 800 Covered T1,T2,T3
StRmaInvalid 872 Not Covered
StRmaPageSel 787 Covered T9,T21,T29
StRmaProgram 822 Covered T9,T21,T97
StRmaProgramWait 836 Covered T9,T21,T97
StRmaRdVerify 847 Covered T9,T21,T28
StRmaWordSel 815 Covered T9,T21,T29


transitionsLine No.CoveredTests
StRmaErase->StRmaEraseWait 809 Covered T9,T21,T29
StRmaEraseWait->StRmaWordSel 815 Covered T9,T21,T29
StRmaIdle->StRmaDisabled 785 Covered T9,T20,T21
StRmaIdle->StRmaPageSel 787 Covered T9,T21,T29
StRmaPageSel->StRmaDisabled 794 Not Covered
StRmaPageSel->StRmaErase 796 Covered T9,T21,T29
StRmaPageSel->StRmaIdle 800 Covered T9,T21,T28
StRmaProgram->StRmaProgramWait 836 Covered T9,T21,T97
StRmaProgramWait->StRmaRdVerify 847 Covered T9,T21,T28
StRmaRdVerify->StRmaWordSel 859 Covered T9,T21,T28
StRmaWordSel->StRmaDisabled 820 Covered T29,T107,T94
StRmaWordSel->StRmaPageSel 826 Covered T9,T21,T28
StRmaWordSel->StRmaProgram 822 Covered T9,T21,T97



Branch Coverage for Module : flash_ctrl_lcmgr
Line No.TotalCoveredPercent
Branches 94 93 98.94
TERNARY 892 2 2 100.00
TERNARY 893 2 2 100.00
TERNARY 896 2 2 100.00
TERNARY 897 2 2 100.00
TERNARY 898 2 2 100.00
TERNARY 900 2 2 100.00
IF 152 2 2 100.00
IF 174 2 2 100.00
IF 227 2 2 100.00
IF 251 2 2 100.00
IF 264 4 4 100.00
IF 359 5 5 100.00
CASE 427 27 26 96.30
IF 569 2 2 100.00
IF 613 2 2 100.00
IF 673 2 2 100.00
IF 688 7 7 100.00
IF 705 2 2 100.00
CASE 777 23 23 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 892 (seed_phase) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 893 (seed_phase) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 896 (seed_phase) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 897 (seed_phase) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 898 (seed_phase) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 900 (seed_phase) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 152 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 174 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 227 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 251 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 264 if ((!rst_ni)) -2-: 266 if (((seed_phase && validate_q) && rvalid_i)) -3-: 270 if ((seed_phase && rvalid_i))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 359 if ((!rst_ni)) -2-: 363 if ((addr_key_req_d && addr_key_ack_q)) -3-: 368 if ((data_key_req_d && data_key_ack_q))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T2,T3
0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 427 case (state_q) -2-: 433 if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqInit])) -3-: 435 if (init_q) -4-: 443 if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqKey])) -5-: 445 if (addr_key_ack_q) -6-: 453 if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqKey])) -7-: 455 if (data_key_ack_q) -8-: 457 (provision_en_i) ? -9-: 473 if ((seed_cnt_q == flash_ctrl_pkg::NumSeeds)) -10-: 476 if (done_i) -11-: 487 if (validate_q) -12-: 498 if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqWait])) -13-: 506 if (edn_ack_i) -14-: 516 if (((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done)) -15-: 521 if (rma_wipe_done) -16-: 533 if (lc_ctrl_pkg::lc_tx_test_false_loose(err_sts_q))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16-StatusTests
StIdle 1 - - - - - - - - - - - - - - Covered T97,T103,T104
StIdle 0 1 - - - - - - - - - - - - - Covered T1,T2,T3
StIdle 0 0 - - - - - - - - - - - - - Covered T1,T2,T3
StReqAddrKey - - 1 - - - - - - - - - - - - Covered T88,T89,T108
StReqAddrKey - - 0 1 - - - - - - - - - - - Covered T1,T2,T3
StReqAddrKey - - 0 0 - - - - - - - - - - - Covered T1,T2,T3
StReqDataKey - - - - 1 - - - - - - - - - - Covered T91,T93,T106
StReqDataKey - - - - 0 1 1 - - - - - - - - Covered T1,T2,T3
StReqDataKey - - - - 0 1 0 - - - - - - - - Covered T94,T95,T96
StReqDataKey - - - - 0 0 - - - - - - - - - Covered T1,T2,T3
StReadSeeds - - - - - - - 1 - - - - - - - Covered T1,T2,T3
StReadSeeds - - - - - - - 0 1 - - - - - - Covered T1,T2,T3
StReadSeeds - - - - - - - 0 0 - - - - - - Covered T1,T2,T3
StReadEval - - - - - - - - - 1 - - - - - Covered T1,T2,T3
StReadEval - - - - - - - - - 0 - - - - - Covered T1,T2,T3
StWait - - - - - - - - - - 1 - - - - Covered T9,T21,T29
StWait - - - - - - - - - - 0 - - - - Covered T1,T2,T3
StEntropyReseed - - - - - - - - - - - 1 - - - Covered T9,T21,T29
StEntropyReseed - - - - - - - - - - - 0 - - - Not Covered
StRmaWipe - - - - - - - - - - - - 1 - - Covered T9,T21,T17
StRmaWipe - - - - - - - - - - - - 0 1 - Covered T9,T21,T17
StRmaWipe - - - - - - - - - - - - 0 0 - Covered T9,T21,T29
StRmaRsp - - - - - - - - - - - - - - 1 Covered T17
StRmaRsp - - - - - - - - - - - - - - 0 Covered T9,T21,T17
StDisabled - - - - - - - - - - - - - - - Covered T20,T29,T33
StInvalid - - - - - - - - - - - - - - - Covered T17,T100,T101
default - - - - - - - - - - - - - - - Covered T17


LineNo. Expression -1-: 569 if (((prim_mubi_pkg::mubi4_test_true_loose(disable_i) && (state_d != StInvalid)) && (!rma_done)))

Branches:
-1-StatusTests
1 Covered T20,T29,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 613 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 673 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 688 if ((!rst_ni)) -2-: 690 if (beat_cnt_clr) -3-: 692 if (prog_cnt_en) -4-: 693 if ((wvalid_o && wready_i)) -5-: 696 if (rd_cnt_en) -6-: 697 if ((rvalid_i && rready_o))

Branches:
-1--2--3--4--5--6-StatusTests
1 - - - - - Covered T1,T2,T3
0 1 - - - - Covered T9,T21,T17
0 0 1 1 - - Covered T9,T21,T17
0 0 1 0 - - Covered T17
0 0 0 - 1 1 Covered T9,T21,T17
0 0 0 - 1 0 Covered T9,T21,T17
0 0 0 - 0 - Covered T1,T2,T3


LineNo. Expression -1-: 705 if (((prog_cnt_en && wvalid_o) && wready_i))

Branches:
-1-StatusTests
1 Covered T9,T21,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 777 case (rma_state_q) -2-: 784 if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) -3-: 786 if (rma_wipe_req_int) -4-: 793 if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) -5-: 795 if ((page_cnt < end_page)) -6-: 807 if (done_i) -7-: 819 if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) -8-: 821 if ((word_cnt < flash_ctrl_pkg::BusWordsPerPage)) -9-: 835 if (((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && wready_i)) -10-: 844 if (done_i) -11-: 856 if (((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && done_i)) -12-: 862 if ((rvalid_i && rready_o))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12-StatusTests
StRmaIdle 1 - - - - - - - - - - Covered T9,T20,T21
StRmaIdle 0 1 - - - - - - - - - Covered T9,T21,T29
StRmaIdle 0 0 - - - - - - - - - Covered T1,T2,T3
StRmaPageSel - - 1 - - - - - - - - Covered T17
StRmaPageSel - - 0 1 - - - - - - - Covered T9,T21,T29
StRmaPageSel - - 0 0 - - - - - - - Covered T9,T21,T17
StRmaErase - - - - 1 - - - - - - Covered T9,T21,T29
StRmaErase - - - - 0 - - - - - - Covered T9,T21,T29
StRmaEraseWait - - - - - - - - - - - Covered T9,T21,T29
StRmaWordSel - - - - - 1 - - - - - Covered T29,T17,T107
StRmaWordSel - - - - - 0 1 - - - - Covered T9,T21,T17
StRmaWordSel - - - - - 0 0 - - - - Covered T9,T21,T17
StRmaProgram - - - - - - - 1 - - - Covered T9,T21,T17
StRmaProgram - - - - - - - 0 - - - Covered T9,T21,T17
StRmaProgramWait - - - - - - - - 1 - - Covered T9,T21,T17
StRmaProgramWait - - - - - - - - 0 - - Covered T9,T21,T17
StRmaRdVerify - - - - - - - - - 1 - Covered T9,T21,T17
StRmaRdVerify - - - - - - - - - 0 - Covered T9,T21,T17
StRmaRdVerify - - - - - - - - - - 1 Covered T9,T21,T17
StRmaRdVerify - - - - - - - - - - 0 Covered T9,T21,T17
StRmaDisabled - - - - - - - - - - - Covered T9,T20,T21
StRmaInvalid - - - - - - - - - - - Covered T17
default - - - - - - - - - - - Covered T17


Assert Coverage for Module : flash_ctrl_lcmgr
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DisableChk_A 349026639 4872996 0 30
ProgRdVerify_A 347112053 2043538 0 0
u_rma_state_regs_A 360968368 360299484 0 0
u_state_regs_A 360968368 360299484 0 0


DisableChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 349026639 4872996 0 30
T15 382887 0 0 0
T16 11203 0 0 0
T20 1140 3 0 0
T21 408711 0 0 0
T26 7528 0 0 0
T27 174681 0 0 0
T28 0 10 0 0
T29 3824 21 0 0
T33 0 185 0 1
T34 0 137 0 1
T35 0 0 0 1
T45 0 350 0 1
T46 0 0 0 1
T47 1513 0 0 0
T52 0 232 0 1
T61 13141 0 0 0
T77 5120 0 0 0
T83 0 10 0 0
T97 0 129610 0 0
T107 0 20 0 0
T110 0 0 0 1
T111 0 0 0 1
T112 0 0 0 1
T113 0 0 0 1

ProgRdVerify_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 347112053 2043538 0 0
T9 401205 65920 0 0
T10 53073 0 0 0
T15 382887 0 0 0
T16 11203 0 0 0
T20 1140 0 0 0
T21 408711 65920 0 0
T22 35370 0 0 0
T23 1287 0 0 0
T24 1126 0 0 0
T25 1435 0 0 0
T28 0 65920 0 0
T64 0 65920 0 0
T65 0 65920 0 0
T66 0 65920 0 0
T103 0 4 0 0
T114 0 65920 0 0
T115 0 4 0 0
T116 0 65920 0 0

u_rma_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 360968368 360299484 0 0
T1 1461 1190 0 0
T2 96602 95525 0 0
T3 393564 393481 0 0
T4 83778 78912 0 0
T5 436096 436008 0 0
T9 401205 401190 0 0
T22 35370 35285 0 0
T23 1287 1210 0 0
T24 1126 920 0 0
T25 1435 1367 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 360968368 360299484 0 0
T1 1461 1190 0 0
T2 96602 95525 0 0
T3 393564 393481 0 0
T4 83778 78912 0 0
T5 436096 436008 0 0
T9 401205 401190 0 0
T22 35370 35285 0 0
T23 1287 1210 0 0
T24 1126 920 0 0
T25 1435 1367 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%