Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23591657	1		T1	196		T2	213784		T3	1371
full_word	7067044	1		T1	196		T2	2740		T3	3186

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30658381	1		T1	392		T2	216524		T3	4557
auto[TlIntgErrCmd]	103	1		T212	6		T222	7		T223	5
auto[TlIntgErrData]	124	1		T212	9		T222	6		T247	11
auto[TlIntgErrBoth]	93	1		T212	5		T222	7		T223	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26878825	1		T1	329		T2	214556		T3	1171
auto[1]	3779876	1		T1	63		T2	1968		T3	3386

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23057146	1		T1	187		T2	213513		T3	1065
auto[TlIntgErrNone]	partial	auto[1]	534215	1		T1	9		T2	271		T3	306
auto[TlIntgErrNone]	full_word	auto[0]	3821541	1		T1	142		T2	1043		T3	106
auto[TlIntgErrNone]	full_word	auto[1]	3245479	1		T1	54		T2	1697		T3	3080
auto[TlIntgErrCmd]	partial	auto[0]	37	1		T212	3		T222	1		T223	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1		T212	2		T222	4		T223	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T373	1		T250	1		T377	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T212	1		T222	2		T376	1
auto[TlIntgErrData]	partial	auto[0]	51	1		T212	2		T222	2		T247	3
auto[TlIntgErrData]	partial	auto[1]	67	1		T212	7		T222	4		T247	8
auto[TlIntgErrData]	full_word	auto[0]	5	1		T375	1		T378	2		T379	1
auto[TlIntgErrData]	full_word	auto[1]	1	1		T238	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	35	1		T212	4		T222	2		T223	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T212	1		T222	4		T223	4
auto[TlIntgErrBoth]	full_word	auto[0]	7	1		T222	1		T301	1		T373	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T247	1		-	-		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20178	1		T68	587		T69	126		T70	107
full_word	3413815	1		T4	1		T6	40267		T26	131072

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3433698	1		T4	1		T6	40267		T26	131072
auto[TlIntgErrCmd]	105	1		T212	5		T222	7		T223	5
auto[TlIntgErrData]	93	1		T212	4		T222	5		T223	3
auto[TlIntgErrBoth]	97	1		T212	9		T222	7		T223	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3408560	1		T4	1		T6	40267		T26	131072
auto[1]	25433	1		T68	763		T69	144		T70	154

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1266	1		T68	33		T69	8		T70	5
auto[TlIntgErrNone]	partial	auto[1]	18636	1		T68	554		T69	118		T70	102
auto[TlIntgErrNone]	full_word	auto[0]	3407184	1		T4	1		T6	40267		T26	131072
auto[TlIntgErrNone]	full_word	auto[1]	6612	1		T68	209		T69	26		T70	52
auto[TlIntgErrCmd]	partial	auto[0]	31	1		T212	1		T222	2		T223	1
auto[TlIntgErrCmd]	partial	auto[1]	68	1		T212	4		T222	5		T223	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T247	1		T379	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T250	1		T238	1		T375	1
auto[TlIntgErrData]	partial	auto[0]	47	1		T212	3		T222	5		T247	3
auto[TlIntgErrData]	partial	auto[1]	40	1		T223	3		T247	2		T301	3
auto[TlIntgErrData]	full_word	auto[0]	5	1		T247	1		T376	1		T380	1
auto[TlIntgErrData]	full_word	auto[1]	1	1		T212	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	24	1		T212	2		T222	2		T247	1
auto[TlIntgErrBoth]	partial	auto[1]	66	1		T212	7		T222	5		T223	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T376	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T247	1		T301	2		T249	1