Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : tlul_sram_byte
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_to_prog_fifo.u_sram_byte 100.00 100.00
tb.dut.u_to_rd_fifo.u_sram_byte 100.00 100.00
tb.dut.u_tl_adapter_eflash.u_sram_byte 100.00 100.00



Module Instance : tb.dut.u_to_prog_fifo.u_sram_byte

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.89 100.00 65.22 85.71 84.62 u_to_prog_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_to_rd_fifo.u_sram_byte

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.52 94.20 73.11 82.76 100.00 u_to_rd_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.55 100.00 81.67 96.55 100.00 u_tl_adapter_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : tlul_sram_byte
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
323 1 1
324 1 1
325 1 1

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_sram_byte
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
323 1 1
324 1 1
325 1 1

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_sram_byte
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
323 1 1
324 1 1
325 1 1

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
323 1 1
324 1 1
325 1 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%