Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T26

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T26
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T26
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T26

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T26
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T16
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T26

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T26

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1394823960	1392394040	0	0
CheckNGreaterZero_A	3500	3500	0	0
GntImpliesReady_A	1394823960	355690690	0	0
GntImpliesValid_A	1394823960	355690690	0	0
GrantKnown_A	1394823960	1392394040	0	0
IdxKnown_A	1394823960	1392394040	0	0
IndexIsCorrect_A	1394823960	355690690	0	0
NoReadyValidNoGrant_A	1394823960	172439736	0	0
Priority_A	1394823960	378235514	0	0
ReadyAndValidImplyGrant_A	1394823960	355690690	0	0
ReqAndReadyImplyGrant_A	1394823960	355690690	0	0
ReqImpliesValid_A	1394823960	378235514	0	0
ValidKnown_A	1394823960	1392394040	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394823960	1392394040	0	0
T1	1601812	1601740	0	0
T2	1737316	1736928	0	0
T3	382068	381536	0	0
T4	3868	3288	0	0
T5	13016	12668	0	0
T6	1882604	1882384	0	0
T10	257612	257408	0	0
T15	329392	314184	0	0
T25	5076	4796	0	0
T26	3131436	3131404	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3500	3500	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T10	4	4	0	0
T15	4	4	0	0
T25	4	4	0	0
T26	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394823960	355690690	0	0
T1	1601812	514650	0	0
T2	1737316	850554	0	0
T3	382068	42270	0	0
T4	3868	318	0	0
T5	13016	880	0	0
T6	1882604	665192	0	0
T10	257612	36706	0	0
T15	329392	71018	0	0
T16	0	26230	0	0
T25	5076	64	0	0
T26	3131436	700566	0	0
T42	0	136176	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394823960	355690690	0	0
T1	1601812	514650	0	0
T2	1737316	850554	0	0
T3	382068	42270	0	0
T4	3868	318	0	0
T5	13016	880	0	0
T6	1882604	665192	0	0
T10	257612	36706	0	0
T15	329392	71018	0	0
T16	0	26230	0	0
T25	5076	64	0	0
T26	3131436	700566	0	0
T42	0	136176	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394823960	1392394040	0	0
T1	1601812	1601740	0	0
T2	1737316	1736928	0	0
T3	382068	381536	0	0
T4	3868	3288	0	0
T5	13016	12668	0	0
T6	1882604	1882384	0	0
T10	257612	257408	0	0
T15	329392	314184	0	0
T25	5076	4796	0	0
T26	3131436	3131404	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394823960	1392394040	0	0
T1	1601812	1601740	0	0
T2	1737316	1736928	0	0
T3	382068	381536	0	0
T4	3868	3288	0	0
T5	13016	12668	0	0
T6	1882604	1882384	0	0
T10	257612	257408	0	0
T15	329392	314184	0	0
T25	5076	4796	0	0
T26	3131436	3131404	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394823960	355690690	0	0
T1	1601812	514650	0	0
T2	1737316	850554	0	0
T3	382068	42270	0	0
T4	3868	318	0	0
T5	13016	880	0	0
T6	1882604	665192	0	0
T10	257612	36706	0	0
T15	329392	71018	0	0
T16	0	26230	0	0
T25	5076	64	0	0
T26	3131436	700566	0	0
T42	0	136176	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394823960	172439736	0	0
T1	1601812	2109952	0	0
T2	1737316	2860	0	0
T3	382068	420	0	0
T4	3868	516	0	0
T5	13016	364	0	0
T6	1882604	177194	0	0
T10	257612	256	0	0
T15	329392	18264	0	0
T16	0	34386	0	0
T21	0	70	0	0
T25	5076	256	0	0
T26	3131436	806656	0	0
T42	0	516	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394823960	378235514	0	0
T1	1601812	514650	0	0
T2	1737316	850554	0	0
T3	382068	42270	0	0
T4	3868	318	0	0
T5	13016	880	0	0
T6	1882604	753176	0	0
T10	257612	36706	0	0
T15	329392	71018	0	0
T16	0	31778	0	0
T25	5076	64	0	0
T26	3131436	700566	0	0
T42	0	136176	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394823960	355690690	0	0
T1	1601812	514650	0	0
T2	1737316	850554	0	0
T3	382068	42270	0	0
T4	3868	318	0	0
T5	13016	880	0	0
T6	1882604	665192	0	0
T10	257612	36706	0	0
T15	329392	71018	0	0
T16	0	26230	0	0
T25	5076	64	0	0
T26	3131436	700566	0	0
T42	0	136176	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394823960	355690690	0	0
T1	1601812	514650	0	0
T2	1737316	850554	0	0
T3	382068	42270	0	0
T4	3868	318	0	0
T5	13016	880	0	0
T6	1882604	665192	0	0
T10	257612	36706	0	0
T15	329392	71018	0	0
T16	0	26230	0	0
T25	5076	64	0	0
T26	3131436	700566	0	0
T42	0	136176	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394823960	378235514	0	0
T1	1601812	514650	0	0
T2	1737316	850554	0	0
T3	382068	42270	0	0
T4	3868	318	0	0
T5	13016	880	0	0
T6	1882604	753176	0	0
T10	257612	36706	0	0
T15	329392	71018	0	0
T16	0	31778	0	0
T25	5076	64	0	0
T26	3131436	700566	0	0
T42	0	136176	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394823960	1392394040	0	0
T1	1601812	1601740	0	0
T2	1737316	1736928	0	0
T3	382068	381536	0	0
T4	3868	3288	0	0
T5	13016	12668	0	0
T6	1882604	1882384	0	0
T10	257612	257408	0	0
T15	329392	314184	0	0
T25	5076	4796	0	0
T26	3131436	3131404	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T16,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T16,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T16,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T16,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T16,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T16,T17
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T16,T17
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T16,T17

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T16,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	348705990	348098510	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	348705990	94767307	0	0
GntImpliesValid_A	348705990	94767307	0	0
GrantKnown_A	348705990	348098510	0	0
IdxKnown_A	348705990	348098510	0	0
IndexIsCorrect_A	348705990	94767307	0	0
NoReadyValidNoGrant_A	348705990	44910162	0	0
Priority_A	348705990	100361265	0	0
ReadyAndValidImplyGrant_A	348705990	94767307	0	0
ReqAndReadyImplyGrant_A	348705990	94767307	0	0
ReqImpliesValid_A	348705990	100361265	0	0
ValidKnown_A	348705990	348098510	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	94767307	0	0
T1	400453	129428	0	0
T2	434329	209454	0	0
T3	95517	11182	0	0
T4	967	158	0	0
T5	3254	316	0	0
T6	470651	196582	0	0
T10	64403	8829	0	0
T15	82348	35509	0	0
T25	1269	32	0	0
T26	782859	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	94767307	0	0
T1	400453	129428	0	0
T2	434329	209454	0	0
T3	95517	11182	0	0
T4	967	158	0	0
T5	3254	316	0	0
T6	470651	196582	0	0
T10	64403	8829	0	0
T15	82348	35509	0	0
T25	1269	32	0	0
T26	782859	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	94767307	0	0
T1	400453	129428	0	0
T2	434329	209454	0	0
T3	95517	11182	0	0
T4	967	158	0	0
T5	3254	316	0	0
T6	470651	196582	0	0
T10	64403	8829	0	0
T15	82348	35509	0	0
T25	1269	32	0	0
T26	782859	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	44910162	0	0
T1	400453	530688	0	0
T2	434329	651	0	0
T3	95517	160	0	0
T4	967	256	0	0
T5	3254	166	0	0
T6	470651	43401	0	0
T10	64403	128	0	0
T15	82348	9132	0	0
T25	1269	128	0	0
T26	782859	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	100361265	0	0
T1	400453	129428	0	0
T2	434329	209454	0	0
T3	95517	11182	0	0
T4	967	158	0	0
T5	3254	316	0	0
T6	470651	217256	0	0
T10	64403	8829	0	0
T15	82348	35509	0	0
T25	1269	32	0	0
T26	782859	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	94767307	0	0
T1	400453	129428	0	0
T2	434329	209454	0	0
T3	95517	11182	0	0
T4	967	158	0	0
T5	3254	316	0	0
T6	470651	196582	0	0
T10	64403	8829	0	0
T15	82348	35509	0	0
T25	1269	32	0	0
T26	782859	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	94767307	0	0
T1	400453	129428	0	0
T2	434329	209454	0	0
T3	95517	11182	0	0
T4	967	158	0	0
T5	3254	316	0	0
T6	470651	196582	0	0
T10	64403	8829	0	0
T15	82348	35509	0	0
T25	1269	32	0	0
T26	782859	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	100361265	0	0
T1	400453	129428	0	0
T2	434329	209454	0	0
T3	95517	11182	0	0
T4	967	158	0	0
T5	3254	316	0	0
T6	470651	217256	0	0
T10	64403	8829	0	0
T15	82348	35509	0	0
T25	1269	32	0	0
T26	782859	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T16,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T16,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T16,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T16,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T16,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T16,T17
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T16,T17
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T16,T17

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T16,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	348705990	348098510	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	348705990	94767319	0	0
GntImpliesValid_A	348705990	94767319	0	0
GrantKnown_A	348705990	348098510	0	0
IdxKnown_A	348705990	348098510	0	0
IndexIsCorrect_A	348705990	94767319	0	0
NoReadyValidNoGrant_A	348705990	44910154	0	0
Priority_A	348705990	100361285	0	0
ReadyAndValidImplyGrant_A	348705990	94767319	0	0
ReqAndReadyImplyGrant_A	348705990	94767319	0	0
ReqImpliesValid_A	348705990	100361285	0	0
ValidKnown_A	348705990	348098510	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	94767319	0	0
T1	400453	129428	0	0
T2	434329	209454	0	0
T3	95517	11182	0	0
T4	967	158	0	0
T5	3254	316	0	0
T6	470651	196582	0	0
T10	64403	8829	0	0
T15	82348	35509	0	0
T25	1269	32	0	0
T26	782859	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	94767319	0	0
T1	400453	129428	0	0
T2	434329	209454	0	0
T3	95517	11182	0	0
T4	967	158	0	0
T5	3254	316	0	0
T6	470651	196582	0	0
T10	64403	8829	0	0
T15	82348	35509	0	0
T25	1269	32	0	0
T26	782859	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	94767319	0	0
T1	400453	129428	0	0
T2	434329	209454	0	0
T3	95517	11182	0	0
T4	967	158	0	0
T5	3254	316	0	0
T6	470651	196582	0	0
T10	64403	8829	0	0
T15	82348	35509	0	0
T25	1269	32	0	0
T26	782859	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	44910154	0	0
T1	400453	530688	0	0
T2	434329	651	0	0
T3	95517	160	0	0
T4	967	256	0	0
T5	3254	166	0	0
T6	470651	43401	0	0
T10	64403	128	0	0
T15	82348	9132	0	0
T25	1269	128	0	0
T26	782859	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	100361285	0	0
T1	400453	129428	0	0
T2	434329	209454	0	0
T3	95517	11182	0	0
T4	967	158	0	0
T5	3254	316	0	0
T6	470651	217256	0	0
T10	64403	8829	0	0
T15	82348	35509	0	0
T25	1269	32	0	0
T26	782859	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	94767319	0	0
T1	400453	129428	0	0
T2	434329	209454	0	0
T3	95517	11182	0	0
T4	967	158	0	0
T5	3254	316	0	0
T6	470651	196582	0	0
T10	64403	8829	0	0
T15	82348	35509	0	0
T25	1269	32	0	0
T26	782859	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	94767319	0	0
T1	400453	129428	0	0
T2	434329	209454	0	0
T3	95517	11182	0	0
T4	967	158	0	0
T5	3254	316	0	0
T6	470651	196582	0	0
T10	64403	8829	0	0
T15	82348	35509	0	0
T25	1269	32	0	0
T26	782859	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	100361285	0	0
T1	400453	129428	0	0
T2	434329	209454	0	0
T3	95517	11182	0	0
T4	967	158	0	0
T5	3254	316	0	0
T6	470651	217256	0	0
T10	64403	8829	0	0
T15	82348	35509	0	0
T25	1269	32	0	0
T26	782859	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T26

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T26
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T26
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T26

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T26
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T16
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T26

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T26

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	348705990	348098510	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	348705990	83078032	0	0
GntImpliesValid_A	348705990	83078032	0	0
GrantKnown_A	348705990	348098510	0	0
IdxKnown_A	348705990	348098510	0	0
IndexIsCorrect_A	348705990	83078032	0	0
NoReadyValidNoGrant_A	348705990	41309710	0	0
Priority_A	348705990	88756482	0	0
ReadyAndValidImplyGrant_A	348705990	83078032	0	0
ReqAndReadyImplyGrant_A	348705990	83078032	0	0
ReqImpliesValid_A	348705990	88756482	0	0
ValidKnown_A	348705990	348098510	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	83078032	0	0
T1	400453	127897	0	0
T2	434329	215823	0	0
T3	95517	9953	0	0
T4	967	1	0	0
T5	3254	124	0	0
T6	470651	136014	0	0
T10	64403	9524	0	0
T15	82348	0	0	0
T16	0	13115	0	0
T25	1269	0	0	0
T26	782859	350251	0	0
T42	0	68088	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	83078032	0	0
T1	400453	127897	0	0
T2	434329	215823	0	0
T3	95517	9953	0	0
T4	967	1	0	0
T5	3254	124	0	0
T6	470651	136014	0	0
T10	64403	9524	0	0
T15	82348	0	0	0
T16	0	13115	0	0
T25	1269	0	0	0
T26	782859	350251	0	0
T42	0	68088	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	83078032	0	0
T1	400453	127897	0	0
T2	434329	215823	0	0
T3	95517	9953	0	0
T4	967	1	0	0
T5	3254	124	0	0
T6	470651	136014	0	0
T10	64403	9524	0	0
T15	82348	0	0	0
T16	0	13115	0	0
T25	1269	0	0	0
T26	782859	350251	0	0
T42	0	68088	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	41309710	0	0
T1	400453	524288	0	0
T2	434329	779	0	0
T3	95517	50	0	0
T4	967	2	0	0
T5	3254	16	0	0
T6	470651	45196	0	0
T10	64403	0	0	0
T15	82348	0	0	0
T16	0	17193	0	0
T21	0	35	0	0
T25	1269	0	0	0
T26	782859	403200	0	0
T42	0	258	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	88756482	0	0
T1	400453	127897	0	0
T2	434329	215823	0	0
T3	95517	9953	0	0
T4	967	1	0	0
T5	3254	124	0	0
T6	470651	159332	0	0
T10	64403	9524	0	0
T15	82348	0	0	0
T16	0	15889	0	0
T25	1269	0	0	0
T26	782859	350251	0	0
T42	0	68088	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	83078032	0	0
T1	400453	127897	0	0
T2	434329	215823	0	0
T3	95517	9953	0	0
T4	967	1	0	0
T5	3254	124	0	0
T6	470651	136014	0	0
T10	64403	9524	0	0
T15	82348	0	0	0
T16	0	13115	0	0
T25	1269	0	0	0
T26	782859	350251	0	0
T42	0	68088	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	83078032	0	0
T1	400453	127897	0	0
T2	434329	215823	0	0
T3	95517	9953	0	0
T4	967	1	0	0
T5	3254	124	0	0
T6	470651	136014	0	0
T10	64403	9524	0	0
T15	82348	0	0	0
T16	0	13115	0	0
T25	1269	0	0	0
T26	782859	350251	0	0
T42	0	68088	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	88756482	0	0
T1	400453	127897	0	0
T2	434329	215823	0	0
T3	95517	9953	0	0
T4	967	1	0	0
T5	3254	124	0	0
T6	470651	159332	0	0
T10	64403	9524	0	0
T15	82348	0	0	0
T16	0	15889	0	0
T25	1269	0	0	0
T26	782859	350251	0	0
T42	0	68088	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T26

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T26
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T26
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T26

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T26
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T16
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T26

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T26

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	348705990	348098510	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	348705990	83078032	0	0
GntImpliesValid_A	348705990	83078032	0	0
GrantKnown_A	348705990	348098510	0	0
IdxKnown_A	348705990	348098510	0	0
IndexIsCorrect_A	348705990	83078032	0	0
NoReadyValidNoGrant_A	348705990	41309710	0	0
Priority_A	348705990	88756482	0	0
ReadyAndValidImplyGrant_A	348705990	83078032	0	0
ReqAndReadyImplyGrant_A	348705990	83078032	0	0
ReqImpliesValid_A	348705990	88756482	0	0
ValidKnown_A	348705990	348098510	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	83078032	0	0
T1	400453	127897	0	0
T2	434329	215823	0	0
T3	95517	9953	0	0
T4	967	1	0	0
T5	3254	124	0	0
T6	470651	136014	0	0
T10	64403	9524	0	0
T15	82348	0	0	0
T16	0	13115	0	0
T25	1269	0	0	0
T26	782859	350251	0	0
T42	0	68088	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	83078032	0	0
T1	400453	127897	0	0
T2	434329	215823	0	0
T3	95517	9953	0	0
T4	967	1	0	0
T5	3254	124	0	0
T6	470651	136014	0	0
T10	64403	9524	0	0
T15	82348	0	0	0
T16	0	13115	0	0
T25	1269	0	0	0
T26	782859	350251	0	0
T42	0	68088	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	83078032	0	0
T1	400453	127897	0	0
T2	434329	215823	0	0
T3	95517	9953	0	0
T4	967	1	0	0
T5	3254	124	0	0
T6	470651	136014	0	0
T10	64403	9524	0	0
T15	82348	0	0	0
T16	0	13115	0	0
T25	1269	0	0	0
T26	782859	350251	0	0
T42	0	68088	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	41309710	0	0
T1	400453	524288	0	0
T2	434329	779	0	0
T3	95517	50	0	0
T4	967	2	0	0
T5	3254	16	0	0
T6	470651	45196	0	0
T10	64403	0	0	0
T15	82348	0	0	0
T16	0	17193	0	0
T21	0	35	0	0
T25	1269	0	0	0
T26	782859	403200	0	0
T42	0	258	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	88756482	0	0
T1	400453	127897	0	0
T2	434329	215823	0	0
T3	95517	9953	0	0
T4	967	1	0	0
T5	3254	124	0	0
T6	470651	159332	0	0
T10	64403	9524	0	0
T15	82348	0	0	0
T16	0	15889	0	0
T25	1269	0	0	0
T26	782859	350251	0	0
T42	0	68088	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	83078032	0	0
T1	400453	127897	0	0
T2	434329	215823	0	0
T3	95517	9953	0	0
T4	967	1	0	0
T5	3254	124	0	0
T6	470651	136014	0	0
T10	64403	9524	0	0
T15	82348	0	0	0
T16	0	13115	0	0
T25	1269	0	0	0
T26	782859	350251	0	0
T42	0	68088	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	83078032	0	0
T1	400453	127897	0	0
T2	434329	215823	0	0
T3	95517	9953	0	0
T4	967	1	0	0
T5	3254	124	0	0
T6	470651	136014	0	0
T10	64403	9524	0	0
T15	82348	0	0	0
T16	0	13115	0	0
T25	1269	0	0	0
T26	782859	350251	0	0
T42	0	68088	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	88756482	0	0
T1	400453	127897	0	0
T2	434329	215823	0	0
T3	95517	9953	0	0
T4	967	1	0	0
T5	3254	124	0	0
T6	470651	159332	0	0
T10	64403	9524	0	0
T15	82348	0	0	0
T16	0	15889	0	0
T25	1269	0	0	0
T26	782859	350251	0	0
T42	0	68088	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0