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Module Instance : tb.dut.u_reg_core.u_std_fault_status_storage_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
65.24 85.71 50.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.59 77.78 50.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg_core.u_std_fault_status_phy_fsm_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.67 100.00 50.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.96 88.89 50.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg_core.u_std_fault_status_ctrl_cnt_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.67 100.00 50.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.96 88.89 50.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg_core.u_std_fault_status_fifo_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.67 100.00 50.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.96 88.89 50.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg_core.u_fault_status_op_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 88.89 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg_core.u_fault_status_mp_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 88.89 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg_core.u_fault_status_rd_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 88.89 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg_core.u_fault_status_prog_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 88.89 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg_core.u_fault_status_prog_win_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 88.89 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg_core.u_fault_status_prog_type_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 88.89 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg_core.u_fault_status_seed_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 88.89 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg_core.u_fault_status_phy_relbl_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.22 100.00 91.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 95.00 100.00 90.00


Module Instance : tb.dut.u_reg_core.u_fault_status_phy_storage_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.22 100.00 91.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 95.00 100.00 90.00


Module Instance : tb.dut.u_reg_core.u_fault_status_spurious_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 88.89 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg_core.u_fault_status_arb_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 88.89 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg_core.u_fault_status_host_gnt_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 88.89 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg_core.u_err_addr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_core.u_ecc_single_err_addr_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg_core.u_ecc_single_err_addr_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg_core.u_phy_alert_cfg_alert_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
65.24 85.71 50.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
65.34 88.89 50.00 57.14


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 66.67 100.00 50.00 50.00


Module Instance : tb.dut.u_reg_core.u_phy_alert_cfg_alert_trig

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
65.24 85.71 50.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
65.34 88.89 50.00 57.14


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 66.67 100.00 50.00 50.00


Module Instance : tb.dut.u_reg_core.u_phy_status_init_wip

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
65.24 85.71 50.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.59 77.78 50.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg_core.u_phy_status_prog_normal_avail

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
65.24 85.71 50.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
58.89 66.67 50.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.82 100.00 99.27 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 0.00 0.00

Go back
Module Instances:
tb.dut.u_reg_core.u_std_fault_status_storage_err
tb.dut.u_reg_core.u_std_fault_status_phy_fsm_err
tb.dut.u_reg_core.u_std_fault_status_ctrl_cnt_err
tb.dut.u_reg_core.u_std_fault_status_fifo_err
tb.dut.u_reg_core.u_fault_status_op_err
tb.dut.u_reg_core.u_fault_status_mp_err
tb.dut.u_reg_core.u_fault_status_rd_err
tb.dut.u_reg_core.u_fault_status_prog_err
tb.dut.u_reg_core.u_fault_status_prog_win_err
tb.dut.u_reg_core.u_fault_status_prog_type_err
tb.dut.u_reg_core.u_fault_status_seed_err
tb.dut.u_reg_core.u_fault_status_phy_relbl_err
tb.dut.u_reg_core.u_fault_status_phy_storage_err
tb.dut.u_reg_core.u_fault_status_spurious_ack
tb.dut.u_reg_core.u_fault_status_arb_err
tb.dut.u_reg_core.u_fault_status_host_gnt_err
tb.dut.u_reg_core.u_err_addr
tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_0
tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_1
tb.dut.u_reg_core.u_ecc_single_err_addr_0
tb.dut.u_reg_core.u_ecc_single_err_addr_1
tb.dut.u_reg_core.u_phy_alert_cfg_alert_ack
tb.dut.u_reg_core.u_phy_alert_cfg_alert_trig
tb.dut.u_reg_core.u_phy_status_init_wip
tb.dut.u_reg_core.u_phy_status_prog_normal_avail
Line Coverage for Instance : tb.dut.u_reg_core.u_std_fault_status_storage_err
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS564375.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 0 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_std_fault_status_storage_err
TotalCoveredPercent
Conditions2150.00
Logical2150.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Branch Coverage for Instance : tb.dut.u_reg_core.u_std_fault_status_storage_err
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_std_fault_status_phy_fsm_err
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_std_fault_status_phy_fsm_err
TotalCoveredPercent
Conditions2150.00
Logical2150.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Branch Coverage for Instance : tb.dut.u_reg_core.u_std_fault_status_phy_fsm_err
Line No.TotalCoveredPercent
Branches 5 4 80.00
TERNARY 64 2 1 50.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T20,T23,T24
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_std_fault_status_ctrl_cnt_err
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_std_fault_status_ctrl_cnt_err
TotalCoveredPercent
Conditions2150.00
Logical2150.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Branch Coverage for Instance : tb.dut.u_reg_core.u_std_fault_status_ctrl_cnt_err
Line No.TotalCoveredPercent
Branches 5 4 80.00
TERNARY 64 2 1 50.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T20,T23,T24
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_std_fault_status_fifo_err
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_std_fault_status_fifo_err
TotalCoveredPercent
Conditions2150.00
Logical2150.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Branch Coverage for Instance : tb.dut.u_reg_core.u_std_fault_status_fifo_err
Line No.TotalCoveredPercent
Branches 5 4 80.00
TERNARY 64 2 1 50.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T20,T23,T24
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_op_err
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_fault_status_op_err
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT102,T65,T66
Branch Coverage for Instance : tb.dut.u_reg_core.u_fault_status_op_err
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T102,T65,T66
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T102,T65,T66
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_mp_err
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_fault_status_mp_err
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT115,T74,T116
Branch Coverage for Instance : tb.dut.u_reg_core.u_fault_status_mp_err
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T115,T74,T116
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T115,T74,T116
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_rd_err
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_fault_status_rd_err
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT79,T75,T105
Branch Coverage for Instance : tb.dut.u_reg_core.u_fault_status_rd_err
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T79,T75,T105
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T79,T75,T105
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_prog_err
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_fault_status_prog_err
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT115,T116,T126
Branch Coverage for Instance : tb.dut.u_reg_core.u_fault_status_prog_err
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T115,T116,T126
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T115,T116,T126
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_prog_win_err
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_fault_status_prog_win_err
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT333,T334,T335
Branch Coverage for Instance : tb.dut.u_reg_core.u_fault_status_prog_win_err
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T333,T334,T335
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T20,T23,T24
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_prog_type_err
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_fault_status_prog_type_err
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT36,T336,T337
Branch Coverage for Instance : tb.dut.u_reg_core.u_fault_status_prog_type_err
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T36,T336,T337
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T36,T20,T23
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_seed_err
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_fault_status_seed_err
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT102,T79,T75
Branch Coverage for Instance : tb.dut.u_reg_core.u_fault_status_seed_err
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T102,T79,T75
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T102,T79,T75
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_phy_relbl_err
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_fault_status_phy_relbl_err
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T90,T47
Branch Coverage for Instance : tb.dut.u_reg_core.u_fault_status_phy_relbl_err
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T11,T90,T47
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T11,T90,T47
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_phy_storage_err
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_fault_status_phy_storage_err
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T79,T103
Branch Coverage for Instance : tb.dut.u_reg_core.u_fault_status_phy_storage_err
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T22,T79,T103
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T22,T79,T103
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_spurious_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_fault_status_spurious_ack
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T142,T127
Branch Coverage for Instance : tb.dut.u_reg_core.u_fault_status_spurious_ack
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T4,T142,T127
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T4,T142,T20
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_arb_err
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_fault_status_arb_err
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT158,T96,T156
Branch Coverage for Instance : tb.dut.u_reg_core.u_fault_status_arb_err
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T158,T96,T156
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T158,T96,T20
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_host_gnt_err
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_fault_status_host_gnt_err
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT20,T23,T24
Branch Coverage for Instance : tb.dut.u_reg_core.u_fault_status_host_gnt_err
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T20,T23,T24
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T20,T23,T24
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_err_addr
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_err_addr
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T6,T49
Branch Coverage for Instance : tb.dut.u_reg_core.u_err_addr
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T2,T6,T49
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T6,T49
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT89,T50,T47
Branch Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T89,T50,T47
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T89,T50,T47
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT90,T50,T48
Branch Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T90,T50,T48
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T90,T50,T48
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_addr_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_addr_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT89,T50,T47
Branch Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_addr_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T89,T50,T47
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T89,T50,T47
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_addr_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_addr_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT90,T50,T48
Branch Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_addr_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T90,T50,T48
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T90,T50,T48
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_phy_alert_cfg_alert_ack
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS564375.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 0 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_phy_alert_cfg_alert_ack
TotalCoveredPercent
Conditions2150.00
Logical2150.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Branch Coverage for Instance : tb.dut.u_reg_core.u_phy_alert_cfg_alert_ack
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_phy_alert_cfg_alert_trig
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS564375.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 0 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_phy_alert_cfg_alert_trig
TotalCoveredPercent
Conditions2150.00
Logical2150.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Branch Coverage for Instance : tb.dut.u_reg_core.u_phy_alert_cfg_alert_trig
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_phy_status_init_wip
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 1 1
65 0 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_phy_status_init_wip
TotalCoveredPercent
Conditions2150.00
Logical2150.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_reg_core.u_phy_status_init_wip
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.u_reg_core.u_phy_status_prog_normal_avail
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 1 1
65 0 1
72 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_phy_status_prog_normal_avail
TotalCoveredPercent
Conditions2150.00
Logical2150.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_reg_core.u_phy_status_prog_normal_avail
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%