Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_to_prog_fifo.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	100.00	75.00			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.89	100.00	65.22			85.71	84.62	u_to_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	90.30	100.00	80.00			90.91

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	351747725	31755576	0	0
DepthKnown_A	351747725	351051036	0	0
RvalidKnown_A	351747725	351051036	0	0
WreadyKnown_A	351747725	351051036	0	0
gen_passthru_fifo.paramCheckPass	1090	1090	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	31755576	0	0
T1	400453	392	0	0
T2	434329	216524	0	0
T3	95517	4559	0	0
T4	967	160	0	0
T5	3254	214	0	0
T6	470651	239155	0	0
T10	64403	9058	0	0
T15	82348	10688	0	0
T25	1269	19	0	0
T26	782859	930144	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1090	1090	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	351747725	36031537	0	0
DepthKnown_A	351747725	351051036	0	0
RvalidKnown_A	351747725	351051036	0	0
WreadyKnown_A	351747725	351051036	0	0
gen_passthru_fifo.paramCheckPass	1090	1090	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	36031537	0	0
T1	400453	1166	0	0
T2	434329	216524	0	0
T3	95517	20662	0	0
T4	967	156	0	0
T5	3254	647	0	0
T6	470651	228825	0	0
T10	64403	9058	0	0
T15	82348	10688	0	0
T25	1269	19	0	0
T26	782859	930144	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1090	1090	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	351747725	2025096	0	0
DepthKnown_A	351747725	351051036	0	0
RvalidKnown_A	351747725	351051036	0	0
WreadyKnown_A	351747725	351051036	0	0
gen_passthru_fifo.paramCheckPass	1090	1090	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	2025096	0	0
T2	434329	1121	0	0
T3	95517	164	0	0
T4	967	10	0	0
T5	3254	3	0	0
T6	470651	17628	0	0
T10	64403	1512	0	0
T15	82348	592	0	0
T25	1269	0	0	0
T26	782859	137728	0	0
T49	187575	5321	0	0
T73	0	17184	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1090	1090	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	351747725	2381855	0	0
DepthKnown_A	351747725	351051036	0	0
RvalidKnown_A	351747725	351051036	0	0
WreadyKnown_A	351747725	351051036	0	0
gen_passthru_fifo.paramCheckPass	1090	1090	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	2381855	0	0
T2	434329	1121	0	0
T3	95517	699	0	0
T4	967	10	0	0
T5	3254	3	0	0
T6	470651	17628	0	0
T10	64403	1512	0	0
T15	82348	592	0	0
T25	1269	0	0	0
T26	782859	137728	0	0
T49	187575	18466	0	0
T73	0	4608	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1090	1090	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	351747725	3856818	0	0
DepthKnown_A	351747725	351051036	0	0
RvalidKnown_A	351747725	351051036	0	0
WreadyKnown_A	351747725	351051036	0	0
gen_passthru_fifo.paramCheckPass	1090	1090	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	3856818	0	0
T2	434329	1041	0	0
T3	95517	42	0	0
T4	967	0	0	0
T5	3254	34	0	0
T6	470651	23606	0	0
T10	64403	0	0	0
T15	82348	1168	0	0
T16	0	19920	0	0
T25	1269	0	0	0
T26	782859	137728	0	0
T42	0	359	0	0
T49	187575	5632	0	0
T73	0	8192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1090	1090	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	351747725	4047112	0	0
DepthKnown_A	351747725	351051036	0	0
RvalidKnown_A	351747725	351051036	0	0
WreadyKnown_A	351747725	351051036	0	0
gen_passthru_fifo.paramCheckPass	1090	1090	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	4047112	0	0
T2	434329	1041	0	0
T3	95517	205	0	0
T4	967	0	0	0
T5	3254	101	0	0
T6	470651	13276	0	0
T10	64403	0	0	0
T15	82348	1168	0	0
T16	0	11132	0	0
T25	1269	0	0	0
T26	782859	137728	0	0
T42	0	172	0	0
T49	187575	25639	0	0
T73	0	8192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1090	1090	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	351747725	25853384	0	0
DepthKnown_A	351747725	351051036	0	0
RvalidKnown_A	351747725	351051036	0	0
WreadyKnown_A	351747725	351051036	0	0
gen_passthru_fifo.paramCheckPass	1090	1090	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	25853384	0	0
T1	400453	392	0	0
T2	434329	214362	0	0
T3	95517	4353	0	0
T4	967	150	0	0
T5	3254	177	0	0
T6	470651	197921	0	0
T10	64403	7546	0	0
T15	82348	8928	0	0
T25	1269	19	0	0
T26	782859	654688	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1090	1090	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	351747725	29602570	0	0
DepthKnown_A	351747725	351051036	0	0
RvalidKnown_A	351747725	351051036	0	0
WreadyKnown_A	351747725	351051036	0	0
gen_passthru_fifo.paramCheckPass	1090	1090	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	29602570	0	0
T1	400453	1166	0	0
T2	434329	214362	0	0
T3	95517	19758	0	0
T4	967	146	0	0
T5	3254	543	0	0
T6	470651	197921	0	0
T10	64403	7546	0	0
T15	82348	8928	0	0
T25	1269	19	0	0
T26	782859	654688	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351747725	351051036	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1090	1090	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T5,T15
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	348705990	2374566	0	0
DepthKnown_A	348705990	348098510	0	0
RvalidKnown_A	348705990	348098510	0	0
WreadyKnown_A	348705990	348098510	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	348705990	2374566	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	2374566	0	0
T2	434329	1121	0	0
T3	95517	699	0	0
T4	967	10	0	0
T5	3254	3	0	0
T6	470651	17628	0	0
T10	64403	1512	0	0
T15	82348	592	0	0
T25	1269	0	0	0
T26	782859	137728	0	0
T49	187575	18466	0	0
T73	0	4608	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	2374566	0	0
T2	434329	1121	0	0
T3	95517	699	0	0
T4	967	10	0	0
T5	3254	3	0	0
T6	470651	17628	0	0
T10	64403	1512	0	0
T15	82348	592	0	0
T25	1269	0	0	0
T26	782859	137728	0	0
T49	187575	18466	0	0
T73	0	4608	0	0