Unified Coverage Report :: Module Instance :: tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.41	100.00	82.05	90.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.41	100.00	89.65			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	95.33	100.00	91.30	90.00		100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.87	100.00	74.36	90.00		90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.41	100.00	89.65			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	84.82	100.00	82.61	90.00		66.67

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	80.56			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.41	100.00	89.65			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T64,T33
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	348705990	47417635	0	0
DepthKnown_A	348705990	348098510	0	0
RvalidKnown_A	348705990	348098510	0	0
WreadyKnown_A	348705990	348098510	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	348705990	47417635	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	47417635	0	0
T1	400453	524288	0	0
T2	434329	779	0	0
T3	95517	50	0	0
T4	967	2	0	0
T5	3254	16	0	0
T6	470651	69713	0	0
T10	64403	0	0	0
T15	82348	0	0	0
T16	0	24113	0	0
T21	0	35	0	0
T25	1269	0	0	0
T26	782859	403200	0	0
T42	0	258	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	47417635	0	0
T1	400453	524288	0	0
T2	434329	779	0	0
T3	95517	50	0	0
T4	967	2	0	0
T5	3254	16	0	0
T6	470651	69713	0	0
T10	64403	0	0	0
T15	82348	0	0	0
T16	0	24113	0	0
T21	0	35	0	0
T25	1269	0	0	0
T26	782859	403200	0	0
T42	0	258	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T6,T42
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	348705990	12036479	0	0
DepthKnown_A	348705990	348098510	0	0
RvalidKnown_A	348705990	348098510	0	0
WreadyKnown_A	348705990	348098510	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	348705990	12036479	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	12036479	0	0
T1	400453	262144	0	0
T2	434329	273	0	0
T3	95517	25	0	0
T4	967	1	0	0
T5	3254	6	0	0
T6	470651	38818	0	0
T10	64403	0	0	0
T15	82348	0	0	0
T16	0	10998	0	0
T21	0	12	0	0
T25	1269	0	0	0
T26	782859	134400	0	0
T42	0	102	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	12036479	0	0
T1	400453	262144	0	0
T2	434329	273	0	0
T3	95517	25	0	0
T4	967	1	0	0
T5	3254	6	0	0
T6	470651	38818	0	0
T10	64403	0	0	0
T15	82348	0	0	0
T16	0	10998	0	0
T21	0	12	0	0
T25	1269	0	0	0
T26	782859	134400	0	0
T42	0	102	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T5
1	0	1	Covered	T1,T6,T42
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T6

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	348705990	10965716	0	0
DepthKnown_A	348705990	348098510	0	0
RvalidKnown_A	348705990	348098510	0	0
WreadyKnown_A	348705990	348098510	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	348705990	10965716	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	10965716	0	0
T1	400453	262144	0	0
T2	434329	0	0	0
T3	95517	0	0	0
T4	967	1	0	0
T5	3254	0	0	0
T6	470651	44569	0	0
T10	64403	0	0	0
T11	0	54	0	0
T13	0	22874	0	0
T15	82348	0	0	0
T17	0	10087	0	0
T25	1269	0	0	0
T26	782859	0	0	0
T27	0	262144	0	0
T33	0	42942	0	0
T42	0	74	0	0
T92	0	11673	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	348098510	0	0
T1	400453	400435	0	0
T2	434329	434232	0	0
T3	95517	95384	0	0
T4	967	822	0	0
T5	3254	3167	0	0
T6	470651	470596	0	0
T10	64403	64352	0	0
T15	82348	78546	0	0
T25	1269	1199	0	0
T26	782859	782851	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	348705990	10965716	0	0
T1	400453	262144	0	0
T2	434329	0	0	0
T3	95517	0	0	0
T4	967	1	0	0
T5	3254	0	0	0
T6	470651	44569	0	0
T10	64403	0	0	0
T11	0	54	0	0
T13	0	22874	0	0
T15	82348	0	0	0
T17	0	10087	0	0
T25	1269	0	0	0
T26	782859	0	0	0
T27	0	262144	0	0
T33	0	42942	0	0
T42	0	74	0	0
T92	0	11673	0	0