| T411 |
/workspace/coverage/default/26.flash_ctrl_sec_info_access.4165924720 |
|
|
Apr 30 02:33:02 PM PDT 24 |
Apr 30 02:34:27 PM PDT 24 |
10623057000 ps |
| T111 |
/workspace/coverage/default/0.flash_ctrl_rma_err.1460678582 |
|
|
Apr 30 02:26:17 PM PDT 24 |
Apr 30 02:46:26 PM PDT 24 |
73591619700 ps |
| T864 |
/workspace/coverage/default/55.flash_ctrl_connect.3775753595 |
|
|
Apr 30 02:35:01 PM PDT 24 |
Apr 30 02:35:15 PM PDT 24 |
48505800 ps |
| T865 |
/workspace/coverage/default/23.flash_ctrl_otp_reset.2239257848 |
|
|
Apr 30 02:32:28 PM PDT 24 |
Apr 30 02:34:18 PM PDT 24 |
37905000 ps |
| T46 |
/workspace/coverage/default/2.flash_ctrl_wr_intg.2500703343 |
|
|
Apr 30 02:27:18 PM PDT 24 |
Apr 30 02:27:34 PM PDT 24 |
85822400 ps |
| T866 |
/workspace/coverage/default/25.flash_ctrl_otp_reset.1289616538 |
|
|
Apr 30 02:32:46 PM PDT 24 |
Apr 30 02:34:57 PM PDT 24 |
95141900 ps |
| T867 |
/workspace/coverage/default/0.flash_ctrl_rand_ops.3899096180 |
|
|
Apr 30 02:25:52 PM PDT 24 |
Apr 30 02:27:40 PM PDT 24 |
66416300 ps |
| T868 |
/workspace/coverage/default/14.flash_ctrl_hw_sec_otp.1160092482 |
|
|
Apr 30 02:30:34 PM PDT 24 |
Apr 30 02:32:09 PM PDT 24 |
20848005500 ps |
| T869 |
/workspace/coverage/default/30.flash_ctrl_alert_test.3258174444 |
|
|
Apr 30 02:33:26 PM PDT 24 |
Apr 30 02:33:41 PM PDT 24 |
139937100 ps |
| T870 |
/workspace/coverage/default/42.flash_ctrl_hw_sec_otp.2778273927 |
|
|
Apr 30 02:34:30 PM PDT 24 |
Apr 30 02:36:19 PM PDT 24 |
7094563800 ps |
| T871 |
/workspace/coverage/default/4.flash_ctrl_sw_op.2370013213 |
|
|
Apr 30 02:27:44 PM PDT 24 |
Apr 30 02:28:12 PM PDT 24 |
126124600 ps |
| T872 |
/workspace/coverage/default/25.flash_ctrl_smoke.1254420502 |
|
|
Apr 30 02:32:48 PM PDT 24 |
Apr 30 02:34:47 PM PDT 24 |
47429200 ps |
| T873 |
/workspace/coverage/default/69.flash_ctrl_connect.2067455078 |
|
|
Apr 30 02:35:20 PM PDT 24 |
Apr 30 02:35:36 PM PDT 24 |
28241700 ps |
| T874 |
/workspace/coverage/default/13.flash_ctrl_hw_sec_otp.3250701843 |
|
|
Apr 30 02:30:20 PM PDT 24 |
Apr 30 02:31:47 PM PDT 24 |
1664876400 ps |
| T875 |
/workspace/coverage/default/11.flash_ctrl_invalid_op.364098171 |
|
|
Apr 30 02:29:50 PM PDT 24 |
Apr 30 02:31:08 PM PDT 24 |
3383944000 ps |
| T194 |
/workspace/coverage/default/4.flash_ctrl_ro_derr.1474576404 |
|
|
Apr 30 02:27:50 PM PDT 24 |
Apr 30 02:30:55 PM PDT 24 |
955857500 ps |
| T876 |
/workspace/coverage/default/38.flash_ctrl_intr_rd.2709279663 |
|
|
Apr 30 02:34:04 PM PDT 24 |
Apr 30 02:37:28 PM PDT 24 |
8056617100 ps |
| T877 |
/workspace/coverage/default/30.flash_ctrl_smoke.2916497470 |
|
|
Apr 30 02:33:26 PM PDT 24 |
Apr 30 02:35:50 PM PDT 24 |
76579700 ps |
| T878 |
/workspace/coverage/default/12.flash_ctrl_rw.1451741178 |
|
|
Apr 30 02:30:14 PM PDT 24 |
Apr 30 02:43:12 PM PDT 24 |
58456549700 ps |
| T879 |
/workspace/coverage/default/16.flash_ctrl_intr_rd.3866896165 |
|
|
Apr 30 02:31:14 PM PDT 24 |
Apr 30 02:34:34 PM PDT 24 |
2430271800 ps |
| T880 |
/workspace/coverage/default/76.flash_ctrl_otp_reset.596301607 |
|
|
Apr 30 02:35:27 PM PDT 24 |
Apr 30 02:37:20 PM PDT 24 |
485930000 ps |
| T881 |
/workspace/coverage/default/40.flash_ctrl_sec_info_access.2599281612 |
|
|
Apr 30 02:34:24 PM PDT 24 |
Apr 30 02:36:16 PM PDT 24 |
31653581000 ps |
| T882 |
/workspace/coverage/default/12.flash_ctrl_lcmgr_intg.350021465 |
|
|
Apr 30 02:30:19 PM PDT 24 |
Apr 30 02:30:51 PM PDT 24 |
47533900 ps |
| T883 |
/workspace/coverage/default/45.flash_ctrl_otp_reset.1881002275 |
|
|
Apr 30 02:34:35 PM PDT 24 |
Apr 30 02:36:30 PM PDT 24 |
46697800 ps |
| T884 |
/workspace/coverage/default/24.flash_ctrl_sec_info_access.2970273837 |
|
|
Apr 30 02:32:47 PM PDT 24 |
Apr 30 02:34:00 PM PDT 24 |
3743522400 ps |
| T335 |
/workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.411149213 |
|
|
Apr 30 02:29:42 PM PDT 24 |
Apr 30 02:30:47 PM PDT 24 |
10039914000 ps |
| T885 |
/workspace/coverage/default/35.flash_ctrl_otp_reset.398366123 |
|
|
Apr 30 02:33:53 PM PDT 24 |
Apr 30 02:36:07 PM PDT 24 |
156878000 ps |
| T886 |
/workspace/coverage/default/45.flash_ctrl_hw_sec_otp.3708597700 |
|
|
Apr 30 02:34:38 PM PDT 24 |
Apr 30 02:37:42 PM PDT 24 |
12537536000 ps |
| T385 |
/workspace/coverage/default/4.flash_ctrl_disable.934317584 |
|
|
Apr 30 02:27:57 PM PDT 24 |
Apr 30 02:28:20 PM PDT 24 |
33232900 ps |
| T887 |
/workspace/coverage/default/3.flash_ctrl_ro_serr.3101002717 |
|
|
Apr 30 02:27:36 PM PDT 24 |
Apr 30 02:30:23 PM PDT 24 |
3921041100 ps |
| T888 |
/workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.894533668 |
|
|
Apr 30 02:31:27 PM PDT 24 |
Apr 30 02:31:58 PM PDT 24 |
15756700 ps |
| T889 |
/workspace/coverage/default/66.flash_ctrl_otp_reset.3202554551 |
|
|
Apr 30 02:35:10 PM PDT 24 |
Apr 30 02:36:59 PM PDT 24 |
127525500 ps |
| T890 |
/workspace/coverage/default/46.flash_ctrl_sec_info_access.2244072586 |
|
|
Apr 30 02:34:42 PM PDT 24 |
Apr 30 02:35:57 PM PDT 24 |
4229883800 ps |
| T891 |
/workspace/coverage/default/44.flash_ctrl_otp_reset.2763854153 |
|
|
Apr 30 02:34:27 PM PDT 24 |
Apr 30 02:36:39 PM PDT 24 |
432117100 ps |
| T892 |
/workspace/coverage/default/32.flash_ctrl_alert_test.2532089916 |
|
|
Apr 30 02:33:35 PM PDT 24 |
Apr 30 02:33:50 PM PDT 24 |
69430700 ps |
| T893 |
/workspace/coverage/default/3.flash_ctrl_disable.2562757901 |
|
|
Apr 30 02:27:35 PM PDT 24 |
Apr 30 02:27:58 PM PDT 24 |
28219300 ps |
| T894 |
/workspace/coverage/default/23.flash_ctrl_disable.2950401705 |
|
|
Apr 30 02:32:42 PM PDT 24 |
Apr 30 02:33:05 PM PDT 24 |
90003300 ps |
| T895 |
/workspace/coverage/default/21.flash_ctrl_smoke.1148172565 |
|
|
Apr 30 02:32:13 PM PDT 24 |
Apr 30 02:34:46 PM PDT 24 |
163577800 ps |
| T896 |
/workspace/coverage/default/32.flash_ctrl_sec_info_access.2694079452 |
|
|
Apr 30 02:33:35 PM PDT 24 |
Apr 30 02:34:47 PM PDT 24 |
4912975100 ps |
| T157 |
/workspace/coverage/default/1.flash_ctrl_phy_arb_redun.3254137252 |
|
|
Apr 30 02:26:56 PM PDT 24 |
Apr 30 02:27:14 PM PDT 24 |
913147000 ps |
| T176 |
/workspace/coverage/default/1.flash_ctrl_ro_serr.1911179651 |
|
|
Apr 30 02:26:39 PM PDT 24 |
Apr 30 02:29:10 PM PDT 24 |
6100082800 ps |
| T177 |
/workspace/coverage/default/13.flash_ctrl_re_evict.3238627168 |
|
|
Apr 30 02:30:34 PM PDT 24 |
Apr 30 02:31:30 PM PDT 24 |
110821600 ps |
| T178 |
/workspace/coverage/default/25.flash_ctrl_intr_rd.23673664 |
|
|
Apr 30 02:32:46 PM PDT 24 |
Apr 30 02:35:44 PM PDT 24 |
11294933100 ps |
| T179 |
/workspace/coverage/default/11.flash_ctrl_sec_info_access.975388916 |
|
|
Apr 30 02:29:59 PM PDT 24 |
Apr 30 02:31:28 PM PDT 24 |
12348105800 ps |
| T180 |
/workspace/coverage/default/11.flash_ctrl_alert_test.575563165 |
|
|
Apr 30 02:29:58 PM PDT 24 |
Apr 30 02:30:24 PM PDT 24 |
32048600 ps |
| T181 |
/workspace/coverage/default/22.flash_ctrl_intr_rd.896545979 |
|
|
Apr 30 02:32:30 PM PDT 24 |
Apr 30 02:35:33 PM PDT 24 |
13813811900 ps |
| T182 |
/workspace/coverage/default/20.flash_ctrl_sec_info_access.1571873421 |
|
|
Apr 30 02:32:09 PM PDT 24 |
Apr 30 02:33:29 PM PDT 24 |
2736396000 ps |
| T183 |
/workspace/coverage/default/4.flash_ctrl_sec_info_access.2918775132 |
|
|
Apr 30 02:27:55 PM PDT 24 |
Apr 30 02:29:04 PM PDT 24 |
1845238300 ps |
| T184 |
/workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.4102644733 |
|
|
Apr 30 02:32:05 PM PDT 24 |
Apr 30 02:32:29 PM PDT 24 |
15772800 ps |
| T159 |
/workspace/coverage/default/3.flash_ctrl_phy_arb_redun.2702885311 |
|
|
Apr 30 02:27:44 PM PDT 24 |
Apr 30 02:28:09 PM PDT 24 |
644555200 ps |
| T384 |
/workspace/coverage/default/27.flash_ctrl_disable.3174169095 |
|
|
Apr 30 02:33:00 PM PDT 24 |
Apr 30 02:33:23 PM PDT 24 |
16148700 ps |
| T897 |
/workspace/coverage/default/9.flash_ctrl_hw_sec_otp.1682777519 |
|
|
Apr 30 02:29:18 PM PDT 24 |
Apr 30 02:30:28 PM PDT 24 |
6914443400 ps |
| T189 |
/workspace/coverage/default/1.flash_ctrl_ro_derr.717470902 |
|
|
Apr 30 02:26:44 PM PDT 24 |
Apr 30 02:29:21 PM PDT 24 |
1440768600 ps |
| T320 |
/workspace/coverage/default/17.flash_ctrl_hw_sec_otp.2743312547 |
|
|
Apr 30 02:31:25 PM PDT 24 |
Apr 30 02:36:07 PM PDT 24 |
3169252000 ps |
| T321 |
/workspace/coverage/default/77.flash_ctrl_otp_reset.3382814858 |
|
|
Apr 30 02:35:26 PM PDT 24 |
Apr 30 02:37:37 PM PDT 24 |
70297400 ps |
| T322 |
/workspace/coverage/default/46.flash_ctrl_smoke.1157106542 |
|
|
Apr 30 02:34:37 PM PDT 24 |
Apr 30 02:36:39 PM PDT 24 |
95060000 ps |
| T323 |
/workspace/coverage/default/23.flash_ctrl_sec_info_access.1096455164 |
|
|
Apr 30 02:32:43 PM PDT 24 |
Apr 30 02:33:51 PM PDT 24 |
3224338300 ps |
| T324 |
/workspace/coverage/default/36.flash_ctrl_sec_info_access.52743524 |
|
|
Apr 30 02:33:56 PM PDT 24 |
Apr 30 02:35:10 PM PDT 24 |
1766050700 ps |
| T325 |
/workspace/coverage/default/2.flash_ctrl_hw_rma.2005602089 |
|
|
Apr 30 02:27:11 PM PDT 24 |
Apr 30 02:56:48 PM PDT 24 |
85113617700 ps |
| T326 |
/workspace/coverage/default/55.flash_ctrl_otp_reset.1422170683 |
|
|
Apr 30 02:35:01 PM PDT 24 |
Apr 30 02:37:16 PM PDT 24 |
147732200 ps |
| T327 |
/workspace/coverage/default/30.flash_ctrl_intr_rd.462453848 |
|
|
Apr 30 02:33:23 PM PDT 24 |
Apr 30 02:36:14 PM PDT 24 |
4326895700 ps |
| T328 |
/workspace/coverage/default/44.flash_ctrl_sec_info_access.2617647147 |
|
|
Apr 30 02:34:34 PM PDT 24 |
Apr 30 02:36:05 PM PDT 24 |
13497931400 ps |
| T898 |
/workspace/coverage/default/48.flash_ctrl_sec_info_access.631696077 |
|
|
Apr 30 02:34:56 PM PDT 24 |
Apr 30 02:36:08 PM PDT 24 |
3743773800 ps |
| T899 |
/workspace/coverage/default/2.flash_ctrl_alert_test.686728619 |
|
|
Apr 30 02:27:26 PM PDT 24 |
Apr 30 02:27:41 PM PDT 24 |
151303100 ps |
| T900 |
/workspace/coverage/default/33.flash_ctrl_hw_sec_otp.3866512046 |
|
|
Apr 30 02:33:36 PM PDT 24 |
Apr 30 02:34:29 PM PDT 24 |
2001490400 ps |
| T901 |
/workspace/coverage/default/1.flash_ctrl_sw_op.613022583 |
|
|
Apr 30 02:26:19 PM PDT 24 |
Apr 30 02:26:47 PM PDT 24 |
104061700 ps |
| T902 |
/workspace/coverage/default/74.flash_ctrl_connect.570911247 |
|
|
Apr 30 02:35:27 PM PDT 24 |
Apr 30 02:35:43 PM PDT 24 |
30349500 ps |
| T903 |
/workspace/coverage/default/13.flash_ctrl_hw_rma_reset.1391083989 |
|
|
Apr 30 02:30:20 PM PDT 24 |
Apr 30 02:45:48 PM PDT 24 |
160167991700 ps |
| T904 |
/workspace/coverage/default/3.flash_ctrl_error_mp.255017952 |
|
|
Apr 30 02:27:30 PM PDT 24 |
Apr 30 03:04:21 PM PDT 24 |
1780174500 ps |
| T386 |
/workspace/coverage/default/22.flash_ctrl_disable.62695270 |
|
|
Apr 30 02:32:32 PM PDT 24 |
Apr 30 02:32:55 PM PDT 24 |
74704300 ps |
| T905 |
/workspace/coverage/default/8.flash_ctrl_wo.3035275037 |
|
|
Apr 30 02:29:03 PM PDT 24 |
Apr 30 02:33:44 PM PDT 24 |
40658055400 ps |
| T906 |
/workspace/coverage/default/10.flash_ctrl_phy_arb.105394116 |
|
|
Apr 30 02:29:32 PM PDT 24 |
Apr 30 02:38:52 PM PDT 24 |
2121772000 ps |
| T907 |
/workspace/coverage/default/13.flash_ctrl_connect.3716005978 |
|
|
Apr 30 02:30:33 PM PDT 24 |
Apr 30 02:31:08 PM PDT 24 |
62367100 ps |
| T908 |
/workspace/coverage/default/3.flash_ctrl_intr_rd.1609044001 |
|
|
Apr 30 02:27:36 PM PDT 24 |
Apr 30 02:30:48 PM PDT 24 |
1851982000 ps |
| T208 |
/workspace/coverage/default/9.flash_ctrl_ro_derr.2399041095 |
|
|
Apr 30 02:29:23 PM PDT 24 |
Apr 30 02:31:35 PM PDT 24 |
2976699900 ps |
| T909 |
/workspace/coverage/default/4.flash_ctrl_hw_sec_otp.1096526512 |
|
|
Apr 30 02:27:48 PM PDT 24 |
Apr 30 02:28:26 PM PDT 24 |
1851820400 ps |
| T910 |
/workspace/coverage/default/6.flash_ctrl_otp_reset.4200841496 |
|
|
Apr 30 02:28:31 PM PDT 24 |
Apr 30 02:30:41 PM PDT 24 |
297495900 ps |
| T911 |
/workspace/coverage/default/0.flash_ctrl_rw.1910872769 |
|
|
Apr 30 02:25:59 PM PDT 24 |
Apr 30 02:36:08 PM PDT 24 |
8174729800 ps |
| T912 |
/workspace/coverage/default/5.flash_ctrl_connect.2342401207 |
|
|
Apr 30 02:28:23 PM PDT 24 |
Apr 30 02:28:38 PM PDT 24 |
26811200 ps |
| T913 |
/workspace/coverage/default/2.flash_ctrl_error_prog_win.3742933036 |
|
|
Apr 30 02:27:09 PM PDT 24 |
Apr 30 02:41:03 PM PDT 24 |
1420964700 ps |
| T914 |
/workspace/coverage/default/18.flash_ctrl_re_evict.3221767054 |
|
|
Apr 30 02:31:46 PM PDT 24 |
Apr 30 02:32:39 PM PDT 24 |
114139900 ps |
| T915 |
/workspace/coverage/default/2.flash_ctrl_sec_info_access.440448059 |
|
|
Apr 30 02:27:16 PM PDT 24 |
Apr 30 02:28:36 PM PDT 24 |
3647935900 ps |
| T916 |
/workspace/coverage/default/14.flash_ctrl_rand_ops.3171421846 |
|
|
Apr 30 02:30:32 PM PDT 24 |
Apr 30 02:35:25 PM PDT 24 |
43295300 ps |
| T286 |
/workspace/coverage/default/13.flash_ctrl_otp_reset.2737037413 |
|
|
Apr 30 02:30:21 PM PDT 24 |
Apr 30 02:32:53 PM PDT 24 |
414715400 ps |
| T917 |
/workspace/coverage/default/2.flash_ctrl_rd_intg.853106694 |
|
|
Apr 30 02:27:19 PM PDT 24 |
Apr 30 02:27:54 PM PDT 24 |
65052800 ps |
| T918 |
/workspace/coverage/default/32.flash_ctrl_smoke.180184311 |
|
|
Apr 30 02:33:34 PM PDT 24 |
Apr 30 02:35:14 PM PDT 24 |
64596300 ps |
| T919 |
/workspace/coverage/default/56.flash_ctrl_otp_reset.581445389 |
|
|
Apr 30 02:35:02 PM PDT 24 |
Apr 30 02:37:15 PM PDT 24 |
212757900 ps |
| T920 |
/workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.4024208191 |
|
|
Apr 30 02:28:16 PM PDT 24 |
Apr 30 02:32:49 PM PDT 24 |
55478537200 ps |
| T921 |
/workspace/coverage/default/14.flash_ctrl_wo.3319877878 |
|
|
Apr 30 02:30:32 PM PDT 24 |
Apr 30 02:33:52 PM PDT 24 |
2536337200 ps |
| T416 |
/workspace/coverage/default/10.flash_ctrl_invalid_op.3202458793 |
|
|
Apr 30 02:29:37 PM PDT 24 |
Apr 30 02:31:16 PM PDT 24 |
8860585100 ps |
| T922 |
/workspace/coverage/default/2.flash_ctrl_lcmgr_intg.1986210871 |
|
|
Apr 30 02:27:23 PM PDT 24 |
Apr 30 02:27:39 PM PDT 24 |
49983500 ps |
| T923 |
/workspace/coverage/default/36.flash_ctrl_connect.1991657637 |
|
|
Apr 30 02:33:55 PM PDT 24 |
Apr 30 02:34:12 PM PDT 24 |
16095900 ps |
| T924 |
/workspace/coverage/default/3.flash_ctrl_hw_rma_reset.2099607814 |
|
|
Apr 30 02:27:22 PM PDT 24 |
Apr 30 02:45:58 PM PDT 24 |
320244270100 ps |
| T925 |
/workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1752952163 |
|
|
Apr 30 02:32:58 PM PDT 24 |
Apr 30 02:37:16 PM PDT 24 |
37570411800 ps |
| T926 |
/workspace/coverage/default/3.flash_ctrl_connect.4204357573 |
|
|
Apr 30 02:27:43 PM PDT 24 |
Apr 30 02:27:59 PM PDT 24 |
13894200 ps |
| T927 |
/workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.994416887 |
|
|
Apr 30 02:28:49 PM PDT 24 |
Apr 30 02:32:26 PM PDT 24 |
14784009200 ps |
| T928 |
/workspace/coverage/default/41.flash_ctrl_disable.148542350 |
|
|
Apr 30 02:34:29 PM PDT 24 |
Apr 30 02:34:52 PM PDT 24 |
36226600 ps |
| T929 |
/workspace/coverage/default/3.flash_ctrl_error_prog_win.1284602851 |
|
|
Apr 30 02:27:29 PM PDT 24 |
Apr 30 02:42:35 PM PDT 24 |
2410435600 ps |
| T930 |
/workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1182328620 |
|
|
Apr 30 02:29:12 PM PDT 24 |
Apr 30 02:33:10 PM PDT 24 |
14224474000 ps |
| T931 |
/workspace/coverage/default/60.flash_ctrl_connect.194710572 |
|
|
Apr 30 02:35:08 PM PDT 24 |
Apr 30 02:35:25 PM PDT 24 |
15916200 ps |
| T932 |
/workspace/coverage/default/29.flash_ctrl_alert_test.1161881653 |
|
|
Apr 30 02:33:26 PM PDT 24 |
Apr 30 02:33:40 PM PDT 24 |
62752200 ps |
| T200 |
/workspace/coverage/default/0.flash_ctrl_rd_intg.50372300 |
|
|
Apr 30 02:26:12 PM PDT 24 |
Apr 30 02:26:45 PM PDT 24 |
68251200 ps |
| T933 |
/workspace/coverage/default/29.flash_ctrl_sec_info_access.2693810113 |
|
|
Apr 30 02:33:26 PM PDT 24 |
Apr 30 02:34:36 PM PDT 24 |
6481586400 ps |
| T934 |
/workspace/coverage/default/17.flash_ctrl_rand_ops.221145769 |
|
|
Apr 30 02:31:28 PM PDT 24 |
Apr 30 02:35:26 PM PDT 24 |
33910200 ps |
| T287 |
/workspace/coverage/default/0.flash_ctrl_otp_reset.362741161 |
|
|
Apr 30 02:25:56 PM PDT 24 |
Apr 30 02:28:07 PM PDT 24 |
61896100 ps |
| T935 |
/workspace/coverage/default/29.flash_ctrl_connect.2602844614 |
|
|
Apr 30 02:33:26 PM PDT 24 |
Apr 30 02:33:40 PM PDT 24 |
17101100 ps |
| T936 |
/workspace/coverage/default/25.flash_ctrl_hw_sec_otp.94371235 |
|
|
Apr 30 02:32:47 PM PDT 24 |
Apr 30 02:33:47 PM PDT 24 |
1789673000 ps |
| T937 |
/workspace/coverage/default/70.flash_ctrl_otp_reset.3808394736 |
|
|
Apr 30 02:35:21 PM PDT 24 |
Apr 30 02:37:32 PM PDT 24 |
76449700 ps |
| T938 |
/workspace/coverage/default/47.flash_ctrl_otp_reset.2286452926 |
|
|
Apr 30 02:34:42 PM PDT 24 |
Apr 30 02:36:35 PM PDT 24 |
82989700 ps |
| T939 |
/workspace/coverage/default/24.flash_ctrl_smoke.1291131870 |
|
|
Apr 30 02:32:41 PM PDT 24 |
Apr 30 02:34:22 PM PDT 24 |
21156700 ps |
| T940 |
/workspace/coverage/default/7.flash_ctrl_rand_ops.3591285153 |
|
|
Apr 30 02:28:42 PM PDT 24 |
Apr 30 02:30:58 PM PDT 24 |
146354700 ps |
| T941 |
/workspace/coverage/default/40.flash_ctrl_hw_sec_otp.2996933771 |
|
|
Apr 30 02:34:24 PM PDT 24 |
Apr 30 02:37:28 PM PDT 24 |
2282325900 ps |
| T403 |
/workspace/coverage/default/27.flash_ctrl_sec_info_access.1523787812 |
|
|
Apr 30 02:33:00 PM PDT 24 |
Apr 30 02:34:10 PM PDT 24 |
6562005100 ps |
| T308 |
/workspace/coverage/default/13.flash_ctrl_rw.658696770 |
|
|
Apr 30 02:30:27 PM PDT 24 |
Apr 30 02:39:38 PM PDT 24 |
4361643800 ps |
| T942 |
/workspace/coverage/default/49.flash_ctrl_hw_sec_otp.3621178456 |
|
|
Apr 30 02:34:54 PM PDT 24 |
Apr 30 02:36:00 PM PDT 24 |
6815601700 ps |
| T112 |
/workspace/coverage/default/1.flash_ctrl_rma_err.208285407 |
|
|
Apr 30 02:27:00 PM PDT 24 |
Apr 30 02:42:57 PM PDT 24 |
46756274200 ps |
| T943 |
/workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2973967136 |
|
|
Apr 30 02:32:30 PM PDT 24 |
Apr 30 02:35:39 PM PDT 24 |
7360408400 ps |
| T944 |
/workspace/coverage/default/3.flash_ctrl_ro.3396216914 |
|
|
Apr 30 02:27:35 PM PDT 24 |
Apr 30 02:29:56 PM PDT 24 |
800393900 ps |
| T945 |
/workspace/coverage/default/19.flash_ctrl_hw_sec_otp.3831862866 |
|
|
Apr 30 02:31:57 PM PDT 24 |
Apr 30 02:32:48 PM PDT 24 |
3185190000 ps |
| T946 |
/workspace/coverage/default/2.flash_ctrl_ro_derr.1907314764 |
|
|
Apr 30 02:27:16 PM PDT 24 |
Apr 30 02:30:05 PM PDT 24 |
3098187800 ps |
| T947 |
/workspace/coverage/default/6.flash_ctrl_intr_rd.2160741923 |
|
|
Apr 30 02:28:36 PM PDT 24 |
Apr 30 02:31:48 PM PDT 24 |
5168722100 ps |
| T948 |
/workspace/coverage/default/5.flash_ctrl_ro.2431645265 |
|
|
Apr 30 02:28:19 PM PDT 24 |
Apr 30 02:30:20 PM PDT 24 |
3898846000 ps |
| T949 |
/workspace/coverage/default/48.flash_ctrl_hw_sec_otp.695499491 |
|
|
Apr 30 02:34:50 PM PDT 24 |
Apr 30 02:36:37 PM PDT 24 |
10591556800 ps |
| T950 |
/workspace/coverage/default/4.flash_ctrl_re_evict.3008214496 |
|
|
Apr 30 02:27:56 PM PDT 24 |
Apr 30 02:28:33 PM PDT 24 |
172782200 ps |
| T951 |
/workspace/coverage/default/7.flash_ctrl_intr_rd.3415984507 |
|
|
Apr 30 02:28:56 PM PDT 24 |
Apr 30 02:31:54 PM PDT 24 |
1934404400 ps |
| T952 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.4225766521 |
|
|
Apr 30 02:19:48 PM PDT 24 |
Apr 30 02:20:04 PM PDT 24 |
14952000 ps |
| T953 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.843418070 |
|
|
Apr 30 02:19:38 PM PDT 24 |
Apr 30 02:19:55 PM PDT 24 |
15373900 ps |
| T67 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3555774577 |
|
|
Apr 30 02:19:25 PM PDT 24 |
Apr 30 02:20:07 PM PDT 24 |
717574400 ps |
| T68 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1298878690 |
|
|
Apr 30 02:19:33 PM PDT 24 |
Apr 30 02:19:51 PM PDT 24 |
82524200 ps |
| T954 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3301623832 |
|
|
Apr 30 02:19:25 PM PDT 24 |
Apr 30 02:19:41 PM PDT 24 |
22795500 ps |
| T955 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1282602328 |
|
|
Apr 30 02:19:30 PM PDT 24 |
Apr 30 02:19:44 PM PDT 24 |
42898400 ps |
| T69 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1414496983 |
|
|
Apr 30 02:20:08 PM PDT 24 |
Apr 30 02:20:28 PM PDT 24 |
115404800 ps |
| T70 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3202490643 |
|
|
Apr 30 02:19:34 PM PDT 24 |
Apr 30 02:19:54 PM PDT 24 |
194532900 ps |
| T234 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2410997176 |
|
|
Apr 30 02:20:10 PM PDT 24 |
Apr 30 02:20:24 PM PDT 24 |
17623300 ps |
| T228 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2030758162 |
|
|
Apr 30 02:19:26 PM PDT 24 |
Apr 30 02:19:41 PM PDT 24 |
65727900 ps |
| T225 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.4064946016 |
|
|
Apr 30 02:20:09 PM PDT 24 |
Apr 30 02:20:45 PM PDT 24 |
1941841400 ps |
| T229 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2789881332 |
|
|
Apr 30 02:19:31 PM PDT 24 |
Apr 30 02:19:47 PM PDT 24 |
82613300 ps |
| T209 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3320653687 |
|
|
Apr 30 02:19:20 PM PDT 24 |
Apr 30 02:19:39 PM PDT 24 |
53024600 ps |
| T210 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2145064812 |
|
|
Apr 30 02:19:39 PM PDT 24 |
Apr 30 02:19:59 PM PDT 24 |
65548800 ps |
| T235 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.520323707 |
|
|
Apr 30 02:20:10 PM PDT 24 |
Apr 30 02:20:24 PM PDT 24 |
25942900 ps |
| T236 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.4008729447 |
|
|
Apr 30 02:20:03 PM PDT 24 |
Apr 30 02:20:17 PM PDT 24 |
60710200 ps |
| T347 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3067231405 |
|
|
Apr 30 02:19:20 PM PDT 24 |
Apr 30 02:19:34 PM PDT 24 |
18945200 ps |
| T348 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1057959475 |
|
|
Apr 30 02:19:55 PM PDT 24 |
Apr 30 02:20:09 PM PDT 24 |
32374600 ps |
| T352 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1216253966 |
|
|
Apr 30 02:20:10 PM PDT 24 |
Apr 30 02:20:23 PM PDT 24 |
49464900 ps |
| T956 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2203481444 |
|
|
Apr 30 02:20:09 PM PDT 24 |
Apr 30 02:20:23 PM PDT 24 |
26657500 ps |
| T226 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2335874573 |
|
|
Apr 30 02:19:26 PM PDT 24 |
Apr 30 02:19:43 PM PDT 24 |
138759900 ps |
| T211 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.720202575 |
|
|
Apr 30 02:19:41 PM PDT 24 |
Apr 30 02:20:01 PM PDT 24 |
104982600 ps |
| T224 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2382099005 |
|
|
Apr 30 02:19:21 PM PDT 24 |
Apr 30 02:20:07 PM PDT 24 |
187763700 ps |
| T957 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1220500985 |
|
|
Apr 30 02:19:32 PM PDT 24 |
Apr 30 02:19:49 PM PDT 24 |
26395100 ps |
| T71 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.528898311 |
|
|
Apr 30 02:19:39 PM PDT 24 |
Apr 30 02:19:54 PM PDT 24 |
26140500 ps |
| T349 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1569833883 |
|
|
Apr 30 02:20:07 PM PDT 24 |
Apr 30 02:20:21 PM PDT 24 |
55662700 ps |
| T958 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1103614259 |
|
|
Apr 30 02:19:56 PM PDT 24 |
Apr 30 02:20:10 PM PDT 24 |
23071100 ps |
| T227 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3315251314 |
|
|
Apr 30 02:19:58 PM PDT 24 |
Apr 30 02:20:20 PM PDT 24 |
878538300 ps |
| T959 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.4239858206 |
|
|
Apr 30 02:19:46 PM PDT 24 |
Apr 30 02:20:03 PM PDT 24 |
13482800 ps |
| T212 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2595235731 |
|
|
Apr 30 02:19:37 PM PDT 24 |
Apr 30 02:32:25 PM PDT 24 |
1503494300 ps |
| T231 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3854342606 |
|
|
Apr 30 02:19:26 PM PDT 24 |
Apr 30 02:19:44 PM PDT 24 |
149134400 ps |
| T329 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3554819209 |
|
|
Apr 30 02:19:30 PM PDT 24 |
Apr 30 02:19:48 PM PDT 24 |
28477600 ps |
| T242 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1887836370 |
|
|
Apr 30 02:19:55 PM PDT 24 |
Apr 30 02:20:12 PM PDT 24 |
36228000 ps |
| T313 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3305403750 |
|
|
Apr 30 02:19:45 PM PDT 24 |
Apr 30 02:20:02 PM PDT 24 |
117788800 ps |
| T960 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1448352222 |
|
|
Apr 30 02:19:59 PM PDT 24 |
Apr 30 02:20:15 PM PDT 24 |
97866000 ps |
| T382 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3351796940 |
|
|
Apr 30 02:19:26 PM PDT 24 |
Apr 30 02:20:16 PM PDT 24 |
2469231300 ps |
| T330 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.4246243956 |
|
|
Apr 30 02:19:53 PM PDT 24 |
Apr 30 02:20:09 PM PDT 24 |
24868200 ps |
| T331 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.986906122 |
|
|
Apr 30 02:19:46 PM PDT 24 |
Apr 30 02:20:10 PM PDT 24 |
168053100 ps |
| T350 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2200137070 |
|
|
Apr 30 02:19:55 PM PDT 24 |
Apr 30 02:20:08 PM PDT 24 |
16584100 ps |
| T332 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2737616324 |
|
|
Apr 30 02:19:43 PM PDT 24 |
Apr 30 02:20:02 PM PDT 24 |
78811000 ps |
| T961 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.846996554 |
|
|
Apr 30 02:19:47 PM PDT 24 |
Apr 30 02:20:01 PM PDT 24 |
63391900 ps |
| T372 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3418959971 |
|
|
Apr 30 02:19:46 PM PDT 24 |
Apr 30 02:20:02 PM PDT 24 |
48884500 ps |
| T243 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2597640517 |
|
|
Apr 30 02:19:58 PM PDT 24 |
Apr 30 02:20:17 PM PDT 24 |
124920400 ps |
| T962 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.197092178 |
|
|
Apr 30 02:19:52 PM PDT 24 |
Apr 30 02:20:09 PM PDT 24 |
31098000 ps |
| T222 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.51185136 |
|
|
Apr 30 02:19:44 PM PDT 24 |
Apr 30 02:34:58 PM PDT 24 |
3111407900 ps |
| T315 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3575002765 |
|
|
Apr 30 02:19:31 PM PDT 24 |
Apr 30 02:19:45 PM PDT 24 |
30092800 ps |
| T339 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.4255323907 |
|
|
Apr 30 02:19:32 PM PDT 24 |
Apr 30 02:21:06 PM PDT 24 |
13103313700 ps |
| T340 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1847116956 |
|
|
Apr 30 02:19:36 PM PDT 24 |
Apr 30 02:20:48 PM PDT 24 |
7511372700 ps |
| T963 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3602603459 |
|
|
Apr 30 02:19:47 PM PDT 24 |
Apr 30 02:20:09 PM PDT 24 |
719636300 ps |
| T223 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3022736055 |
|
|
Apr 30 02:19:46 PM PDT 24 |
Apr 30 02:27:37 PM PDT 24 |
1403066700 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3041622119 |
|
|
Apr 30 02:19:28 PM PDT 24 |
Apr 30 02:19:44 PM PDT 24 |
80040600 ps |
| T965 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3692497999 |
|
|
Apr 30 02:19:54 PM PDT 24 |
Apr 30 02:20:11 PM PDT 24 |
99452200 ps |
| T230 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2269977209 |
|
|
Apr 30 02:19:34 PM PDT 24 |
Apr 30 02:19:50 PM PDT 24 |
32951200 ps |
| T351 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.535829040 |
|
|
Apr 30 02:19:46 PM PDT 24 |
Apr 30 02:20:01 PM PDT 24 |
123115200 ps |
| T247 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.4016842010 |
|
|
Apr 30 02:19:59 PM PDT 24 |
Apr 30 02:35:07 PM PDT 24 |
1393321400 ps |
| T966 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.4130199870 |
|
|
Apr 30 02:19:38 PM PDT 24 |
Apr 30 02:19:54 PM PDT 24 |
63151600 ps |
| T341 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.654249385 |
|
|
Apr 30 02:19:59 PM PDT 24 |
Apr 30 02:20:17 PM PDT 24 |
148580100 ps |
| T342 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.684958805 |
|
|
Apr 30 02:19:39 PM PDT 24 |
Apr 30 02:19:58 PM PDT 24 |
111825400 ps |
| T967 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3390193202 |
|
|
Apr 30 02:19:39 PM PDT 24 |
Apr 30 02:19:53 PM PDT 24 |
16801300 ps |
| T301 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3565086528 |
|
|
Apr 30 02:19:54 PM PDT 24 |
Apr 30 02:35:07 PM PDT 24 |
396927700 ps |
| T968 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2462404160 |
|
|
Apr 30 02:20:01 PM PDT 24 |
Apr 30 02:20:15 PM PDT 24 |
52315000 ps |
| T969 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2267013638 |
|
|
Apr 30 02:19:48 PM PDT 24 |
Apr 30 02:20:06 PM PDT 24 |
205197400 ps |
| T970 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1913830724 |
|
|
Apr 30 02:19:26 PM PDT 24 |
Apr 30 02:19:40 PM PDT 24 |
29966200 ps |
| T343 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1114705958 |
|
|
Apr 30 02:19:26 PM PDT 24 |
Apr 30 02:20:08 PM PDT 24 |
1783001200 ps |
| T344 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.252156823 |
|
|
Apr 30 02:20:02 PM PDT 24 |
Apr 30 02:20:18 PM PDT 24 |
106375100 ps |
| T971 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1408788547 |
|
|
Apr 30 02:20:12 PM PDT 24 |
Apr 30 02:20:27 PM PDT 24 |
22025400 ps |
| T972 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3037569110 |
|
|
Apr 30 02:19:53 PM PDT 24 |
Apr 30 02:20:08 PM PDT 24 |
18238600 ps |
| T244 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.140595446 |
|
|
Apr 30 02:19:45 PM PDT 24 |
Apr 30 02:20:01 PM PDT 24 |
441445200 ps |
| T232 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3684022981 |
|
|
Apr 30 02:19:46 PM PDT 24 |
Apr 30 02:20:03 PM PDT 24 |
217871600 ps |
| T973 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3295088145 |
|
|
Apr 30 02:19:56 PM PDT 24 |
Apr 30 02:20:12 PM PDT 24 |
49954400 ps |
| T974 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3031505611 |
|
|
Apr 30 02:20:04 PM PDT 24 |
Apr 30 02:20:21 PM PDT 24 |
35956700 ps |
| T249 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1275602443 |
|
|
Apr 30 02:19:56 PM PDT 24 |
Apr 30 02:35:14 PM PDT 24 |
1016374900 ps |
| T373 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3019873668 |
|
|
Apr 30 02:19:39 PM PDT 24 |
Apr 30 02:34:53 PM PDT 24 |
3441479800 ps |
| T975 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2156699422 |
|
|
Apr 30 02:20:05 PM PDT 24 |
Apr 30 02:20:19 PM PDT 24 |
18276200 ps |
| T976 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2677193078 |
|
|
Apr 30 02:19:26 PM PDT 24 |
Apr 30 02:19:44 PM PDT 24 |
88311200 ps |
| T977 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.557694402 |
|
|
Apr 30 02:20:12 PM PDT 24 |
Apr 30 02:20:27 PM PDT 24 |
93600400 ps |
| T978 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.106229895 |
|
|
Apr 30 02:19:34 PM PDT 24 |
Apr 30 02:20:20 PM PDT 24 |
241387700 ps |
| T979 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2957921661 |
|
|
Apr 30 02:19:45 PM PDT 24 |
Apr 30 02:19:59 PM PDT 24 |
19931000 ps |
| T233 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2543577445 |
|
|
Apr 30 02:19:43 PM PDT 24 |
Apr 30 02:20:02 PM PDT 24 |
52148500 ps |
| T345 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2457428799 |
|
|
Apr 30 02:19:34 PM PDT 24 |
Apr 30 02:19:53 PM PDT 24 |
357127300 ps |
| T346 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1996960887 |
|
|
Apr 30 02:19:27 PM PDT 24 |
Apr 30 02:20:36 PM PDT 24 |
10893804500 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3739587734 |
|
|
Apr 30 02:19:36 PM PDT 24 |
Apr 30 02:19:50 PM PDT 24 |
74451500 ps |
| T250 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1729485770 |
|
|
Apr 30 02:19:56 PM PDT 24 |
Apr 30 02:27:38 PM PDT 24 |
724451700 ps |
| T981 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.907556393 |
|
|
Apr 30 02:19:29 PM PDT 24 |
Apr 30 02:19:43 PM PDT 24 |
17460600 ps |
| T982 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2546266496 |
|
|
Apr 30 02:19:35 PM PDT 24 |
Apr 30 02:19:53 PM PDT 24 |
26320500 ps |
| T983 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.419469695 |
|
|
Apr 30 02:19:45 PM PDT 24 |
Apr 30 02:20:06 PM PDT 24 |
235729000 ps |
| T984 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.408357518 |
|
|
Apr 30 02:20:00 PM PDT 24 |
Apr 30 02:20:15 PM PDT 24 |
16847600 ps |
| T985 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2259347816 |
|
|
Apr 30 02:19:33 PM PDT 24 |
Apr 30 02:19:47 PM PDT 24 |
16478800 ps |
| T986 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.54495714 |
|
|
Apr 30 02:20:02 PM PDT 24 |
Apr 30 02:20:18 PM PDT 24 |
13625700 ps |
| T987 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.77103298 |
|
|
Apr 30 02:20:04 PM PDT 24 |
Apr 30 02:20:18 PM PDT 24 |
28885400 ps |
| T988 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.108192446 |
|
|
Apr 30 02:19:33 PM PDT 24 |
Apr 30 02:19:47 PM PDT 24 |
38921700 ps |
| T989 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1135178596 |
|
|
Apr 30 02:19:32 PM PDT 24 |
Apr 30 02:20:11 PM PDT 24 |
666664000 ps |
| T238 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2029851217 |
|
|
Apr 30 02:19:26 PM PDT 24 |
Apr 30 02:26:01 PM PDT 24 |
182911400 ps |
| T248 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2802802770 |
|
|
Apr 30 02:19:33 PM PDT 24 |
Apr 30 02:19:50 PM PDT 24 |
66725500 ps |
| T375 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3493203128 |
|
|
Apr 30 02:20:00 PM PDT 24 |
Apr 30 02:27:39 PM PDT 24 |
829540500 ps |
| T376 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3549072288 |
|
|
Apr 30 02:20:00 PM PDT 24 |
Apr 30 02:35:14 PM PDT 24 |
1485497700 ps |
| T990 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1565271553 |
|
|
Apr 30 02:20:07 PM PDT 24 |
Apr 30 02:20:21 PM PDT 24 |
17427800 ps |
| T991 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.419827834 |
|
|
Apr 30 02:20:13 PM PDT 24 |
Apr 30 02:20:27 PM PDT 24 |
68775900 ps |
| T316 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3559279787 |
|
|
Apr 30 02:19:36 PM PDT 24 |
Apr 30 02:19:50 PM PDT 24 |
48136100 ps |
| T992 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4018179616 |
|
|
Apr 30 02:19:59 PM PDT 24 |
Apr 30 02:20:15 PM PDT 24 |
53572900 ps |
| T993 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.4216966939 |
|
|
Apr 30 02:19:58 PM PDT 24 |
Apr 30 02:20:11 PM PDT 24 |
35000300 ps |
| T994 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3247780827 |
|
|
Apr 30 02:19:53 PM PDT 24 |
Apr 30 02:20:06 PM PDT 24 |
25227500 ps |
| T995 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.4218714696 |
|
|
Apr 30 02:19:46 PM PDT 24 |
Apr 30 02:20:05 PM PDT 24 |
120345800 ps |
| T996 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2719922190 |
|
|
Apr 30 02:19:20 PM PDT 24 |
Apr 30 02:19:37 PM PDT 24 |
99235200 ps |
| T997 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.560377109 |
|
|
Apr 30 02:20:05 PM PDT 24 |
Apr 30 02:20:19 PM PDT 24 |
29780400 ps |
| T998 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1394804762 |
|
|
Apr 30 02:19:43 PM PDT 24 |
Apr 30 02:20:00 PM PDT 24 |
19224400 ps |
| T380 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1567501079 |
|
|
Apr 30 02:19:39 PM PDT 24 |
Apr 30 02:27:24 PM PDT 24 |
1267579900 ps |
| T245 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.582190758 |
|
|
Apr 30 02:19:46 PM PDT 24 |
Apr 30 02:20:04 PM PDT 24 |
176198200 ps |
| T999 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2947664718 |
|
|
Apr 30 02:20:10 PM PDT 24 |
Apr 30 02:20:24 PM PDT 24 |
41155200 ps |
| T1000 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.324538501 |
|
|
Apr 30 02:19:26 PM PDT 24 |
Apr 30 02:19:40 PM PDT 24 |
11917100 ps |
| T1001 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1690291682 |
|
|
Apr 30 02:19:41 PM PDT 24 |
Apr 30 02:19:55 PM PDT 24 |
22892200 ps |
| T1002 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1881971128 |
|
|
Apr 30 02:19:43 PM PDT 24 |
Apr 30 02:19:58 PM PDT 24 |
116850200 ps |
| T1003 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2709232868 |
|
|
Apr 30 02:19:36 PM PDT 24 |
Apr 30 02:19:55 PM PDT 24 |
915970600 ps |
| T1004 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1035399668 |
|
|
Apr 30 02:19:39 PM PDT 24 |
Apr 30 02:19:53 PM PDT 24 |
46201600 ps |
| T1005 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3917889593 |
|
|
Apr 30 02:20:04 PM PDT 24 |
Apr 30 02:20:20 PM PDT 24 |
12131400 ps |
| T1006 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.562931775 |
|
|
Apr 30 02:20:02 PM PDT 24 |
Apr 30 02:20:18 PM PDT 24 |
33526700 ps |
| T1007 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.974186040 |
|
|
Apr 30 02:20:02 PM PDT 24 |
Apr 30 02:20:19 PM PDT 24 |
38430600 ps |
| T246 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3252049438 |
|
|
Apr 30 02:19:25 PM PDT 24 |
Apr 30 02:19:44 PM PDT 24 |
50420800 ps |
| T1008 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1209879970 |
|
|
Apr 30 02:19:53 PM PDT 24 |
Apr 30 02:20:08 PM PDT 24 |
20999800 ps |
| T237 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.581714742 |
|
|
Apr 30 02:19:57 PM PDT 24 |
Apr 30 02:20:16 PM PDT 24 |
194826500 ps |
| T251 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.500044388 |
|
|
Apr 30 02:19:59 PM PDT 24 |
Apr 30 02:20:19 PM PDT 24 |
55063800 ps |
| T1009 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.4104071347 |
|
|
Apr 30 02:19:46 PM PDT 24 |
Apr 30 02:20:00 PM PDT 24 |
25129700 ps |
| T378 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2102934740 |
|
|
Apr 30 02:19:39 PM PDT 24 |
Apr 30 02:34:56 PM PDT 24 |
699132400 ps |
| T253 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1072592729 |
|
|
Apr 30 02:19:46 PM PDT 24 |
Apr 30 02:20:03 PM PDT 24 |
135426000 ps |
| T1010 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3823682151 |
|
|
Apr 30 02:19:32 PM PDT 24 |
Apr 30 02:20:18 PM PDT 24 |
157631300 ps |