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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.99 95.78 93.24 94.81 90.48 97.84 95.01 97.78


Total test records in report: 1090
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T1011 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2861982512 Apr 30 02:19:57 PM PDT 24 Apr 30 02:20:17 PM PDT 24 490837900 ps
T1012 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1217826209 Apr 30 02:19:38 PM PDT 24 Apr 30 02:19:55 PM PDT 24 20739800 ps
T317 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2418665594 Apr 30 02:19:26 PM PDT 24 Apr 30 02:19:40 PM PDT 24 46534600 ps
T1013 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3972012279 Apr 30 02:19:37 PM PDT 24 Apr 30 02:19:54 PM PDT 24 18633600 ps
T1014 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1131309964 Apr 30 02:20:11 PM PDT 24 Apr 30 02:20:25 PM PDT 24 14390600 ps
T318 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3499471419 Apr 30 02:19:23 PM PDT 24 Apr 30 02:19:37 PM PDT 24 49641600 ps
T1015 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1344439833 Apr 30 02:20:00 PM PDT 24 Apr 30 02:20:17 PM PDT 24 55998500 ps
T1016 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2524321841 Apr 30 02:19:55 PM PDT 24 Apr 30 02:20:11 PM PDT 24 76724000 ps
T1017 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2860087898 Apr 30 02:19:32 PM PDT 24 Apr 30 02:19:46 PM PDT 24 99386500 ps
T1018 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1889310626 Apr 30 02:19:46 PM PDT 24 Apr 30 02:35:04 PM PDT 24 862048300 ps
T1019 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3696629579 Apr 30 02:19:34 PM PDT 24 Apr 30 02:19:48 PM PDT 24 24657100 ps
T1020 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3032574261 Apr 30 02:20:01 PM PDT 24 Apr 30 02:20:18 PM PDT 24 79948600 ps
T319 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3852220795 Apr 30 02:19:32 PM PDT 24 Apr 30 02:19:47 PM PDT 24 46621800 ps
T241 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2155864789 Apr 30 02:19:59 PM PDT 24 Apr 30 02:20:19 PM PDT 24 225630000 ps
T1021 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1895347308 Apr 30 02:20:03 PM PDT 24 Apr 30 02:20:17 PM PDT 24 42918400 ps
T1022 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.586984797 Apr 30 02:20:01 PM PDT 24 Apr 30 02:20:17 PM PDT 24 44273000 ps
T379 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.516160323 Apr 30 02:19:58 PM PDT 24 Apr 30 02:35:00 PM PDT 24 3301857700 ps
T1023 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3545064443 Apr 30 02:19:45 PM PDT 24 Apr 30 02:20:00 PM PDT 24 48041700 ps
T1024 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.823835093 Apr 30 02:19:26 PM PDT 24 Apr 30 02:20:03 PM PDT 24 211641200 ps
T1025 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2419540914 Apr 30 02:19:38 PM PDT 24 Apr 30 02:20:26 PM PDT 24 3282706000 ps
T1026 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3738551826 Apr 30 02:19:38 PM PDT 24 Apr 30 02:19:55 PM PDT 24 14377300 ps
T1027 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.459635186 Apr 30 02:20:05 PM PDT 24 Apr 30 02:20:19 PM PDT 24 57933400 ps
T1028 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3299405102 Apr 30 02:19:45 PM PDT 24 Apr 30 02:20:00 PM PDT 24 25026300 ps
T1029 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3844345565 Apr 30 02:19:58 PM PDT 24 Apr 30 02:20:14 PM PDT 24 12354300 ps
T1030 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3617887642 Apr 30 02:20:15 PM PDT 24 Apr 30 02:20:29 PM PDT 24 15944300 ps
T1031 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.4085697555 Apr 30 02:20:12 PM PDT 24 Apr 30 02:20:26 PM PDT 24 50607300 ps
T1032 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.119779323 Apr 30 02:19:53 PM PDT 24 Apr 30 02:20:28 PM PDT 24 117777400 ps
T1033 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.767480567 Apr 30 02:20:00 PM PDT 24 Apr 30 02:20:20 PM PDT 24 54097900 ps
T1034 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1552621272 Apr 30 02:19:27 PM PDT 24 Apr 30 02:19:43 PM PDT 24 24365800 ps
T1035 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2680254347 Apr 30 02:19:46 PM PDT 24 Apr 30 02:20:04 PM PDT 24 269695600 ps
T1036 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.4036516819 Apr 30 02:19:40 PM PDT 24 Apr 30 02:19:57 PM PDT 24 29166700 ps
T1037 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1958356803 Apr 30 02:20:05 PM PDT 24 Apr 30 02:20:19 PM PDT 24 58190100 ps
T1038 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3170110628 Apr 30 02:19:46 PM PDT 24 Apr 30 02:20:04 PM PDT 24 285840600 ps
T1039 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.3017182244 Apr 30 02:19:47 PM PDT 24 Apr 30 02:20:02 PM PDT 24 24952500 ps
T1040 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3309962344 Apr 30 02:20:00 PM PDT 24 Apr 30 02:20:16 PM PDT 24 13914800 ps
T1041 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1813675826 Apr 30 02:19:33 PM PDT 24 Apr 30 02:19:47 PM PDT 24 18126500 ps
T1042 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.637539048 Apr 30 02:19:35 PM PDT 24 Apr 30 02:20:24 PM PDT 24 4281986100 ps
T1043 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1734565348 Apr 30 02:19:33 PM PDT 24 Apr 30 02:20:40 PM PDT 24 4790321600 ps
T1044 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3285141675 Apr 30 02:19:19 PM PDT 24 Apr 30 02:26:57 PM PDT 24 681610700 ps
T1045 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.4062334115 Apr 30 02:20:06 PM PDT 24 Apr 30 02:20:21 PM PDT 24 29321500 ps
T1046 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2044937937 Apr 30 02:19:45 PM PDT 24 Apr 30 02:20:02 PM PDT 24 26080900 ps
T1047 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1326112378 Apr 30 02:19:46 PM PDT 24 Apr 30 02:20:00 PM PDT 24 14717400 ps
T1048 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3367314280 Apr 30 02:19:55 PM PDT 24 Apr 30 02:20:12 PM PDT 24 81722300 ps
T1049 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3201228624 Apr 30 02:20:05 PM PDT 24 Apr 30 02:20:19 PM PDT 24 59564700 ps
T1050 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2496960187 Apr 30 02:20:06 PM PDT 24 Apr 30 02:20:20 PM PDT 24 27039500 ps
T1051 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.772735760 Apr 30 02:20:00 PM PDT 24 Apr 30 02:20:14 PM PDT 24 58157400 ps
T1052 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2345648421 Apr 30 02:20:05 PM PDT 24 Apr 30 02:20:21 PM PDT 24 40814300 ps
T1053 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.4042489300 Apr 30 02:19:28 PM PDT 24 Apr 30 02:19:55 PM PDT 24 31308900 ps
T1054 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1787512467 Apr 30 02:20:01 PM PDT 24 Apr 30 02:20:21 PM PDT 24 551308000 ps
T374 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2053748496 Apr 30 02:19:29 PM PDT 24 Apr 30 02:34:43 PM PDT 24 1260288000 ps
T239 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.4057173421 Apr 30 02:20:00 PM PDT 24 Apr 30 02:20:17 PM PDT 24 33345600 ps
T1055 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1177600031 Apr 30 02:19:53 PM PDT 24 Apr 30 02:20:12 PM PDT 24 41139600 ps
T1056 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3895056329 Apr 30 02:19:34 PM PDT 24 Apr 30 02:20:22 PM PDT 24 26971800 ps
T1057 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.268365071 Apr 30 02:19:25 PM PDT 24 Apr 30 02:19:39 PM PDT 24 14993400 ps
T1058 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3961142319 Apr 30 02:19:38 PM PDT 24 Apr 30 02:19:57 PM PDT 24 61981900 ps
T1059 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3686138556 Apr 30 02:20:04 PM PDT 24 Apr 30 02:20:17 PM PDT 24 15879300 ps
T1060 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1848471319 Apr 30 02:19:33 PM PDT 24 Apr 30 02:27:32 PM PDT 24 179306000 ps
T377 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.183512322 Apr 30 02:19:45 PM PDT 24 Apr 30 02:35:02 PM PDT 24 604648400 ps
T1061 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1688715267 Apr 30 02:19:19 PM PDT 24 Apr 30 02:19:35 PM PDT 24 44151400 ps
T1062 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3845348636 Apr 30 02:19:44 PM PDT 24 Apr 30 02:20:00 PM PDT 24 22643600 ps
T1063 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.3507266684 Apr 30 02:20:15 PM PDT 24 Apr 30 02:20:29 PM PDT 24 16072000 ps
T1064 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3945081344 Apr 30 02:19:38 PM PDT 24 Apr 30 02:19:53 PM PDT 24 24976200 ps
T1065 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1482080288 Apr 30 02:19:36 PM PDT 24 Apr 30 02:19:56 PM PDT 24 39982600 ps
T1066 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.382434575 Apr 30 02:19:53 PM PDT 24 Apr 30 02:20:12 PM PDT 24 604300100 ps
T1067 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2658073119 Apr 30 02:19:35 PM PDT 24 Apr 30 02:19:49 PM PDT 24 36200800 ps
T1068 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.309754872 Apr 30 02:19:52 PM PDT 24 Apr 30 02:20:09 PM PDT 24 20926600 ps
T1069 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1341463418 Apr 30 02:20:06 PM PDT 24 Apr 30 02:20:20 PM PDT 24 14078300 ps
T252 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2624990946 Apr 30 02:19:43 PM PDT 24 Apr 30 02:27:30 PM PDT 24 539752300 ps
T1070 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3647427984 Apr 30 02:19:53 PM PDT 24 Apr 30 02:20:12 PM PDT 24 42458700 ps
T1071 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1495703424 Apr 30 02:19:54 PM PDT 24 Apr 30 02:20:08 PM PDT 24 14896100 ps
T240 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1915357115 Apr 30 02:20:02 PM PDT 24 Apr 30 02:20:21 PM PDT 24 203465000 ps
T1072 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2290413687 Apr 30 02:20:01 PM PDT 24 Apr 30 02:20:17 PM PDT 24 42143900 ps
T1073 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3752897470 Apr 30 02:20:03 PM PDT 24 Apr 30 02:20:17 PM PDT 24 18214600 ps
T1074 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.643705662 Apr 30 02:20:04 PM PDT 24 Apr 30 02:20:18 PM PDT 24 15991200 ps
T1075 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.75917942 Apr 30 02:19:45 PM PDT 24 Apr 30 02:20:03 PM PDT 24 35155300 ps
T1076 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3241067971 Apr 30 02:19:20 PM PDT 24 Apr 30 02:19:34 PM PDT 24 15177400 ps
T1077 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.4254914262 Apr 30 02:20:00 PM PDT 24 Apr 30 02:20:17 PM PDT 24 631039900 ps
T1078 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.990555789 Apr 30 02:19:33 PM PDT 24 Apr 30 02:19:48 PM PDT 24 39638000 ps
T1079 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3963479238 Apr 30 02:19:55 PM PDT 24 Apr 30 02:20:12 PM PDT 24 69795900 ps
T1080 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.2409030165 Apr 30 02:19:27 PM PDT 24 Apr 30 02:19:40 PM PDT 24 23710700 ps
T1081 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3279695783 Apr 30 02:19:32 PM PDT 24 Apr 30 02:19:46 PM PDT 24 18757800 ps
T1082 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.4086974703 Apr 30 02:19:38 PM PDT 24 Apr 30 02:19:53 PM PDT 24 37361500 ps
T1083 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1149374491 Apr 30 02:19:46 PM PDT 24 Apr 30 02:20:07 PM PDT 24 196174800 ps
T1084 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2068362264 Apr 30 02:19:45 PM PDT 24 Apr 30 02:20:19 PM PDT 24 239751800 ps
T1085 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.286608760 Apr 30 02:19:52 PM PDT 24 Apr 30 02:20:24 PM PDT 24 1132700700 ps
T1086 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.510193884 Apr 30 02:19:40 PM PDT 24 Apr 30 02:20:02 PM PDT 24 656403000 ps
T1087 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1441013236 Apr 30 02:20:09 PM PDT 24 Apr 30 02:20:23 PM PDT 24 60493900 ps
T1088 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2672988169 Apr 30 02:20:06 PM PDT 24 Apr 30 02:20:20 PM PDT 24 74057300 ps
T1089 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2405611382 Apr 30 02:20:06 PM PDT 24 Apr 30 02:20:20 PM PDT 24 148091600 ps
T1090 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1485375870 Apr 30 02:19:24 PM PDT 24 Apr 30 02:19:41 PM PDT 24 13331100 ps

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.1592043897
Short name T3
Test name
Test status
Simulation time 1776643100 ps
CPU time 68.38 seconds
Started Apr 30 02:26:05 PM PDT 24
Finished Apr 30 02:27:14 PM PDT 24
Peak memory 260036 kb
Host smart-667c152a-6d3c-42b1-8387-4ed3d808c8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592043897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.1592043897
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.140157500
Short name T6
Test name
Test status
Simulation time 4894801600 ps
CPU time 718.3 seconds
Started Apr 30 02:27:48 PM PDT 24
Finished Apr 30 02:39:47 PM PDT 24
Peak memory 313936 kb
Host smart-23a9b350-a6f2-4308-b959-fbee0c3e32af
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140157500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.flash_ctrl_rw.140157500
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3202490643
Short name T70
Test name
Test status
Simulation time 194532900 ps
CPU time 19.03 seconds
Started Apr 30 02:19:34 PM PDT 24
Finished Apr 30 02:19:54 PM PDT 24
Peak memory 270436 kb
Host smart-bc118372-7e58-420d-b7f7-074e4a4b19f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202490643 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.3202490643
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.3663799496
Short name T1
Test name
Test status
Simulation time 160181517800 ps
CPU time 988.68 seconds
Started Apr 30 02:29:49 PM PDT 24
Finished Apr 30 02:46:28 PM PDT 24
Peak memory 262300 kb
Host smart-ea99b9b3-cf50-4049-93b1-01a22f5768bd
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663799496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.3663799496
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.3332292348
Short name T43
Test name
Test status
Simulation time 207322832200 ps
CPU time 898.66 seconds
Started Apr 30 02:31:40 PM PDT 24
Finished Apr 30 02:46:57 PM PDT 24
Peak memory 273684 kb
Host smart-54735d5f-3ddf-4cd9-8062-e46f99fa9080
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332292348 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.flash_ctrl_mp_regions.3332292348
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.2540952981
Short name T53
Test name
Test status
Simulation time 39463200 ps
CPU time 130.05 seconds
Started Apr 30 02:34:54 PM PDT 24
Finished Apr 30 02:37:04 PM PDT 24
Peak memory 260564 kb
Host smart-ffa169b8-c73b-4d7e-96ac-fe2bedab4be5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540952981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o
tp_reset.2540952981
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.51185136
Short name T222
Test name
Test status
Simulation time 3111407900 ps
CPU time 912.9 seconds
Started Apr 30 02:19:44 PM PDT 24
Finished Apr 30 02:34:58 PM PDT 24
Peak memory 263948 kb
Host smart-c350f06d-a26e-4d5f-8090-8751630e5405
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51185136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
tl_intg_err.51185136
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.2774801916
Short name T42
Test name
Test status
Simulation time 5236698800 ps
CPU time 434.55 seconds
Started Apr 30 02:27:49 PM PDT 24
Finished Apr 30 02:35:04 PM PDT 24
Peak memory 260660 kb
Host smart-2432f0c9-5bcf-4075-b251-d5e57ed8da84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2774801916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.2774801916
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.1988930046
Short name T162
Test name
Test status
Simulation time 7856120800 ps
CPU time 259.67 seconds
Started Apr 30 02:34:16 PM PDT 24
Finished Apr 30 02:38:37 PM PDT 24
Peak memory 290332 kb
Host smart-3281f44b-a922-442a-bfdd-85e0dadbf15a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988930046 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.1988930046
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.3638095950
Short name T79
Test name
Test status
Simulation time 37619100 ps
CPU time 135.12 seconds
Started Apr 30 02:28:16 PM PDT 24
Finished Apr 30 02:30:32 PM PDT 24
Peak memory 259272 kb
Host smart-ec16a462-85de-46cc-84f3-28859fc7164d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638095950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot
p_reset.3638095950
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.2692134698
Short name T20
Test name
Test status
Simulation time 44166500 ps
CPU time 14.35 seconds
Started Apr 30 02:26:15 PM PDT 24
Finished Apr 30 02:26:30 PM PDT 24
Peak memory 261476 kb
Host smart-9b679628-0699-4985-8c06-dfb414eebf3d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692134698 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.2692134698
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.3819329773
Short name T529
Test name
Test status
Simulation time 176381800 ps
CPU time 132.03 seconds
Started Apr 30 02:31:28 PM PDT 24
Finished Apr 30 02:33:58 PM PDT 24
Peak memory 259352 kb
Host smart-c0fda23f-d839-4253-b0de-680038661ad5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819329773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o
tp_reset.3819329773
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.136994063
Short name T18
Test name
Test status
Simulation time 137784400 ps
CPU time 14.96 seconds
Started Apr 30 02:26:14 PM PDT 24
Finished Apr 30 02:26:29 PM PDT 24
Peak memory 259696 kb
Host smart-12e5c823-f56c-4fa7-9df4-243c0715338d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136994063 -assert nopostproc +UVM
_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.136994063
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1057959475
Short name T348
Test name
Test status
Simulation time 32374600 ps
CPU time 13.89 seconds
Started Apr 30 02:19:55 PM PDT 24
Finished Apr 30 02:20:09 PM PDT 24
Peak memory 262492 kb
Host smart-b1a49e01-0852-4661-bac8-fdaea93930dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057959475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
1057959475
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.247829868
Short name T88
Test name
Test status
Simulation time 7334833500 ps
CPU time 76.41 seconds
Started Apr 30 02:30:14 PM PDT 24
Finished Apr 30 02:31:48 PM PDT 24
Peak memory 262940 kb
Host smart-f7590627-3ae8-4ecf-af97-dc2a83e1f49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247829868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.247829868
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.594302384
Short name T689
Test name
Test status
Simulation time 230620800 ps
CPU time 130.41 seconds
Started Apr 30 02:35:10 PM PDT 24
Finished Apr 30 02:37:21 PM PDT 24
Peak memory 263260 kb
Host smart-19cba580-259f-4644-9c2c-37985b1d2f78
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594302384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_ot
p_reset.594302384
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.3549077868
Short name T8
Test name
Test status
Simulation time 19666300 ps
CPU time 13.67 seconds
Started Apr 30 02:30:48 PM PDT 24
Finished Apr 30 02:31:19 PM PDT 24
Peak memory 257716 kb
Host smart-dc511d30-d3b2-42bf-abeb-71673d73d427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549077868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.
3549077868
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.854354992
Short name T116
Test name
Test status
Simulation time 10012127200 ps
CPU time 151.73 seconds
Started Apr 30 02:29:19 PM PDT 24
Finished Apr 30 02:31:57 PM PDT 24
Peak memory 397136 kb
Host smart-e663bdd8-6576-4a01-948f-6a551a04b517
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854354992 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.854354992
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.1951363523
Short name T51
Test name
Test status
Simulation time 3729279900 ps
CPU time 172.61 seconds
Started Apr 30 02:28:19 PM PDT 24
Finished Apr 30 02:31:13 PM PDT 24
Peak memory 283556 kb
Host smart-583f5b38-f84c-403a-b314-d5926fcbeae2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1951363523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.1951363523
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.1722950043
Short name T110
Test name
Test status
Simulation time 40210255400 ps
CPU time 946.72 seconds
Started Apr 30 02:27:23 PM PDT 24
Finished Apr 30 02:43:10 PM PDT 24
Peak memory 258620 kb
Host smart-bc494c44-25da-416a-8076-0e6834bae5b9
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722950043 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.1722950043
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.720202575
Short name T211
Test name
Test status
Simulation time 104982600 ps
CPU time 19.25 seconds
Started Apr 30 02:19:41 PM PDT 24
Finished Apr 30 02:20:01 PM PDT 24
Peak memory 263932 kb
Host smart-237d4855-0d41-44d2-9677-4ece1b07d2fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720202575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.720202575
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.1703801614
Short name T4
Test name
Test status
Simulation time 121153100 ps
CPU time 14.48 seconds
Started Apr 30 02:27:43 PM PDT 24
Finished Apr 30 02:27:58 PM PDT 24
Peak memory 274624 kb
Host smart-a8d698cb-a550-4f28-9d8f-54dc8fe6658a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1703801614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.1703801614
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.3408797801
Short name T267
Test name
Test status
Simulation time 2990548400 ps
CPU time 54.11 seconds
Started Apr 30 02:33:23 PM PDT 24
Finished Apr 30 02:34:17 PM PDT 24
Peak memory 261976 kb
Host smart-8fe48f7b-4a73-46fc-abec-9613c629f523
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408797801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.3408797801
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.1983347343
Short name T95
Test name
Test status
Simulation time 499032700 ps
CPU time 22.09 seconds
Started Apr 30 02:27:51 PM PDT 24
Finished Apr 30 02:28:14 PM PDT 24
Peak memory 264456 kb
Host smart-4f6e3f25-929f-484c-b53d-7c68e6f0b7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983347343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.1983347343
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.281455310
Short name T122
Test name
Test status
Simulation time 273370886900 ps
CPU time 2807.52 seconds
Started Apr 30 02:25:53 PM PDT 24
Finished Apr 30 03:12:42 PM PDT 24
Peak memory 264068 kb
Host smart-7f58d269-6fd8-4bdc-be01-d2a1a8f0eb58
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281455310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.flash_ctrl_host_ctrl_arb.281455310
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.1131194724
Short name T119
Test name
Test status
Simulation time 81226100 ps
CPU time 113.78 seconds
Started Apr 30 02:35:03 PM PDT 24
Finished Apr 30 02:36:57 PM PDT 24
Peak memory 262768 kb
Host smart-483ab51c-b70f-4006-98bd-24ad56aa1b6f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131194724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o
tp_reset.1131194724
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.1806600340
Short name T160
Test name
Test status
Simulation time 856134900 ps
CPU time 70.79 seconds
Started Apr 30 02:26:34 PM PDT 24
Finished Apr 30 02:27:46 PM PDT 24
Peak memory 259136 kb
Host smart-c1675dd1-9a67-412f-8874-a11860d0ff4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806600340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.1806600340
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3575002765
Short name T315
Test name
Test status
Simulation time 30092800 ps
CPU time 13.56 seconds
Started Apr 30 02:19:31 PM PDT 24
Finished Apr 30 02:19:45 PM PDT 24
Peak memory 263796 kb
Host smart-8e0bc76f-7518-4cb4-8071-fb896a097c33
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575002765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.3575002765
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.2919567828
Short name T161
Test name
Test status
Simulation time 5832579700 ps
CPU time 70.21 seconds
Started Apr 30 02:27:56 PM PDT 24
Finished Apr 30 02:29:06 PM PDT 24
Peak memory 259272 kb
Host smart-25a8874c-d9bb-4d21-a4c7-3adea3651c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919567828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.2919567828
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.3950968489
Short name T15
Test name
Test status
Simulation time 3425698100 ps
CPU time 43.9 seconds
Started Apr 30 02:34:36 PM PDT 24
Finished Apr 30 02:35:21 PM PDT 24
Peak memory 262072 kb
Host smart-515a1eaa-32bb-4bb6-8e91-2ad135a39b86
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950968489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_
hw_sec_otp.3950968489
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.3978140711
Short name T360
Test name
Test status
Simulation time 8664514200 ps
CPU time 218.19 seconds
Started Apr 30 02:32:32 PM PDT 24
Finished Apr 30 02:36:11 PM PDT 24
Peak memory 293416 kb
Host smart-119963ba-8a33-4c27-9071-545310674cb3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978140711 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.3978140711
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3555774577
Short name T67
Test name
Test status
Simulation time 717574400 ps
CPU time 41.79 seconds
Started Apr 30 02:19:25 PM PDT 24
Finished Apr 30 02:20:07 PM PDT 24
Peak memory 260336 kb
Host smart-45866988-c18a-495b-a33b-82b7acd439cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555774577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.3555774577
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.3694154019
Short name T155
Test name
Test status
Simulation time 116328100 ps
CPU time 34.4 seconds
Started Apr 30 02:29:49 PM PDT 24
Finished Apr 30 02:30:34 PM PDT 24
Peak memory 273052 kb
Host smart-100e4eb0-59e6-4820-b754-291b00311195
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694154019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.3694154019
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.2931117304
Short name T35
Test name
Test status
Simulation time 815864000 ps
CPU time 2300.19 seconds
Started Apr 30 02:26:01 PM PDT 24
Finished Apr 30 03:04:22 PM PDT 24
Peak memory 264448 kb
Host smart-4502e2f7-64ff-474d-a802-2e5515913992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931117304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.2931117304
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.3446534535
Short name T22
Test name
Test status
Simulation time 15658600 ps
CPU time 13.74 seconds
Started Apr 30 02:32:06 PM PDT 24
Finished Apr 30 02:32:29 PM PDT 24
Peak memory 259116 kb
Host smart-844dceed-7343-4923-a605-064f322bc112
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446534535 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.3446534535
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.1623815885
Short name T136
Test name
Test status
Simulation time 1014647800 ps
CPU time 77.38 seconds
Started Apr 30 02:31:47 PM PDT 24
Finished Apr 30 02:33:22 PM PDT 24
Peak memory 262292 kb
Host smart-1154826f-8461-4a7d-b204-f09e1d41723a
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623815885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.1
623815885
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.3079076070
Short name T14
Test name
Test status
Simulation time 5499403400 ps
CPU time 184.82 seconds
Started Apr 30 02:29:12 PM PDT 24
Finished Apr 30 02:32:24 PM PDT 24
Peak memory 293516 kb
Host smart-3f160b94-47d0-4be9-99e2-f1ea4960515a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079076070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_intr_rd.3079076070
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3549072288
Short name T376
Test name
Test status
Simulation time 1485497700 ps
CPU time 913.59 seconds
Started Apr 30 02:20:00 PM PDT 24
Finished Apr 30 02:35:14 PM PDT 24
Peak memory 262016 kb
Host smart-d61d4c04-5793-469c-96ef-b236e79483b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549072288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.3549072288
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.2476006815
Short name T355
Test name
Test status
Simulation time 16733741300 ps
CPU time 202.22 seconds
Started Apr 30 02:32:10 PM PDT 24
Finished Apr 30 02:35:40 PM PDT 24
Peak memory 284308 kb
Host smart-3944bace-1235-49f5-a207-c9e86266e989
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476006815 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.2476006815
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.3309757542
Short name T167
Test name
Test status
Simulation time 793327700 ps
CPU time 787.69 seconds
Started Apr 30 02:25:57 PM PDT 24
Finished Apr 30 02:39:06 PM PDT 24
Peak memory 264460 kb
Host smart-40e72c41-7a65-43da-bb9b-e8fd77f3ea69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309757542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.3309757542
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3963479238
Short name T1079
Test name
Test status
Simulation time 69795900 ps
CPU time 16.52 seconds
Started Apr 30 02:19:55 PM PDT 24
Finished Apr 30 02:20:12 PM PDT 24
Peak memory 263812 kb
Host smart-43111574-4da2-4d6e-bc25-361bb81b2275
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963479238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
3963479238
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.3254137252
Short name T157
Test name
Test status
Simulation time 913147000 ps
CPU time 17.45 seconds
Started Apr 30 02:26:56 PM PDT 24
Finished Apr 30 02:27:14 PM PDT 24
Peak memory 263260 kb
Host smart-8ae6c5b7-aad0-479d-a457-74e8eb7c357b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254137252 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.3254137252
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.2993443255
Short name T129
Test name
Test status
Simulation time 3910170300 ps
CPU time 617.9 seconds
Started Apr 30 02:31:56 PM PDT 24
Finished Apr 30 02:42:29 PM PDT 24
Peak memory 309148 kb
Host smart-466d0c0b-dab2-4c21-b811-68d9e1b0eb71
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993443255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.flash_ctrl_rw.2993443255
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2410997176
Short name T234
Test name
Test status
Simulation time 17623300 ps
CPU time 13.87 seconds
Started Apr 30 02:20:10 PM PDT 24
Finished Apr 30 02:20:24 PM PDT 24
Peak memory 262436 kb
Host smart-331e1dd7-fc9b-4408-853c-74b55c427eba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410997176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
2410997176
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2595235731
Short name T212
Test name
Test status
Simulation time 1503494300 ps
CPU time 767.54 seconds
Started Apr 30 02:19:37 PM PDT 24
Finished Apr 30 02:32:25 PM PDT 24
Peak memory 261844 kb
Host smart-86217369-8aa1-43ba-976c-c3b2e64f73a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595235731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.2595235731
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.1991895428
Short name T362
Test name
Test status
Simulation time 304545000 ps
CPU time 36.04 seconds
Started Apr 30 02:30:14 PM PDT 24
Finished Apr 30 02:31:08 PM PDT 24
Peak memory 271460 kb
Host smart-7a6c260c-4f7f-4f0b-b9f0-622628c48b93
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991895428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_re_evict.1991895428
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.50372300
Short name T200
Test name
Test status
Simulation time 68251200 ps
CPU time 32.64 seconds
Started Apr 30 02:26:12 PM PDT 24
Finished Apr 30 02:26:45 PM PDT 24
Peak memory 270512 kb
Host smart-5d439c2f-43b6-4cf6-ac19-87efece546d4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50372300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.flash_ctrl_rd_intg.50372300
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.1144558570
Short name T49
Test name
Test status
Simulation time 7803168800 ps
CPU time 67.09 seconds
Started Apr 30 02:28:25 PM PDT 24
Finished Apr 30 02:29:33 PM PDT 24
Peak memory 262004 kb
Host smart-29b0e16a-4dc7-4052-a2a7-327e1a63cd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144558570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.1144558570
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3019873668
Short name T373
Test name
Test status
Simulation time 3441479800 ps
CPU time 913.34 seconds
Started Apr 30 02:19:39 PM PDT 24
Finished Apr 30 02:34:53 PM PDT 24
Peak memory 263932 kb
Host smart-6d874ec9-3e4a-4dd1-a1b7-eb3ad8db5c7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019873668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.3019873668
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.1910872769
Short name T911
Test name
Test status
Simulation time 8174729800 ps
CPU time 607.84 seconds
Started Apr 30 02:25:59 PM PDT 24
Finished Apr 30 02:36:08 PM PDT 24
Peak memory 309140 kb
Host smart-d5ff68c2-cd65-43e9-8784-7ba71bbda497
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910872769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.flash_ctrl_rw.1910872769
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.269353293
Short name T56
Test name
Test status
Simulation time 20757100 ps
CPU time 21.99 seconds
Started Apr 30 02:29:49 PM PDT 24
Finished Apr 30 02:30:21 PM PDT 24
Peak memory 273084 kb
Host smart-86f0ae21-bc6f-45ff-9ad4-2b804163483a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269353293 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.269353293
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.4213365517
Short name T76
Test name
Test status
Simulation time 334666787400 ps
CPU time 2035.02 seconds
Started Apr 30 02:25:55 PM PDT 24
Finished Apr 30 02:59:52 PM PDT 24
Peak memory 262704 kb
Host smart-8dd15a08-aa37-40c5-bd75-d511dae59f38
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213365517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.flash_ctrl_hw_rma.4213365517
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.65929756
Short name T96
Test name
Test status
Simulation time 905541000 ps
CPU time 22.1 seconds
Started Apr 30 02:26:14 PM PDT 24
Finished Apr 30 02:26:37 PM PDT 24
Peak memory 264716 kb
Host smart-c91cb83a-aa64-4256-ad1f-d1e07e240632
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65929756 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.65929756
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.398145240
Short name T81
Test name
Test status
Simulation time 17193800 ps
CPU time 13.34 seconds
Started Apr 30 02:32:11 PM PDT 24
Finished Apr 30 02:32:31 PM PDT 24
Peak memory 275268 kb
Host smart-472ec497-7547-4eb8-b742-a8787efd26b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398145240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.398145240
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.2502638272
Short name T130
Test name
Test status
Simulation time 31376691200 ps
CPU time 241.75 seconds
Started Apr 30 02:28:43 PM PDT 24
Finished Apr 30 02:32:46 PM PDT 24
Peak memory 272960 kb
Host smart-d13c44c6-8feb-448a-a80c-e0bddf78b8d2
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502638272 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_mp_regions.2502638272
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.97344738
Short name T469
Test name
Test status
Simulation time 53753000 ps
CPU time 13.41 seconds
Started Apr 30 02:26:24 PM PDT 24
Finished Apr 30 02:26:38 PM PDT 24
Peak memory 257940 kb
Host smart-b9acb8e6-6377-4b4c-ac9f-bc4845d390c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97344738 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.97344738
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.1726258610
Short name T261
Test name
Test status
Simulation time 589149900 ps
CPU time 66.79 seconds
Started Apr 30 02:28:48 PM PDT 24
Finished Apr 30 02:29:55 PM PDT 24
Peak memory 262128 kb
Host smart-1b323c0d-8dc1-4aa6-85a7-17326df7d1dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726258610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.1726258610
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2155864789
Short name T241
Test name
Test status
Simulation time 225630000 ps
CPU time 19.56 seconds
Started Apr 30 02:19:59 PM PDT 24
Finished Apr 30 02:20:19 PM PDT 24
Peak memory 263908 kb
Host smart-0cefec66-322e-4e55-956b-4e3e3b0eee6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155864789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.
2155864789
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.4258419811
Short name T356
Test name
Test status
Simulation time 11155706400 ps
CPU time 212.03 seconds
Started Apr 30 02:33:50 PM PDT 24
Finished Apr 30 02:37:23 PM PDT 24
Peak memory 284424 kb
Host smart-31baf29f-1e64-4273-9929-d51c1e3e9f94
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258419811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla
sh_ctrl_intr_rd.4258419811
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.983612704
Short name T31
Test name
Test status
Simulation time 31193300 ps
CPU time 22.08 seconds
Started Apr 30 02:33:53 PM PDT 24
Finished Apr 30 02:34:16 PM PDT 24
Peak memory 280396 kb
Host smart-311c001b-9cb8-49eb-9347-00e4b6b296a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983612704 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.983612704
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.1485530633
Short name T695
Test name
Test status
Simulation time 24800900 ps
CPU time 13.79 seconds
Started Apr 30 02:26:18 PM PDT 24
Finished Apr 30 02:26:32 PM PDT 24
Peak memory 264692 kb
Host smart-3239a320-4833-4098-a9f6-158bc13d26d4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485530633 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.1485530633
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2721856154
Short name T336
Test name
Test status
Simulation time 10061335900 ps
CPU time 67.72 seconds
Started Apr 30 02:27:01 PM PDT 24
Finished Apr 30 02:28:10 PM PDT 24
Peak memory 264724 kb
Host smart-68409bd3-7182-48cc-b45f-6da7d3e8c28d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721856154 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.2721856154
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.411149213
Short name T335
Test name
Test status
Simulation time 10039914000 ps
CPU time 57.77 seconds
Started Apr 30 02:29:42 PM PDT 24
Finished Apr 30 02:30:47 PM PDT 24
Peak memory 267700 kb
Host smart-bf15fcb7-07cf-47dd-a06e-fb559d3e6295
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411149213 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.411149213
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.516160323
Short name T379
Test name
Test status
Simulation time 3301857700 ps
CPU time 901.98 seconds
Started Apr 30 02:19:58 PM PDT 24
Finished Apr 30 02:35:00 PM PDT 24
Peak memory 263952 kb
Host smart-8ce5925c-a102-4f58-a827-080259c7b6c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516160323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl
_tl_intg_err.516160323
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.3957677952
Short name T402
Test name
Test status
Simulation time 1573338300 ps
CPU time 52.02 seconds
Started Apr 30 02:30:33 PM PDT 24
Finished Apr 30 02:31:44 PM PDT 24
Peak memory 261628 kb
Host smart-91c23430-ff2f-414a-a800-4241fcd6550e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957677952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.3957677952
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.1571873421
Short name T182
Test name
Test status
Simulation time 2736396000 ps
CPU time 71.58 seconds
Started Apr 30 02:32:09 PM PDT 24
Finished Apr 30 02:33:29 PM PDT 24
Peak memory 262368 kb
Host smart-2fa1bf3b-a64b-451f-b916-d39eb1c5c344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571873421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.1571873421
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.1980508470
Short name T405
Test name
Test status
Simulation time 1411765400 ps
CPU time 73.61 seconds
Started Apr 30 02:34:29 PM PDT 24
Finished Apr 30 02:35:43 PM PDT 24
Peak memory 264420 kb
Host smart-65f3a0c4-472d-488a-961b-0401c196f94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980508470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.1980508470
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.277328055
Short name T23
Test name
Test status
Simulation time 75093200 ps
CPU time 13.91 seconds
Started Apr 30 02:26:57 PM PDT 24
Finished Apr 30 02:27:12 PM PDT 24
Peak memory 264436 kb
Host smart-991ae339-7021-4376-9f3b-e9d780a967b8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277328055 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.277328055
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.2071232690
Short name T64
Test name
Test status
Simulation time 178044900 ps
CPU time 80.47 seconds
Started Apr 30 02:25:53 PM PDT 24
Finished Apr 30 02:27:15 PM PDT 24
Peak memory 261688 kb
Host smart-5f2fb5b4-eb0d-4de9-bb9a-3ce18bbe612d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2071232690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.2071232690
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.3735633812
Short name T203
Test name
Test status
Simulation time 70133900 ps
CPU time 14.25 seconds
Started Apr 30 02:26:12 PM PDT 24
Finished Apr 30 02:26:27 PM PDT 24
Peak memory 261412 kb
Host smart-f3bceac7-cc38-4c34-a6b7-db8819ea9745
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735633812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.flash_ctrl_config_regwen.3735633812
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.1418230491
Short name T83
Test name
Test status
Simulation time 75549900 ps
CPU time 30.19 seconds
Started Apr 30 02:29:37 PM PDT 24
Finished Apr 30 02:30:15 PM PDT 24
Peak memory 267100 kb
Host smart-b575f931-96a3-4ac3-a3d3-891f2c6194cc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418230491 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.1418230491
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.1699767916
Short name T59
Test name
Test status
Simulation time 26544500 ps
CPU time 21.95 seconds
Started Apr 30 02:26:54 PM PDT 24
Finished Apr 30 02:27:17 PM PDT 24
Peak memory 280124 kb
Host smart-b318d5e9-edfd-43b3-a333-c4c3a78dfe7f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699767916 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.1699767916
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.1074670699
Short name T368
Test name
Test status
Simulation time 142641200 ps
CPU time 32.61 seconds
Started Apr 30 02:30:38 PM PDT 24
Finished Apr 30 02:31:30 PM PDT 24
Peak memory 269372 kb
Host smart-905fe349-836e-4266-a5d4-0ac9fdc85813
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074670699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.1074670699
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.1075727005
Short name T420
Test name
Test status
Simulation time 2289142600 ps
CPU time 158.89 seconds
Started Apr 30 02:27:18 PM PDT 24
Finished Apr 30 02:29:58 PM PDT 24
Peak memory 293680 kb
Host smart-e1b058fa-0787-46b7-8f5b-642d2faeb447
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075727005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_intr_rd.1075727005
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.3312334520
Short name T609
Test name
Test status
Simulation time 33932101900 ps
CPU time 205.61 seconds
Started Apr 30 02:27:57 PM PDT 24
Finished Apr 30 02:31:23 PM PDT 24
Peak memory 284244 kb
Host smart-593d7785-1218-4660-b7ed-077b4fd7787a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312334520 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.3312334520
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.855134708
Short name T472
Test name
Test status
Simulation time 19564000 ps
CPU time 13.81 seconds
Started Apr 30 02:27:00 PM PDT 24
Finished Apr 30 02:27:15 PM PDT 24
Peak memory 259196 kb
Host smart-9fa27ad7-bd06-4294-b363-97a6675cc557
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855134708 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.855134708
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.4016842010
Short name T247
Test name
Test status
Simulation time 1393321400 ps
CPU time 907.68 seconds
Started Apr 30 02:19:59 PM PDT 24
Finished Apr 30 02:35:07 PM PDT 24
Peak memory 263936 kb
Host smart-1e101d0e-7007-43b2-9fed-fa99efedf2f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016842010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.4016842010
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2029851217
Short name T238
Test name
Test status
Simulation time 182911400 ps
CPU time 394.37 seconds
Started Apr 30 02:19:26 PM PDT 24
Finished Apr 30 02:26:01 PM PDT 24
Peak memory 260396 kb
Host smart-146ef369-4581-47c0-85ad-b9b40a479a5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029851217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_tl_intg_err.2029851217
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.2880716953
Short name T186
Test name
Test status
Simulation time 54355200 ps
CPU time 27.93 seconds
Started Apr 30 02:29:59 PM PDT 24
Finished Apr 30 02:30:40 PM PDT 24
Peak memory 274516 kb
Host smart-a7a8e8f6-1c40-440f-aebb-b5a1aa496925
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880716953 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.2880716953
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.1792310299
Short name T206
Test name
Test status
Simulation time 26462700 ps
CPU time 13.53 seconds
Started Apr 30 02:30:20 PM PDT 24
Finished Apr 30 02:30:51 PM PDT 24
Peak memory 258796 kb
Host smart-c0d43102-6cc1-4c21-a33e-bd2c8ad56170
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792310299 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.1792310299
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.3635865072
Short name T400
Test name
Test status
Simulation time 14964900 ps
CPU time 22.37 seconds
Started Apr 30 02:30:32 PM PDT 24
Finished Apr 30 02:31:13 PM PDT 24
Peak memory 279980 kb
Host smart-bba601b7-089a-4827-9a55-37654b56f8fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635865072 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.3635865072
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.440448059
Short name T915
Test name
Test status
Simulation time 3647935900 ps
CPU time 79.08 seconds
Started Apr 30 02:27:16 PM PDT 24
Finished Apr 30 02:28:36 PM PDT 24
Peak memory 262848 kb
Host smart-48398cbf-7d9d-42cd-860e-56175d58ba30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440448059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.440448059
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.4074599686
Short name T396
Test name
Test status
Simulation time 39148200 ps
CPU time 132.66 seconds
Started Apr 30 02:32:18 PM PDT 24
Finished Apr 30 02:34:32 PM PDT 24
Peak memory 259280 kb
Host smart-417f7732-ab9c-4afc-995f-1e348e6a60e7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074599686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o
tp_reset.4074599686
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.17059386
Short name T404
Test name
Test status
Simulation time 2991107500 ps
CPU time 72.3 seconds
Started Apr 30 02:32:29 PM PDT 24
Finished Apr 30 02:33:42 PM PDT 24
Peak memory 264128 kb
Host smart-0cd1cbf9-ef56-4dc9-9f4f-af36086f2988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17059386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.17059386
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.62695270
Short name T386
Test name
Test status
Simulation time 74704300 ps
CPU time 22.61 seconds
Started Apr 30 02:32:32 PM PDT 24
Finished Apr 30 02:32:55 PM PDT 24
Peak memory 280320 kb
Host smart-dee6e1e0-cef4-4a0f-a40c-2dc662fd539d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62695270 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.flash_ctrl_disable.62695270
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.1273556356
Short name T365
Test name
Test status
Simulation time 28418000 ps
CPU time 28.95 seconds
Started Apr 30 02:33:08 PM PDT 24
Finished Apr 30 02:33:37 PM PDT 24
Peak memory 274552 kb
Host smart-e904fc83-2905-4825-aa48-bfb9d3f134d1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273556356 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.1273556356
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.4225143246
Short name T395
Test name
Test status
Simulation time 144618800 ps
CPU time 132.46 seconds
Started Apr 30 02:34:17 PM PDT 24
Finished Apr 30 02:36:30 PM PDT 24
Peak memory 263140 kb
Host smart-91fb64e1-196a-4a47-984e-3de3fa45dd13
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225143246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o
tp_reset.4225143246
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.3732410815
Short name T169
Test name
Test status
Simulation time 41715100 ps
CPU time 133.23 seconds
Started Apr 30 02:26:29 PM PDT 24
Finished Apr 30 02:28:42 PM PDT 24
Peak memory 264176 kb
Host smart-1889ea72-208a-4d69-97ce-f3af48b1e09f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732410815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot
p_reset.3732410815
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2802802770
Short name T248
Test name
Test status
Simulation time 66725500 ps
CPU time 16.71 seconds
Started Apr 30 02:19:33 PM PDT 24
Finished Apr 30 02:19:50 PM PDT 24
Peak memory 263912 kb
Host smart-b7549606-373f-4077-9d9f-8da81d22f3a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802802770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.2
802802770
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.829838295
Short name T24
Test name
Test status
Simulation time 14922200 ps
CPU time 14.21 seconds
Started Apr 30 02:28:01 PM PDT 24
Finished Apr 30 02:28:16 PM PDT 24
Peak memory 261388 kb
Host smart-d01a071b-a826-45b7-9500-2340d16baf75
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829838295 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.829838295
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1072592729
Short name T253
Test name
Test status
Simulation time 135426000 ps
CPU time 16.14 seconds
Started Apr 30 02:19:46 PM PDT 24
Finished Apr 30 02:20:03 PM PDT 24
Peak memory 263844 kb
Host smart-2ec487d2-49dc-45e4-bbb3-9d2102c53be5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072592729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.1
072592729
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.628670362
Short name T101
Test name
Test status
Simulation time 760426451400 ps
CPU time 1502.71 seconds
Started Apr 30 02:30:50 PM PDT 24
Finished Apr 30 02:56:11 PM PDT 24
Peak memory 263876 kb
Host smart-a7e3bbef-0cc8-4ec7-abf8-4c411c9ab1a1
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628670362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.flash_ctrl_hw_rma_reset.628670362
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.2710736437
Short name T107
Test name
Test status
Simulation time 71970400 ps
CPU time 112.63 seconds
Started Apr 30 02:30:51 PM PDT 24
Finished Apr 30 02:33:01 PM PDT 24
Peak memory 260912 kb
Host smart-470a7506-5694-4583-8e43-2dae291ce7e6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710736437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o
tp_reset.2710736437
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.3842748712
Short name T109
Test name
Test status
Simulation time 320250714800 ps
CPU time 889.58 seconds
Started Apr 30 02:31:38 PM PDT 24
Finished Apr 30 02:46:47 PM PDT 24
Peak memory 262920 kb
Host smart-682de915-9f0f-460c-a5a2-cb5153ba863b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842748712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.flash_ctrl_hw_rma_reset.3842748712
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.3959850703
Short name T142
Test name
Test status
Simulation time 95509600 ps
CPU time 14.1 seconds
Started Apr 30 02:28:02 PM PDT 24
Finished Apr 30 02:28:17 PM PDT 24
Peak memory 261096 kb
Host smart-b0b5e0a8-f120-4562-a23b-155aefee6cad
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3959850703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.3959850703
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2624990946
Short name T252
Test name
Test status
Simulation time 539752300 ps
CPU time 466.42 seconds
Started Apr 30 02:19:43 PM PDT 24
Finished Apr 30 02:27:30 PM PDT 24
Peak memory 263968 kb
Host smart-4d8e2b9d-59e4-49c7-a4cd-8e85a890ac2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624990946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl
_tl_intg_err.2624990946
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.2022276313
Short name T2
Test name
Test status
Simulation time 9034063000 ps
CPU time 2492.28 seconds
Started Apr 30 02:25:59 PM PDT 24
Finished Apr 30 03:07:33 PM PDT 24
Peak memory 263424 kb
Host smart-4afa8749-814b-4c3f-86f6-c05fbfbc5122
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022276313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_err
or_mp.2022276313
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.3913802015
Short name T193
Test name
Test status
Simulation time 822936267200 ps
CPU time 1620.62 seconds
Started Apr 30 02:26:28 PM PDT 24
Finished Apr 30 02:53:29 PM PDT 24
Peak memory 264580 kb
Host smart-9c1b6996-4adb-45a0-9285-6532cd2d7522
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913802015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_host_ctrl_arb.3913802015
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.3510424671
Short name T19
Test name
Test status
Simulation time 87174800 ps
CPU time 14.97 seconds
Started Apr 30 02:26:58 PM PDT 24
Finished Apr 30 02:27:14 PM PDT 24
Peak memory 264568 kb
Host smart-d226d24e-ba31-4737-8b1c-6db4f8c69e2d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510424671 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.3510424671
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.2702885311
Short name T159
Test name
Test status
Simulation time 644555200 ps
CPU time 23.53 seconds
Started Apr 30 02:27:44 PM PDT 24
Finished Apr 30 02:28:09 PM PDT 24
Peak memory 264772 kb
Host smart-53e74cd7-4bd4-4a2a-bb9a-72aaf265278c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702885311 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.2702885311
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.1912022213
Short name T77
Test name
Test status
Simulation time 786949696800 ps
CPU time 1946.34 seconds
Started Apr 30 02:27:54 PM PDT 24
Finished Apr 30 03:00:21 PM PDT 24
Peak memory 264620 kb
Host smart-b9c7dcd1-69c4-4248-8ec8-f19b36665054
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912022213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_host_ctrl_arb.1912022213
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.2218566486
Short name T195
Test name
Test status
Simulation time 1190732400 ps
CPU time 128.64 seconds
Started Apr 30 02:28:16 PM PDT 24
Finished Apr 30 02:30:25 PM PDT 24
Peak memory 289528 kb
Host smart-e40267f7-a936-4c76-8694-3a05c37db918
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218566486 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.2218566486
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1996960887
Short name T346
Test name
Test status
Simulation time 10893804500 ps
CPU time 68.84 seconds
Started Apr 30 02:19:27 PM PDT 24
Finished Apr 30 02:20:36 PM PDT 24
Peak memory 260436 kb
Host smart-9ad5fba8-ae28-4a9e-bc53-2d636e5f28e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996960887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.1996960887
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3351796940
Short name T382
Test name
Test status
Simulation time 2469231300 ps
CPU time 50.06 seconds
Started Apr 30 02:19:26 PM PDT 24
Finished Apr 30 02:20:16 PM PDT 24
Peak memory 261908 kb
Host smart-1f5dc526-c70c-4f9b-8578-643ecea4672a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351796940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.3351796940
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2382099005
Short name T224
Test name
Test status
Simulation time 187763700 ps
CPU time 46.08 seconds
Started Apr 30 02:19:21 PM PDT 24
Finished Apr 30 02:20:07 PM PDT 24
Peak memory 260396 kb
Host smart-04630db1-74c2-4848-a352-f092eefa7b8a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382099005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.2382099005
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1552621272
Short name T1034
Test name
Test status
Simulation time 24365800 ps
CPU time 14.98 seconds
Started Apr 30 02:19:27 PM PDT 24
Finished Apr 30 02:19:43 PM PDT 24
Peak memory 277012 kb
Host smart-083f17b5-af54-4f31-8162-5e127f1bd033
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552621272 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.1552621272
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2719922190
Short name T996
Test name
Test status
Simulation time 99235200 ps
CPU time 16.69 seconds
Started Apr 30 02:19:20 PM PDT 24
Finished Apr 30 02:19:37 PM PDT 24
Peak memory 260268 kb
Host smart-3a44bb71-5f5f-46a9-a554-7d47e38fb38f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719922190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.2719922190
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3067231405
Short name T347
Test name
Test status
Simulation time 18945200 ps
CPU time 13.5 seconds
Started Apr 30 02:19:20 PM PDT 24
Finished Apr 30 02:19:34 PM PDT 24
Peak memory 262656 kb
Host smart-a06b436c-f481-4ea9-9eca-a7f04d80e105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067231405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.3
067231405
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3499471419
Short name T318
Test name
Test status
Simulation time 49641600 ps
CPU time 13.81 seconds
Started Apr 30 02:19:23 PM PDT 24
Finished Apr 30 02:19:37 PM PDT 24
Peak memory 260940 kb
Host smart-037890d8-8bd1-468b-af83-bbda874abf2a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499471419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_mem_partial_access.3499471419
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3241067971
Short name T1076
Test name
Test status
Simulation time 15177400 ps
CPU time 13.47 seconds
Started Apr 30 02:19:20 PM PDT 24
Finished Apr 30 02:19:34 PM PDT 24
Peak memory 262600 kb
Host smart-dd5a4412-3670-40db-a340-7ff9c7b0bf34
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241067971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.3241067971
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.823835093
Short name T1024
Test name
Test status
Simulation time 211641200 ps
CPU time 36.62 seconds
Started Apr 30 02:19:26 PM PDT 24
Finished Apr 30 02:20:03 PM PDT 24
Peak memory 260316 kb
Host smart-0dfcd122-0af1-4a47-b75a-3d6444d177ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823835093 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.823835093
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1485375870
Short name T1090
Test name
Test status
Simulation time 13331100 ps
CPU time 16.19 seconds
Started Apr 30 02:19:24 PM PDT 24
Finished Apr 30 02:19:41 PM PDT 24
Peak memory 260272 kb
Host smart-245622d2-ed76-48cc-bc7b-8e820457b049
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485375870 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.1485375870
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1688715267
Short name T1061
Test name
Test status
Simulation time 44151400 ps
CPU time 15.74 seconds
Started Apr 30 02:19:19 PM PDT 24
Finished Apr 30 02:19:35 PM PDT 24
Peak memory 260288 kb
Host smart-5e1447a6-1ff7-4277-b7d9-5f7f873569d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688715267 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.1688715267
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3320653687
Short name T209
Test name
Test status
Simulation time 53024600 ps
CPU time 19.02 seconds
Started Apr 30 02:19:20 PM PDT 24
Finished Apr 30 02:19:39 PM PDT 24
Peak memory 263912 kb
Host smart-f57456cf-c9f2-45bb-8137-1fb46fb7a791
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320653687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.3
320653687
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3285141675
Short name T1044
Test name
Test status
Simulation time 681610700 ps
CPU time 456.84 seconds
Started Apr 30 02:19:19 PM PDT 24
Finished Apr 30 02:26:57 PM PDT 24
Peak memory 263932 kb
Host smart-a0db1c23-ff76-4fab-8838-d3e8aafed835
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285141675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl
_tl_intg_err.3285141675
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1114705958
Short name T343
Test name
Test status
Simulation time 1783001200 ps
CPU time 41.89 seconds
Started Apr 30 02:19:26 PM PDT 24
Finished Apr 30 02:20:08 PM PDT 24
Peak memory 260264 kb
Host smart-166aa998-c862-4b7b-ae15-28a1e459e7d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114705958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.1114705958
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.4042489300
Short name T1053
Test name
Test status
Simulation time 31308900 ps
CPU time 26.41 seconds
Started Apr 30 02:19:28 PM PDT 24
Finished Apr 30 02:19:55 PM PDT 24
Peak memory 260408 kb
Host smart-3fb185fc-e8e2-4c8f-86f7-566375e9c86d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042489300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_hw_reset.4042489300
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2677193078
Short name T976
Test name
Test status
Simulation time 88311200 ps
CPU time 16.81 seconds
Started Apr 30 02:19:26 PM PDT 24
Finished Apr 30 02:19:44 PM PDT 24
Peak memory 278700 kb
Host smart-ea7ec427-96ab-4c9d-a107-aadf5293143f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677193078 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.2677193078
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2030758162
Short name T228
Test name
Test status
Simulation time 65727900 ps
CPU time 14.44 seconds
Started Apr 30 02:19:26 PM PDT 24
Finished Apr 30 02:19:41 PM PDT 24
Peak memory 260400 kb
Host smart-a06ecd71-79da-4bbd-b181-b9393afd918e
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030758162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.2030758162
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.268365071
Short name T1057
Test name
Test status
Simulation time 14993400 ps
CPU time 13.63 seconds
Started Apr 30 02:19:25 PM PDT 24
Finished Apr 30 02:19:39 PM PDT 24
Peak memory 262332 kb
Host smart-32aa2e1b-881c-4949-aed2-062616594d8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268365071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.268365071
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2418665594
Short name T317
Test name
Test status
Simulation time 46534600 ps
CPU time 13.95 seconds
Started Apr 30 02:19:26 PM PDT 24
Finished Apr 30 02:19:40 PM PDT 24
Peak memory 263744 kb
Host smart-21407056-e2e3-4a04-8a98-095f29e11dd0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418665594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.2418665594
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.907556393
Short name T981
Test name
Test status
Simulation time 17460600 ps
CPU time 13.31 seconds
Started Apr 30 02:19:29 PM PDT 24
Finished Apr 30 02:19:43 PM PDT 24
Peak memory 260908 kb
Host smart-c5c5bbbb-0ac5-44aa-9cc1-edf923840241
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907556393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem
_walk.907556393
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2335874573
Short name T226
Test name
Test status
Simulation time 138759900 ps
CPU time 16.29 seconds
Started Apr 30 02:19:26 PM PDT 24
Finished Apr 30 02:19:43 PM PDT 24
Peak memory 263904 kb
Host smart-e026d37b-5df6-49a4-a211-3164f3f1da6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335874573 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.2335874573
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3041622119
Short name T964
Test name
Test status
Simulation time 80040600 ps
CPU time 15.7 seconds
Started Apr 30 02:19:28 PM PDT 24
Finished Apr 30 02:19:44 PM PDT 24
Peak memory 260408 kb
Host smart-2c6b5779-abb4-4589-b61d-907f3a39219f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041622119 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.3041622119
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1282602328
Short name T955
Test name
Test status
Simulation time 42898400 ps
CPU time 13.21 seconds
Started Apr 30 02:19:30 PM PDT 24
Finished Apr 30 02:19:44 PM PDT 24
Peak memory 260408 kb
Host smart-e3ceb56c-f2bb-4f5b-913b-3de8a199bf12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282602328 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.1282602328
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3854342606
Short name T231
Test name
Test status
Simulation time 149134400 ps
CPU time 17.39 seconds
Started Apr 30 02:19:26 PM PDT 24
Finished Apr 30 02:19:44 PM PDT 24
Peak memory 260972 kb
Host smart-1db83772-ac82-4a20-a4a9-8225dd8a61fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854342606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.3
854342606
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2053748496
Short name T374
Test name
Test status
Simulation time 1260288000 ps
CPU time 913.2 seconds
Started Apr 30 02:19:29 PM PDT 24
Finished Apr 30 02:34:43 PM PDT 24
Peak memory 261592 kb
Host smart-0f77a8e4-04b5-4c70-8574-16e068a382c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053748496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.2053748496
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3418959971
Short name T372
Test name
Test status
Simulation time 48884500 ps
CPU time 15.32 seconds
Started Apr 30 02:19:46 PM PDT 24
Finished Apr 30 02:20:02 PM PDT 24
Peak memory 271984 kb
Host smart-aa24ab78-ebb8-4f7a-9410-700cf283cf5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418959971 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.3418959971
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2267013638
Short name T969
Test name
Test status
Simulation time 205197400 ps
CPU time 17.33 seconds
Started Apr 30 02:19:48 PM PDT 24
Finished Apr 30 02:20:06 PM PDT 24
Peak memory 260416 kb
Host smart-e878c1c5-a877-416e-b371-e9cd9feea40f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267013638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_csr_rw.2267013638
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.846996554
Short name T961
Test name
Test status
Simulation time 63391900 ps
CPU time 13.81 seconds
Started Apr 30 02:19:47 PM PDT 24
Finished Apr 30 02:20:01 PM PDT 24
Peak memory 262752 kb
Host smart-cc042b92-1749-4bb7-9faa-621049f5841b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846996554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.846996554
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.986906122
Short name T331
Test name
Test status
Simulation time 168053100 ps
CPU time 22.2 seconds
Started Apr 30 02:19:46 PM PDT 24
Finished Apr 30 02:20:10 PM PDT 24
Peak memory 260328 kb
Host smart-75317adb-7c65-458b-a4d3-0a725f40eea4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986906122 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.986906122
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2957921661
Short name T979
Test name
Test status
Simulation time 19931000 ps
CPU time 13.47 seconds
Started Apr 30 02:19:45 PM PDT 24
Finished Apr 30 02:19:59 PM PDT 24
Peak memory 260344 kb
Host smart-65ff2ee9-70c5-4fe7-b80a-9e839843edea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957921661 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.2957921661
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1326112378
Short name T1047
Test name
Test status
Simulation time 14717400 ps
CPU time 13.42 seconds
Started Apr 30 02:19:46 PM PDT 24
Finished Apr 30 02:20:00 PM PDT 24
Peak memory 260412 kb
Host smart-0b8767a4-ba2c-489c-89cb-4d2b9c40cd54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326112378 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.1326112378
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1149374491
Short name T1083
Test name
Test status
Simulation time 196174800 ps
CPU time 19.56 seconds
Started Apr 30 02:19:46 PM PDT 24
Finished Apr 30 02:20:07 PM PDT 24
Peak memory 263828 kb
Host smart-57bf36b1-1068-4e2b-8dc0-b35e5d110cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149374491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
1149374491
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1889310626
Short name T1018
Test name
Test status
Simulation time 862048300 ps
CPU time 917.05 seconds
Started Apr 30 02:19:46 PM PDT 24
Finished Apr 30 02:35:04 PM PDT 24
Peak memory 263952 kb
Host smart-9d446360-0665-4d9b-a613-6a57102e31dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889310626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr
l_tl_intg_err.1889310626
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.4218714696
Short name T995
Test name
Test status
Simulation time 120345800 ps
CPU time 17.61 seconds
Started Apr 30 02:19:46 PM PDT 24
Finished Apr 30 02:20:05 PM PDT 24
Peak memory 271996 kb
Host smart-9424b94f-f907-4f90-9bfe-4b22e2a15782
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218714696 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.4218714696
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3170110628
Short name T1038
Test name
Test status
Simulation time 285840600 ps
CPU time 16.81 seconds
Started Apr 30 02:19:46 PM PDT 24
Finished Apr 30 02:20:04 PM PDT 24
Peak memory 260388 kb
Host smart-94aec263-fda3-4b5f-acd5-6a1619b601c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170110628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_csr_rw.3170110628
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.3017182244
Short name T1039
Test name
Test status
Simulation time 24952500 ps
CPU time 14.06 seconds
Started Apr 30 02:19:47 PM PDT 24
Finished Apr 30 02:20:02 PM PDT 24
Peak memory 262536 kb
Host smart-7cbbc033-c331-4e0b-84ef-ea230fbd581c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017182244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.
3017182244
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.419469695
Short name T983
Test name
Test status
Simulation time 235729000 ps
CPU time 19.71 seconds
Started Apr 30 02:19:45 PM PDT 24
Finished Apr 30 02:20:06 PM PDT 24
Peak memory 263764 kb
Host smart-effe2707-7414-4745-b9c1-dc46d04af65b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419469695 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.419469695
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.4239858206
Short name T959
Test name
Test status
Simulation time 13482800 ps
CPU time 15.85 seconds
Started Apr 30 02:19:46 PM PDT 24
Finished Apr 30 02:20:03 PM PDT 24
Peak memory 260416 kb
Host smart-a9232918-948c-43f9-8179-cef87819daa3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239858206 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.4239858206
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3845348636
Short name T1062
Test name
Test status
Simulation time 22643600 ps
CPU time 16.07 seconds
Started Apr 30 02:19:44 PM PDT 24
Finished Apr 30 02:20:00 PM PDT 24
Peak memory 260308 kb
Host smart-9655dc3d-7c73-49e9-9976-f536d9f4e7b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845348636 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.3845348636
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.582190758
Short name T245
Test name
Test status
Simulation time 176198200 ps
CPU time 17.69 seconds
Started Apr 30 02:19:46 PM PDT 24
Finished Apr 30 02:20:04 PM PDT 24
Peak memory 263780 kb
Host smart-972ec1bb-5b06-4418-bab7-0d913415a71e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582190758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.582190758
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3647427984
Short name T1070
Test name
Test status
Simulation time 42458700 ps
CPU time 18 seconds
Started Apr 30 02:19:53 PM PDT 24
Finished Apr 30 02:20:12 PM PDT 24
Peak memory 271992 kb
Host smart-286eeef4-b9e8-4027-b484-12f9b1535932
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647427984 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.3647427984
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3692497999
Short name T965
Test name
Test status
Simulation time 99452200 ps
CPU time 17.24 seconds
Started Apr 30 02:19:54 PM PDT 24
Finished Apr 30 02:20:11 PM PDT 24
Peak memory 260356 kb
Host smart-6b093a75-6e1b-4bf3-9cd0-dcefb4286300
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692497999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.3692497999
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3037569110
Short name T972
Test name
Test status
Simulation time 18238600 ps
CPU time 13.56 seconds
Started Apr 30 02:19:53 PM PDT 24
Finished Apr 30 02:20:08 PM PDT 24
Peak memory 262516 kb
Host smart-abf42b4d-ab33-4b28-ae32-aeab82803201
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037569110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
3037569110
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3367314280
Short name T1048
Test name
Test status
Simulation time 81722300 ps
CPU time 16.57 seconds
Started Apr 30 02:19:55 PM PDT 24
Finished Apr 30 02:20:12 PM PDT 24
Peak memory 262004 kb
Host smart-b3841a6b-771e-454b-8959-ffe089899ff9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367314280 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.3367314280
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3247780827
Short name T994
Test name
Test status
Simulation time 25227500 ps
CPU time 13.32 seconds
Started Apr 30 02:19:53 PM PDT 24
Finished Apr 30 02:20:06 PM PDT 24
Peak memory 260404 kb
Host smart-96badd37-0720-4b85-8fe1-c5eab4c02b79
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247780827 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.3247780827
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3844345565
Short name T1029
Test name
Test status
Simulation time 12354300 ps
CPU time 15.73 seconds
Started Apr 30 02:19:58 PM PDT 24
Finished Apr 30 02:20:14 PM PDT 24
Peak memory 260380 kb
Host smart-28fb316f-4c84-4d79-a372-d6cfabd00835
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844345565 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.3844345565
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3684022981
Short name T232
Test name
Test status
Simulation time 217871600 ps
CPU time 16.19 seconds
Started Apr 30 02:19:46 PM PDT 24
Finished Apr 30 02:20:03 PM PDT 24
Peak memory 263916 kb
Host smart-a353bf99-10b1-4181-ad50-6cf8e806d9aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684022981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
3684022981
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.183512322
Short name T377
Test name
Test status
Simulation time 604648400 ps
CPU time 916.67 seconds
Started Apr 30 02:19:45 PM PDT 24
Finished Apr 30 02:35:02 PM PDT 24
Peak memory 263960 kb
Host smart-8baadaea-6838-430a-951e-c00aa526d8f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183512322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl
_tl_intg_err.183512322
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.382434575
Short name T1066
Test name
Test status
Simulation time 604300100 ps
CPU time 19.34 seconds
Started Apr 30 02:19:53 PM PDT 24
Finished Apr 30 02:20:12 PM PDT 24
Peak memory 270584 kb
Host smart-b4fe6983-e108-4c3b-886d-616f1390ab68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382434575 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.382434575
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.4246243956
Short name T330
Test name
Test status
Simulation time 24868200 ps
CPU time 14.79 seconds
Started Apr 30 02:19:53 PM PDT 24
Finished Apr 30 02:20:09 PM PDT 24
Peak memory 260308 kb
Host smart-1605e3ca-507e-4140-8699-0e9445c7ca90
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246243956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_csr_rw.4246243956
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1495703424
Short name T1071
Test name
Test status
Simulation time 14896100 ps
CPU time 13.55 seconds
Started Apr 30 02:19:54 PM PDT 24
Finished Apr 30 02:20:08 PM PDT 24
Peak memory 261724 kb
Host smart-1cb086a7-7581-40e5-ae0b-12bbb00c4a08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495703424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.
1495703424
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.119779323
Short name T1032
Test name
Test status
Simulation time 117777400 ps
CPU time 34.25 seconds
Started Apr 30 02:19:53 PM PDT 24
Finished Apr 30 02:20:28 PM PDT 24
Peak memory 261920 kb
Host smart-06c6d17d-7992-4bd2-9a04-2d9fe75ecf49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119779323 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.119779323
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.4216966939
Short name T993
Test name
Test status
Simulation time 35000300 ps
CPU time 13.3 seconds
Started Apr 30 02:19:58 PM PDT 24
Finished Apr 30 02:20:11 PM PDT 24
Peak memory 260396 kb
Host smart-acf5f63d-00e8-4375-ab48-038bbc94f1b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216966939 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.4216966939
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3295088145
Short name T973
Test name
Test status
Simulation time 49954400 ps
CPU time 15.77 seconds
Started Apr 30 02:19:56 PM PDT 24
Finished Apr 30 02:20:12 PM PDT 24
Peak memory 260280 kb
Host smart-4618c2ce-f9f2-480a-b6a2-e754dd046aca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295088145 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.3295088145
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1887836370
Short name T242
Test name
Test status
Simulation time 36228000 ps
CPU time 16 seconds
Started Apr 30 02:19:55 PM PDT 24
Finished Apr 30 02:20:12 PM PDT 24
Peak memory 263896 kb
Host smart-aa7cf273-a033-485d-bd42-19fb63e918f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887836370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
1887836370
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1729485770
Short name T250
Test name
Test status
Simulation time 724451700 ps
CPU time 461.92 seconds
Started Apr 30 02:19:56 PM PDT 24
Finished Apr 30 02:27:38 PM PDT 24
Peak memory 263892 kb
Host smart-393855b0-3709-4254-b0c9-fb7bb44aa9c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729485770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.1729485770
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1177600031
Short name T1055
Test name
Test status
Simulation time 41139600 ps
CPU time 18.57 seconds
Started Apr 30 02:19:53 PM PDT 24
Finished Apr 30 02:20:12 PM PDT 24
Peak memory 278272 kb
Host smart-11ceff8c-23ee-4a20-9d13-88751aafc87a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177600031 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.1177600031
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.309754872
Short name T1068
Test name
Test status
Simulation time 20926600 ps
CPU time 16.37 seconds
Started Apr 30 02:19:52 PM PDT 24
Finished Apr 30 02:20:09 PM PDT 24
Peak memory 260260 kb
Host smart-5c1afc4a-e886-4a79-87bb-1136c877e000
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309754872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.flash_ctrl_csr_rw.309754872
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.286608760
Short name T1085
Test name
Test status
Simulation time 1132700700 ps
CPU time 30.89 seconds
Started Apr 30 02:19:52 PM PDT 24
Finished Apr 30 02:20:24 PM PDT 24
Peak memory 260248 kb
Host smart-fef31bc6-8d58-44f0-9113-6810e1b585a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286608760 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.286608760
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1209879970
Short name T1008
Test name
Test status
Simulation time 20999800 ps
CPU time 13.57 seconds
Started Apr 30 02:19:53 PM PDT 24
Finished Apr 30 02:20:08 PM PDT 24
Peak memory 260224 kb
Host smart-1ac350af-62f5-45f1-adf4-e961a4f4569d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209879970 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.1209879970
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.197092178
Short name T962
Test name
Test status
Simulation time 31098000 ps
CPU time 15.81 seconds
Started Apr 30 02:19:52 PM PDT 24
Finished Apr 30 02:20:09 PM PDT 24
Peak memory 260380 kb
Host smart-8b080ddb-7481-4c57-80ac-e60cb6a9443f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197092178 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.197092178
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1275602443
Short name T249
Test name
Test status
Simulation time 1016374900 ps
CPU time 917.43 seconds
Started Apr 30 02:19:56 PM PDT 24
Finished Apr 30 02:35:14 PM PDT 24
Peak memory 261648 kb
Host smart-06fb53e4-9c39-4f00-808a-99ee24cb03ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275602443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr
l_tl_intg_err.1275602443
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2597640517
Short name T243
Test name
Test status
Simulation time 124920400 ps
CPU time 19.01 seconds
Started Apr 30 02:19:58 PM PDT 24
Finished Apr 30 02:20:17 PM PDT 24
Peak memory 272108 kb
Host smart-b6390bff-bbfa-4fc2-8fae-a471574aa065
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597640517 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.2597640517
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.974186040
Short name T1007
Test name
Test status
Simulation time 38430600 ps
CPU time 16.5 seconds
Started Apr 30 02:20:02 PM PDT 24
Finished Apr 30 02:20:19 PM PDT 24
Peak memory 260428 kb
Host smart-ce99b2a5-b12f-4264-990d-55d42905ba50
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974186040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.flash_ctrl_csr_rw.974186040
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2200137070
Short name T350
Test name
Test status
Simulation time 16584100 ps
CPU time 13.41 seconds
Started Apr 30 02:19:55 PM PDT 24
Finished Apr 30 02:20:08 PM PDT 24
Peak memory 262696 kb
Host smart-1c8a30e7-c94d-4ebd-886b-20f4f4e59a95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200137070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
2200137070
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3315251314
Short name T227
Test name
Test status
Simulation time 878538300 ps
CPU time 21.09 seconds
Started Apr 30 02:19:58 PM PDT 24
Finished Apr 30 02:20:20 PM PDT 24
Peak memory 261772 kb
Host smart-feed8852-3d62-42d7-aba7-49bc57820433
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315251314 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.3315251314
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2524321841
Short name T1016
Test name
Test status
Simulation time 76724000 ps
CPU time 15.7 seconds
Started Apr 30 02:19:55 PM PDT 24
Finished Apr 30 02:20:11 PM PDT 24
Peak memory 260392 kb
Host smart-d9c18a87-6b65-48e7-93b0-1aeda9a05f07
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524321841 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.2524321841
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1103614259
Short name T958
Test name
Test status
Simulation time 23071100 ps
CPU time 14.31 seconds
Started Apr 30 02:19:56 PM PDT 24
Finished Apr 30 02:20:10 PM PDT 24
Peak memory 260412 kb
Host smart-bf416503-78c0-47c0-b9ca-4f0840237094
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103614259 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.1103614259
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.581714742
Short name T237
Test name
Test status
Simulation time 194826500 ps
CPU time 18.86 seconds
Started Apr 30 02:19:57 PM PDT 24
Finished Apr 30 02:20:16 PM PDT 24
Peak memory 261156 kb
Host smart-9648dd44-dbc6-4b45-8fcc-ad16eae3b792
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581714742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.581714742
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3565086528
Short name T301
Test name
Test status
Simulation time 396927700 ps
CPU time 912.54 seconds
Started Apr 30 02:19:54 PM PDT 24
Finished Apr 30 02:35:07 PM PDT 24
Peak memory 263928 kb
Host smart-69a56d3a-d78c-4b45-8b7f-8cf7f599ec76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565086528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr
l_tl_intg_err.3565086528
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4018179616
Short name T992
Test name
Test status
Simulation time 53572900 ps
CPU time 15.7 seconds
Started Apr 30 02:19:59 PM PDT 24
Finished Apr 30 02:20:15 PM PDT 24
Peak memory 278008 kb
Host smart-6a9b55ad-132d-4273-aa35-2a3e8b4c90cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018179616 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.4018179616
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1344439833
Short name T1015
Test name
Test status
Simulation time 55998500 ps
CPU time 16.66 seconds
Started Apr 30 02:20:00 PM PDT 24
Finished Apr 30 02:20:17 PM PDT 24
Peak memory 260392 kb
Host smart-0e567dc3-4d0d-4ec8-8214-19dd48e29765
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344439833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.1344439833
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.772735760
Short name T1051
Test name
Test status
Simulation time 58157400 ps
CPU time 13.9 seconds
Started Apr 30 02:20:00 PM PDT 24
Finished Apr 30 02:20:14 PM PDT 24
Peak memory 262484 kb
Host smart-b5170d50-db6a-4f6e-b98f-17721d80d88e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772735760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.772735760
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3032574261
Short name T1020
Test name
Test status
Simulation time 79948600 ps
CPU time 15.86 seconds
Started Apr 30 02:20:01 PM PDT 24
Finished Apr 30 02:20:18 PM PDT 24
Peak memory 261856 kb
Host smart-39f7349e-9d91-4550-b67c-e7edd091d694
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032574261 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.3032574261
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.586984797
Short name T1022
Test name
Test status
Simulation time 44273000 ps
CPU time 15.75 seconds
Started Apr 30 02:20:01 PM PDT 24
Finished Apr 30 02:20:17 PM PDT 24
Peak memory 260340 kb
Host smart-55c04c7d-be80-4af9-a728-01e493846301
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586984797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.586984797
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2290413687
Short name T1072
Test name
Test status
Simulation time 42143900 ps
CPU time 15.61 seconds
Started Apr 30 02:20:01 PM PDT 24
Finished Apr 30 02:20:17 PM PDT 24
Peak memory 260336 kb
Host smart-a91fec26-f37f-4ed7-b51b-35f8489692d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290413687 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.2290413687
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1915357115
Short name T240
Test name
Test status
Simulation time 203465000 ps
CPU time 18.78 seconds
Started Apr 30 02:20:02 PM PDT 24
Finished Apr 30 02:20:21 PM PDT 24
Peak memory 263832 kb
Host smart-1e1c79a4-3c2d-49d3-9bba-9b1ec941c886
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915357115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
1915357115
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3493203128
Short name T375
Test name
Test status
Simulation time 829540500 ps
CPU time 457.58 seconds
Started Apr 30 02:20:00 PM PDT 24
Finished Apr 30 02:27:39 PM PDT 24
Peak memory 260344 kb
Host smart-47e13678-4a94-4e6f-ac23-8f324c262054
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493203128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr
l_tl_intg_err.3493203128
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.767480567
Short name T1033
Test name
Test status
Simulation time 54097900 ps
CPU time 19.55 seconds
Started Apr 30 02:20:00 PM PDT 24
Finished Apr 30 02:20:20 PM PDT 24
Peak memory 278232 kb
Host smart-29ffb652-0f5a-489c-a438-de940b08e4fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767480567 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.767480567
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.654249385
Short name T341
Test name
Test status
Simulation time 148580100 ps
CPU time 17.64 seconds
Started Apr 30 02:19:59 PM PDT 24
Finished Apr 30 02:20:17 PM PDT 24
Peak memory 260496 kb
Host smart-f61227c5-f9ff-4a79-bb92-4359dcd78dee
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654249385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.flash_ctrl_csr_rw.654249385
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.408357518
Short name T984
Test name
Test status
Simulation time 16847600 ps
CPU time 13.71 seconds
Started Apr 30 02:20:00 PM PDT 24
Finished Apr 30 02:20:15 PM PDT 24
Peak memory 262576 kb
Host smart-7e6eee76-5ddc-4b83-a540-48a9248e8eba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408357518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.408357518
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2861982512
Short name T1011
Test name
Test status
Simulation time 490837900 ps
CPU time 20.01 seconds
Started Apr 30 02:19:57 PM PDT 24
Finished Apr 30 02:20:17 PM PDT 24
Peak memory 262724 kb
Host smart-3e395371-6be2-4ba0-9cbb-5bd62c4d8069
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861982512 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.2861982512
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.562931775
Short name T1006
Test name
Test status
Simulation time 33526700 ps
CPU time 15.69 seconds
Started Apr 30 02:20:02 PM PDT 24
Finished Apr 30 02:20:18 PM PDT 24
Peak memory 260344 kb
Host smart-4cf6266b-e62b-47ef-a248-49ba60cfcb93
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562931775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.562931775
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.54495714
Short name T986
Test name
Test status
Simulation time 13625700 ps
CPU time 15.9 seconds
Started Apr 30 02:20:02 PM PDT 24
Finished Apr 30 02:20:18 PM PDT 24
Peak memory 260344 kb
Host smart-0e2a4eda-c26f-4896-a638-2c6cd301d024
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54495714 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.54495714
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.4057173421
Short name T239
Test name
Test status
Simulation time 33345600 ps
CPU time 16.45 seconds
Started Apr 30 02:20:00 PM PDT 24
Finished Apr 30 02:20:17 PM PDT 24
Peak memory 263884 kb
Host smart-3e3673b2-61e5-42af-b9a3-be5033914189
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057173421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.
4057173421
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1787512467
Short name T1054
Test name
Test status
Simulation time 551308000 ps
CPU time 19.54 seconds
Started Apr 30 02:20:01 PM PDT 24
Finished Apr 30 02:20:21 PM PDT 24
Peak memory 272004 kb
Host smart-d8edf9da-0915-45d9-96b2-f56b9fb94cfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787512467 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.1787512467
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.4254914262
Short name T1077
Test name
Test status
Simulation time 631039900 ps
CPU time 16.63 seconds
Started Apr 30 02:20:00 PM PDT 24
Finished Apr 30 02:20:17 PM PDT 24
Peak memory 260424 kb
Host smart-d6d95d25-7751-459f-9ce7-d6b486cb6840
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254914262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.4254914262
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2462404160
Short name T968
Test name
Test status
Simulation time 52315000 ps
CPU time 14.24 seconds
Started Apr 30 02:20:01 PM PDT 24
Finished Apr 30 02:20:15 PM PDT 24
Peak memory 262652 kb
Host smart-67f28a01-cf62-4488-979e-34c71971bd4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462404160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
2462404160
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.252156823
Short name T344
Test name
Test status
Simulation time 106375100 ps
CPU time 15.67 seconds
Started Apr 30 02:20:02 PM PDT 24
Finished Apr 30 02:20:18 PM PDT 24
Peak memory 263512 kb
Host smart-46d81524-b594-440a-8c47-fa66e8a532c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252156823 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.252156823
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3917889593
Short name T1005
Test name
Test status
Simulation time 12131400 ps
CPU time 16.05 seconds
Started Apr 30 02:20:04 PM PDT 24
Finished Apr 30 02:20:20 PM PDT 24
Peak memory 260404 kb
Host smart-90349717-8088-42cd-ac0f-87600871594c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917889593 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.3917889593
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1448352222
Short name T960
Test name
Test status
Simulation time 97866000 ps
CPU time 15.75 seconds
Started Apr 30 02:19:59 PM PDT 24
Finished Apr 30 02:20:15 PM PDT 24
Peak memory 260344 kb
Host smart-2148f097-ced4-45b6-816b-3d29cfcab54f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448352222 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.1448352222
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.500044388
Short name T251
Test name
Test status
Simulation time 55063800 ps
CPU time 19.28 seconds
Started Apr 30 02:19:59 PM PDT 24
Finished Apr 30 02:20:19 PM PDT 24
Peak memory 263884 kb
Host smart-facd4323-2b1c-4224-a7f1-7b36a4fd6d62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500044388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.500044388
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1414496983
Short name T69
Test name
Test status
Simulation time 115404800 ps
CPU time 19.33 seconds
Started Apr 30 02:20:08 PM PDT 24
Finished Apr 30 02:20:28 PM PDT 24
Peak memory 270384 kb
Host smart-6d84f14a-413c-450b-a77c-8c332cab681a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414496983 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.1414496983
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3031505611
Short name T974
Test name
Test status
Simulation time 35956700 ps
CPU time 16.61 seconds
Started Apr 30 02:20:04 PM PDT 24
Finished Apr 30 02:20:21 PM PDT 24
Peak memory 263956 kb
Host smart-4a44f1cf-6ec4-4de9-9aba-ef6a95691cbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031505611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.3031505611
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.77103298
Short name T987
Test name
Test status
Simulation time 28885400 ps
CPU time 13.64 seconds
Started Apr 30 02:20:04 PM PDT 24
Finished Apr 30 02:20:18 PM PDT 24
Peak memory 262456 kb
Host smart-aea799bc-3171-4f08-a775-69f671ae5f7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77103298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.77103298
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.4064946016
Short name T225
Test name
Test status
Simulation time 1941841400 ps
CPU time 35.91 seconds
Started Apr 30 02:20:09 PM PDT 24
Finished Apr 30 02:20:45 PM PDT 24
Peak memory 260412 kb
Host smart-8bc8212d-c21b-4253-a21b-907f7397cc42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064946016 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.4064946016
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3309962344
Short name T1040
Test name
Test status
Simulation time 13914800 ps
CPU time 16.07 seconds
Started Apr 30 02:20:00 PM PDT 24
Finished Apr 30 02:20:16 PM PDT 24
Peak memory 260332 kb
Host smart-274efc31-c313-4c14-9a7d-6924cd98dc4b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309962344 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.3309962344
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2345648421
Short name T1052
Test name
Test status
Simulation time 40814300 ps
CPU time 15.61 seconds
Started Apr 30 02:20:05 PM PDT 24
Finished Apr 30 02:20:21 PM PDT 24
Peak memory 260352 kb
Host smart-8fd18dd3-c022-4817-b6d0-1e45853e0da6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345648421 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.2345648421
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1135178596
Short name T989
Test name
Test status
Simulation time 666664000 ps
CPU time 38.46 seconds
Started Apr 30 02:19:32 PM PDT 24
Finished Apr 30 02:20:11 PM PDT 24
Peak memory 260292 kb
Host smart-9b325dfb-6e98-4f90-9123-6899c03464f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135178596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.1135178596
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.637539048
Short name T1042
Test name
Test status
Simulation time 4281986100 ps
CPU time 48.99 seconds
Started Apr 30 02:19:35 PM PDT 24
Finished Apr 30 02:20:24 PM PDT 24
Peak memory 260324 kb
Host smart-4245f43a-d10b-4f9e-abc1-9ecddcedbf81
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637539048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_csr_bit_bash.637539048
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3823682151
Short name T1010
Test name
Test status
Simulation time 157631300 ps
CPU time 45.69 seconds
Started Apr 30 02:19:32 PM PDT 24
Finished Apr 30 02:20:18 PM PDT 24
Peak memory 260384 kb
Host smart-3cb0f468-d5de-483c-8af1-f2aae1c8a78b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823682151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_hw_reset.3823682151
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3554819209
Short name T329
Test name
Test status
Simulation time 28477600 ps
CPU time 17.76 seconds
Started Apr 30 02:19:30 PM PDT 24
Finished Apr 30 02:19:48 PM PDT 24
Peak memory 260288 kb
Host smart-082e0ed6-db2a-4283-9c85-daa54bd19335
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554819209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.3554819209
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1913830724
Short name T970
Test name
Test status
Simulation time 29966200 ps
CPU time 13.71 seconds
Started Apr 30 02:19:26 PM PDT 24
Finished Apr 30 02:19:40 PM PDT 24
Peak memory 262728 kb
Host smart-a645a439-d5f6-4667-98e8-157deca487a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913830724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.1
913830724
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.2409030165
Short name T1080
Test name
Test status
Simulation time 23710700 ps
CPU time 13.21 seconds
Started Apr 30 02:19:27 PM PDT 24
Finished Apr 30 02:19:40 PM PDT 24
Peak memory 262500 kb
Host smart-044817c3-c6be-4b82-8f09-b35d8cc20e00
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409030165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me
m_walk.2409030165
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2789881332
Short name T229
Test name
Test status
Simulation time 82613300 ps
CPU time 15.38 seconds
Started Apr 30 02:19:31 PM PDT 24
Finished Apr 30 02:19:47 PM PDT 24
Peak memory 260368 kb
Host smart-f305fe30-95e2-4208-b6b2-23e95e1fcc7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789881332 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.2789881332
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.324538501
Short name T1000
Test name
Test status
Simulation time 11917100 ps
CPU time 13.33 seconds
Started Apr 30 02:19:26 PM PDT 24
Finished Apr 30 02:19:40 PM PDT 24
Peak memory 260348 kb
Host smart-20660973-53bb-4aa4-aa45-02f417df4976
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324538501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.324538501
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3301623832
Short name T954
Test name
Test status
Simulation time 22795500 ps
CPU time 15.68 seconds
Started Apr 30 02:19:25 PM PDT 24
Finished Apr 30 02:19:41 PM PDT 24
Peak memory 260220 kb
Host smart-878a11a6-143e-44dd-8f90-95ef4223705f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301623832 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.3301623832
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3252049438
Short name T246
Test name
Test status
Simulation time 50420800 ps
CPU time 18.7 seconds
Started Apr 30 02:19:25 PM PDT 24
Finished Apr 30 02:19:44 PM PDT 24
Peak memory 263912 kb
Host smart-09b80e5b-c66e-4ce0-af9c-a0cf27b15706
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252049438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.3
252049438
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.459635186
Short name T1027
Test name
Test status
Simulation time 57933400 ps
CPU time 13.98 seconds
Started Apr 30 02:20:05 PM PDT 24
Finished Apr 30 02:20:19 PM PDT 24
Peak memory 262352 kb
Host smart-f4e4af95-51ba-45de-ab81-dd8c8a919d11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459635186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.459635186
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3752897470
Short name T1073
Test name
Test status
Simulation time 18214600 ps
CPU time 13.67 seconds
Started Apr 30 02:20:03 PM PDT 24
Finished Apr 30 02:20:17 PM PDT 24
Peak memory 262492 kb
Host smart-925d1311-ae00-45bd-93ee-c92100c5b160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752897470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
3752897470
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.4008729447
Short name T236
Test name
Test status
Simulation time 60710200 ps
CPU time 13.46 seconds
Started Apr 30 02:20:03 PM PDT 24
Finished Apr 30 02:20:17 PM PDT 24
Peak memory 262556 kb
Host smart-65b431a8-1bf0-448c-b156-a461b43cd44e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008729447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
4008729447
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2156699422
Short name T975
Test name
Test status
Simulation time 18276200 ps
CPU time 13.58 seconds
Started Apr 30 02:20:05 PM PDT 24
Finished Apr 30 02:20:19 PM PDT 24
Peak memory 262316 kb
Host smart-4cc01361-ea03-4442-be8d-69c27329d7d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156699422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
2156699422
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1565271553
Short name T990
Test name
Test status
Simulation time 17427800 ps
CPU time 13.7 seconds
Started Apr 30 02:20:07 PM PDT 24
Finished Apr 30 02:20:21 PM PDT 24
Peak memory 262448 kb
Host smart-ad23f04f-2ede-4f6a-8e52-52e43b07745e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565271553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
1565271553
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2405611382
Short name T1089
Test name
Test status
Simulation time 148091600 ps
CPU time 13.42 seconds
Started Apr 30 02:20:06 PM PDT 24
Finished Apr 30 02:20:20 PM PDT 24
Peak memory 262440 kb
Host smart-8d7f1739-f075-4f89-96ff-76111a90fae4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405611382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
2405611382
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1958356803
Short name T1037
Test name
Test status
Simulation time 58190100 ps
CPU time 13.53 seconds
Started Apr 30 02:20:05 PM PDT 24
Finished Apr 30 02:20:19 PM PDT 24
Peak memory 262592 kb
Host smart-cacfaf3d-9c32-4494-b3fc-9d72c612d54b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958356803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.
1958356803
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.643705662
Short name T1074
Test name
Test status
Simulation time 15991200 ps
CPU time 13.67 seconds
Started Apr 30 02:20:04 PM PDT 24
Finished Apr 30 02:20:18 PM PDT 24
Peak memory 262508 kb
Host smart-bc6972c4-315b-4ba3-bfe1-f20aa1d9924b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643705662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.643705662
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2496960187
Short name T1050
Test name
Test status
Simulation time 27039500 ps
CPU time 13.52 seconds
Started Apr 30 02:20:06 PM PDT 24
Finished Apr 30 02:20:20 PM PDT 24
Peak memory 262272 kb
Host smart-df31e803-da33-426b-9e53-8bc00b7503e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496960187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.
2496960187
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1847116956
Short name T340
Test name
Test status
Simulation time 7511372700 ps
CPU time 72 seconds
Started Apr 30 02:19:36 PM PDT 24
Finished Apr 30 02:20:48 PM PDT 24
Peak memory 260320 kb
Host smart-a403c4ae-f047-40a5-95e4-954c415a300b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847116956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.1847116956
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2419540914
Short name T1025
Test name
Test status
Simulation time 3282706000 ps
CPU time 47.14 seconds
Started Apr 30 02:19:38 PM PDT 24
Finished Apr 30 02:20:26 PM PDT 24
Peak memory 260248 kb
Host smart-3ed07f4f-91d6-4fcc-9240-d1ef964d5d69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419540914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_bit_bash.2419540914
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3895056329
Short name T1056
Test name
Test status
Simulation time 26971800 ps
CPU time 47.81 seconds
Started Apr 30 02:19:34 PM PDT 24
Finished Apr 30 02:20:22 PM PDT 24
Peak memory 260256 kb
Host smart-076a58ab-1f67-40bf-8e7a-4ca88ea8a2eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895056329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.3895056329
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1482080288
Short name T1065
Test name
Test status
Simulation time 39982600 ps
CPU time 18.76 seconds
Started Apr 30 02:19:36 PM PDT 24
Finished Apr 30 02:19:56 PM PDT 24
Peak memory 272104 kb
Host smart-ae944852-00d5-4cba-b521-46895834eb4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482080288 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.1482080288
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2709232868
Short name T1003
Test name
Test status
Simulation time 915970600 ps
CPU time 18.42 seconds
Started Apr 30 02:19:36 PM PDT 24
Finished Apr 30 02:19:55 PM PDT 24
Peak memory 260344 kb
Host smart-ef940c2a-2ccb-4bb2-bd2a-147d64b7f7a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709232868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.2709232868
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2658073119
Short name T1067
Test name
Test status
Simulation time 36200800 ps
CPU time 13.54 seconds
Started Apr 30 02:19:35 PM PDT 24
Finished Apr 30 02:19:49 PM PDT 24
Peak memory 262760 kb
Host smart-57e934a8-be9a-4887-a3ac-ca0e3023fdc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658073119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.2
658073119
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3559279787
Short name T316
Test name
Test status
Simulation time 48136100 ps
CPU time 13.52 seconds
Started Apr 30 02:19:36 PM PDT 24
Finished Apr 30 02:19:50 PM PDT 24
Peak memory 263668 kb
Host smart-0f97d5e2-4f13-4c9b-b3ed-c69b83d94649
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559279787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.3559279787
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2259347816
Short name T985
Test name
Test status
Simulation time 16478800 ps
CPU time 13.39 seconds
Started Apr 30 02:19:33 PM PDT 24
Finished Apr 30 02:19:47 PM PDT 24
Peak memory 262616 kb
Host smart-acd67301-162b-4e09-bbd1-4a78b456c4f4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259347816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.2259347816
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2457428799
Short name T345
Test name
Test status
Simulation time 357127300 ps
CPU time 18.7 seconds
Started Apr 30 02:19:34 PM PDT 24
Finished Apr 30 02:19:53 PM PDT 24
Peak memory 260228 kb
Host smart-1610dd96-5548-45b3-9647-e69abb4c537d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457428799 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.2457428799
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2860087898
Short name T1017
Test name
Test status
Simulation time 99386500 ps
CPU time 13.33 seconds
Started Apr 30 02:19:32 PM PDT 24
Finished Apr 30 02:19:46 PM PDT 24
Peak memory 260376 kb
Host smart-00dc123a-7126-4430-9a4c-968396ebfa22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860087898 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.2860087898
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3279695783
Short name T1081
Test name
Test status
Simulation time 18757800 ps
CPU time 13.49 seconds
Started Apr 30 02:19:32 PM PDT 24
Finished Apr 30 02:19:46 PM PDT 24
Peak memory 260320 kb
Host smart-0041a149-2477-47ca-9e85-21ba07a593f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279695783 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.3279695783
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1298878690
Short name T68
Test name
Test status
Simulation time 82524200 ps
CPU time 17.72 seconds
Started Apr 30 02:19:33 PM PDT 24
Finished Apr 30 02:19:51 PM PDT 24
Peak memory 263904 kb
Host smart-7bbd6af0-a074-4144-8683-eac25aa5ca73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298878690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.1
298878690
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1567501079
Short name T380
Test name
Test status
Simulation time 1267579900 ps
CPU time 464.78 seconds
Started Apr 30 02:19:39 PM PDT 24
Finished Apr 30 02:27:24 PM PDT 24
Peak memory 263928 kb
Host smart-cbcc22cb-fc00-46f7-a67e-2e897527b19a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567501079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.1567501079
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3686138556
Short name T1059
Test name
Test status
Simulation time 15879300 ps
CPU time 13.42 seconds
Started Apr 30 02:20:04 PM PDT 24
Finished Apr 30 02:20:17 PM PDT 24
Peak memory 260888 kb
Host smart-fe5f42c7-3bbc-4449-bbfa-fd9da7b65e05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686138556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.
3686138556
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.560377109
Short name T997
Test name
Test status
Simulation time 29780400 ps
CPU time 13.78 seconds
Started Apr 30 02:20:05 PM PDT 24
Finished Apr 30 02:20:19 PM PDT 24
Peak memory 262528 kb
Host smart-83360a29-d169-4bad-bb35-5b8f8b39991b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560377109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.560377109
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2672988169
Short name T1088
Test name
Test status
Simulation time 74057300 ps
CPU time 13.62 seconds
Started Apr 30 02:20:06 PM PDT 24
Finished Apr 30 02:20:20 PM PDT 24
Peak memory 262436 kb
Host smart-29d45059-4b62-445a-856e-7b163321bba3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672988169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.
2672988169
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1895347308
Short name T1021
Test name
Test status
Simulation time 42918400 ps
CPU time 13.58 seconds
Started Apr 30 02:20:03 PM PDT 24
Finished Apr 30 02:20:17 PM PDT 24
Peak memory 262692 kb
Host smart-95d90e31-5fce-4aea-bc44-2cf74fb01d4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895347308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
1895347308
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.4062334115
Short name T1045
Test name
Test status
Simulation time 29321500 ps
CPU time 13.7 seconds
Started Apr 30 02:20:06 PM PDT 24
Finished Apr 30 02:20:21 PM PDT 24
Peak memory 262716 kb
Host smart-c2f1625d-11e1-4fae-8e83-9c39fbcf7b1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062334115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
4062334115
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3201228624
Short name T1049
Test name
Test status
Simulation time 59564700 ps
CPU time 13.43 seconds
Started Apr 30 02:20:05 PM PDT 24
Finished Apr 30 02:20:19 PM PDT 24
Peak memory 262436 kb
Host smart-052cf834-06fe-4e34-90fd-397597b7c1b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201228624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.
3201228624
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1441013236
Short name T1087
Test name
Test status
Simulation time 60493900 ps
CPU time 13.82 seconds
Started Apr 30 02:20:09 PM PDT 24
Finished Apr 30 02:20:23 PM PDT 24
Peak memory 262300 kb
Host smart-0400f9b7-a9e4-4254-940c-f0cb0f180dc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441013236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
1441013236
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1569833883
Short name T349
Test name
Test status
Simulation time 55662700 ps
CPU time 13.45 seconds
Started Apr 30 02:20:07 PM PDT 24
Finished Apr 30 02:20:21 PM PDT 24
Peak memory 262376 kb
Host smart-0fb2f191-1203-40f9-ae4e-145984bbf0b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569833883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.
1569833883
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1341463418
Short name T1069
Test name
Test status
Simulation time 14078300 ps
CPU time 13.93 seconds
Started Apr 30 02:20:06 PM PDT 24
Finished Apr 30 02:20:20 PM PDT 24
Peak memory 262744 kb
Host smart-7430983d-1a99-4e3b-8b9f-bfff0b200994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341463418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
1341463418
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2203481444
Short name T956
Test name
Test status
Simulation time 26657500 ps
CPU time 13.67 seconds
Started Apr 30 02:20:09 PM PDT 24
Finished Apr 30 02:20:23 PM PDT 24
Peak memory 260808 kb
Host smart-cd82ea1c-2dcd-4e6e-9449-10a3fea561e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203481444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.
2203481444
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1734565348
Short name T1043
Test name
Test status
Simulation time 4790321600 ps
CPU time 67.12 seconds
Started Apr 30 02:19:33 PM PDT 24
Finished Apr 30 02:20:40 PM PDT 24
Peak memory 260384 kb
Host smart-c5d760a0-d1c8-4f41-b7ca-44684be270eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734565348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.1734565348
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.4255323907
Short name T339
Test name
Test status
Simulation time 13103313700 ps
CPU time 94.25 seconds
Started Apr 30 02:19:32 PM PDT 24
Finished Apr 30 02:21:06 PM PDT 24
Peak memory 261940 kb
Host smart-7ea8cb33-1916-4b43-80f2-498bd1a16c68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255323907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.4255323907
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.106229895
Short name T978
Test name
Test status
Simulation time 241387700 ps
CPU time 46.28 seconds
Started Apr 30 02:19:34 PM PDT 24
Finished Apr 30 02:20:20 PM PDT 24
Peak memory 260320 kb
Host smart-0c44cf38-3848-4acc-a708-d8bc70fed10f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106229895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_hw_reset.106229895
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2546266496
Short name T982
Test name
Test status
Simulation time 26320500 ps
CPU time 17.16 seconds
Started Apr 30 02:19:35 PM PDT 24
Finished Apr 30 02:19:53 PM PDT 24
Peak memory 272068 kb
Host smart-a90eab44-2737-4f8a-93be-106a53aa1d6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546266496 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.2546266496
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3739587734
Short name T980
Test name
Test status
Simulation time 74451500 ps
CPU time 13.9 seconds
Started Apr 30 02:19:36 PM PDT 24
Finished Apr 30 02:19:50 PM PDT 24
Peak memory 260388 kb
Host smart-b3445855-df1c-498e-a78a-48cfe26ff759
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739587734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_csr_rw.3739587734
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3696629579
Short name T1019
Test name
Test status
Simulation time 24657100 ps
CPU time 13.5 seconds
Started Apr 30 02:19:34 PM PDT 24
Finished Apr 30 02:19:48 PM PDT 24
Peak memory 260776 kb
Host smart-99a89d10-b2a4-4b3b-9270-a189e3ae278b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696629579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.3
696629579
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3852220795
Short name T319
Test name
Test status
Simulation time 46621800 ps
CPU time 13.88 seconds
Started Apr 30 02:19:32 PM PDT 24
Finished Apr 30 02:19:47 PM PDT 24
Peak memory 263816 kb
Host smart-f36bdcbf-2b1c-4042-8307-bc694b8289a0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852220795 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_mem_partial_access.3852220795
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1813675826
Short name T1041
Test name
Test status
Simulation time 18126500 ps
CPU time 13.54 seconds
Started Apr 30 02:19:33 PM PDT 24
Finished Apr 30 02:19:47 PM PDT 24
Peak memory 262468 kb
Host smart-c917292a-0399-4efe-9715-a6805329776b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813675826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me
m_walk.1813675826
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.990555789
Short name T1078
Test name
Test status
Simulation time 39638000 ps
CPU time 14.89 seconds
Started Apr 30 02:19:33 PM PDT 24
Finished Apr 30 02:19:48 PM PDT 24
Peak memory 261776 kb
Host smart-853d831a-6b50-4e53-ad56-7d4476f22362
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990555789 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.990555789
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.108192446
Short name T988
Test name
Test status
Simulation time 38921700 ps
CPU time 13.3 seconds
Started Apr 30 02:19:33 PM PDT 24
Finished Apr 30 02:19:47 PM PDT 24
Peak memory 260424 kb
Host smart-dac6c83f-026f-4d24-b6ad-69b8c8da1a6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108192446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.108192446
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1220500985
Short name T957
Test name
Test status
Simulation time 26395100 ps
CPU time 15.91 seconds
Started Apr 30 02:19:32 PM PDT 24
Finished Apr 30 02:19:49 PM PDT 24
Peak memory 260332 kb
Host smart-0f054af9-bb51-49b6-a9bc-172e8c432c61
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220500985 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.1220500985
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1848471319
Short name T1060
Test name
Test status
Simulation time 179306000 ps
CPU time 478.08 seconds
Started Apr 30 02:19:33 PM PDT 24
Finished Apr 30 02:27:32 PM PDT 24
Peak memory 261528 kb
Host smart-4816ab2d-4659-4b4f-94a7-95e8bd3b848a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848471319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.1848471319
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.3507266684
Short name T1063
Test name
Test status
Simulation time 16072000 ps
CPU time 13.69 seconds
Started Apr 30 02:20:15 PM PDT 24
Finished Apr 30 02:20:29 PM PDT 24
Peak memory 262748 kb
Host smart-d41025e4-63f5-4fcf-b8d8-2b7eccaa7e17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507266684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
3507266684
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.557694402
Short name T977
Test name
Test status
Simulation time 93600400 ps
CPU time 13.93 seconds
Started Apr 30 02:20:12 PM PDT 24
Finished Apr 30 02:20:27 PM PDT 24
Peak memory 262452 kb
Host smart-183820db-9725-4b1b-b5a1-6f5744e6b692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557694402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.557694402
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.4085697555
Short name T1031
Test name
Test status
Simulation time 50607300 ps
CPU time 13.79 seconds
Started Apr 30 02:20:12 PM PDT 24
Finished Apr 30 02:20:26 PM PDT 24
Peak memory 262760 kb
Host smart-675f5485-2310-4121-8971-82a5621521c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085697555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.
4085697555
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1131309964
Short name T1014
Test name
Test status
Simulation time 14390600 ps
CPU time 13.62 seconds
Started Apr 30 02:20:11 PM PDT 24
Finished Apr 30 02:20:25 PM PDT 24
Peak memory 262452 kb
Host smart-f7cf172b-1791-4f7b-a35c-b23f1fb6733c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131309964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.
1131309964
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3617887642
Short name T1030
Test name
Test status
Simulation time 15944300 ps
CPU time 13.72 seconds
Started Apr 30 02:20:15 PM PDT 24
Finished Apr 30 02:20:29 PM PDT 24
Peak memory 262412 kb
Host smart-b436c600-7bb7-4bfa-9e6e-39a24effce67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617887642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
3617887642
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1408788547
Short name T971
Test name
Test status
Simulation time 22025400 ps
CPU time 14.09 seconds
Started Apr 30 02:20:12 PM PDT 24
Finished Apr 30 02:20:27 PM PDT 24
Peak memory 262516 kb
Host smart-a7545efb-8dff-4e81-9491-b17a390ec7ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408788547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
1408788547
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.419827834
Short name T991
Test name
Test status
Simulation time 68775900 ps
CPU time 13.68 seconds
Started Apr 30 02:20:13 PM PDT 24
Finished Apr 30 02:20:27 PM PDT 24
Peak memory 262756 kb
Host smart-dcbf252c-170a-4497-b3c0-f0174f0dcbdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419827834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.419827834
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.520323707
Short name T235
Test name
Test status
Simulation time 25942900 ps
CPU time 13.56 seconds
Started Apr 30 02:20:10 PM PDT 24
Finished Apr 30 02:20:24 PM PDT 24
Peak memory 262748 kb
Host smart-1b3ef483-f21f-460b-887f-79ddcfd22c31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520323707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.520323707
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1216253966
Short name T352
Test name
Test status
Simulation time 49464900 ps
CPU time 13.62 seconds
Started Apr 30 02:20:10 PM PDT 24
Finished Apr 30 02:20:23 PM PDT 24
Peak memory 262436 kb
Host smart-2b385068-2d20-48ff-9cef-d75b3c777dbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216253966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
1216253966
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2947664718
Short name T999
Test name
Test status
Simulation time 41155200 ps
CPU time 13.64 seconds
Started Apr 30 02:20:10 PM PDT 24
Finished Apr 30 02:20:24 PM PDT 24
Peak memory 262580 kb
Host smart-3e2830db-4bad-4793-a67a-e86b0910c900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947664718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
2947664718
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3961142319
Short name T1058
Test name
Test status
Simulation time 61981900 ps
CPU time 18.08 seconds
Started Apr 30 02:19:38 PM PDT 24
Finished Apr 30 02:19:57 PM PDT 24
Peak memory 271980 kb
Host smart-a286cbc3-b9fe-4945-a258-68e96c9803ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961142319 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.3961142319
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1217826209
Short name T1012
Test name
Test status
Simulation time 20739800 ps
CPU time 16.46 seconds
Started Apr 30 02:19:38 PM PDT 24
Finished Apr 30 02:19:55 PM PDT 24
Peak memory 260444 kb
Host smart-599ff515-118a-4a48-817f-ffc24c7afdd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217826209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.1217826209
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.4086974703
Short name T1082
Test name
Test status
Simulation time 37361500 ps
CPU time 13.75 seconds
Started Apr 30 02:19:38 PM PDT 24
Finished Apr 30 02:19:53 PM PDT 24
Peak memory 262520 kb
Host smart-24ff2b00-a8b4-4203-86d4-fae8d9653fab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086974703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.4
086974703
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.684958805
Short name T342
Test name
Test status
Simulation time 111825400 ps
CPU time 18.36 seconds
Started Apr 30 02:19:39 PM PDT 24
Finished Apr 30 02:19:58 PM PDT 24
Peak memory 261980 kb
Host smart-26f33f74-e2f1-4073-a40a-d298ff1e30db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684958805 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.684958805
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.4130199870
Short name T966
Test name
Test status
Simulation time 63151600 ps
CPU time 15.79 seconds
Started Apr 30 02:19:38 PM PDT 24
Finished Apr 30 02:19:54 PM PDT 24
Peak memory 260384 kb
Host smart-7bd9fd18-3ddd-4ddd-a20d-e14073a02de1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130199870 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.4130199870
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1035399668
Short name T1004
Test name
Test status
Simulation time 46201600 ps
CPU time 13.55 seconds
Started Apr 30 02:19:39 PM PDT 24
Finished Apr 30 02:19:53 PM PDT 24
Peak memory 260404 kb
Host smart-0a89a5c9-085d-4eff-9600-b2af6a67a2e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035399668 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.1035399668
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2269977209
Short name T230
Test name
Test status
Simulation time 32951200 ps
CPU time 16.08 seconds
Started Apr 30 02:19:34 PM PDT 24
Finished Apr 30 02:19:50 PM PDT 24
Peak memory 263820 kb
Host smart-f3d9b3f1-0b6a-453f-9a4d-b2667585d932
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269977209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.2
269977209
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3545064443
Short name T1023
Test name
Test status
Simulation time 48041700 ps
CPU time 14.92 seconds
Started Apr 30 02:19:45 PM PDT 24
Finished Apr 30 02:20:00 PM PDT 24
Peak memory 277176 kb
Host smart-dcdd7037-d8c2-4b4e-91c3-f5415969e159
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545064443 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.3545064443
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2044937937
Short name T1046
Test name
Test status
Simulation time 26080900 ps
CPU time 16.95 seconds
Started Apr 30 02:19:45 PM PDT 24
Finished Apr 30 02:20:02 PM PDT 24
Peak memory 260344 kb
Host smart-af69859c-3e63-47ec-80fa-92c0504a9bfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044937937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.2044937937
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3945081344
Short name T1064
Test name
Test status
Simulation time 24976200 ps
CPU time 13.65 seconds
Started Apr 30 02:19:38 PM PDT 24
Finished Apr 30 02:19:53 PM PDT 24
Peak memory 262396 kb
Host smart-7c05e1e2-35e9-4210-bb71-9ac4f510a743
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945081344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.3
945081344
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2737616324
Short name T332
Test name
Test status
Simulation time 78811000 ps
CPU time 17.99 seconds
Started Apr 30 02:19:43 PM PDT 24
Finished Apr 30 02:20:02 PM PDT 24
Peak memory 260336 kb
Host smart-5f26c7c6-a93f-49bf-83fa-2d0ab29346d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737616324 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.2737616324
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1881971128
Short name T1002
Test name
Test status
Simulation time 116850200 ps
CPU time 13.52 seconds
Started Apr 30 02:19:43 PM PDT 24
Finished Apr 30 02:19:58 PM PDT 24
Peak memory 260332 kb
Host smart-7ae08af5-5648-4eed-aed4-35cc1a62c7b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881971128 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.1881971128
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3972012279
Short name T1013
Test name
Test status
Simulation time 18633600 ps
CPU time 16.02 seconds
Started Apr 30 02:19:37 PM PDT 24
Finished Apr 30 02:19:54 PM PDT 24
Peak memory 260396 kb
Host smart-05d45026-0619-4dae-a6bc-2e517c434ebd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972012279 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.3972012279
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.528898311
Short name T71
Test name
Test status
Simulation time 26140500 ps
CPU time 15.02 seconds
Started Apr 30 02:19:39 PM PDT 24
Finished Apr 30 02:19:54 PM PDT 24
Peak memory 272108 kb
Host smart-6d5f27ab-d6fa-437e-82c1-189b837fe72a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528898311 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.528898311
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.4036516819
Short name T1036
Test name
Test status
Simulation time 29166700 ps
CPU time 17.1 seconds
Started Apr 30 02:19:40 PM PDT 24
Finished Apr 30 02:19:57 PM PDT 24
Peak memory 260412 kb
Host smart-6ca92b8c-c2df-4cd1-b48c-133b0f9a336b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036516819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_csr_rw.4036516819
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3390193202
Short name T967
Test name
Test status
Simulation time 16801300 ps
CPU time 13.51 seconds
Started Apr 30 02:19:39 PM PDT 24
Finished Apr 30 02:19:53 PM PDT 24
Peak memory 262328 kb
Host smart-04229447-46f1-4cd2-b49b-8ab2c89bc6a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390193202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.3
390193202
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.510193884
Short name T1086
Test name
Test status
Simulation time 656403000 ps
CPU time 21.17 seconds
Started Apr 30 02:19:40 PM PDT 24
Finished Apr 30 02:20:02 PM PDT 24
Peak memory 260412 kb
Host smart-c1f9427f-c4fc-40de-91e7-084224752278
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510193884 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.510193884
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1394804762
Short name T998
Test name
Test status
Simulation time 19224400 ps
CPU time 16.14 seconds
Started Apr 30 02:19:43 PM PDT 24
Finished Apr 30 02:20:00 PM PDT 24
Peak memory 260340 kb
Host smart-f012b2b4-e61e-4e55-841c-9d4c9a2533a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394804762 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.1394804762
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3738551826
Short name T1026
Test name
Test status
Simulation time 14377300 ps
CPU time 16.02 seconds
Started Apr 30 02:19:38 PM PDT 24
Finished Apr 30 02:19:55 PM PDT 24
Peak memory 260440 kb
Host smart-e81826cd-9aae-4b64-800f-e6723ef54f06
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738551826 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.3738551826
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2543577445
Short name T233
Test name
Test status
Simulation time 52148500 ps
CPU time 18.13 seconds
Started Apr 30 02:19:43 PM PDT 24
Finished Apr 30 02:20:02 PM PDT 24
Peak memory 263828 kb
Host smart-717d1b21-6678-4944-ba1e-ca5eed13261a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543577445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.2
543577445
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2102934740
Short name T378
Test name
Test status
Simulation time 699132400 ps
CPU time 916.67 seconds
Started Apr 30 02:19:39 PM PDT 24
Finished Apr 30 02:34:56 PM PDT 24
Peak memory 261476 kb
Host smart-845a0574-0822-418f-afbe-dac9cb7857b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102934740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.2102934740
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.140595446
Short name T244
Test name
Test status
Simulation time 441445200 ps
CPU time 15.28 seconds
Started Apr 30 02:19:45 PM PDT 24
Finished Apr 30 02:20:01 PM PDT 24
Peak memory 263824 kb
Host smart-2bac52ab-2aac-429f-929e-665ac1d40729
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140595446 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.140595446
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.75917942
Short name T1075
Test name
Test status
Simulation time 35155300 ps
CPU time 16.94 seconds
Started Apr 30 02:19:45 PM PDT 24
Finished Apr 30 02:20:03 PM PDT 24
Peak memory 260288 kb
Host smart-1f2602d1-53ec-48dd-89e3-d7150810a83b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75917942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 8.flash_ctrl_csr_rw.75917942
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3299405102
Short name T1028
Test name
Test status
Simulation time 25026300 ps
CPU time 13.66 seconds
Started Apr 30 02:19:45 PM PDT 24
Finished Apr 30 02:20:00 PM PDT 24
Peak memory 262768 kb
Host smart-38d384a6-9b96-451a-bad7-bf14b3371b80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299405102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.3
299405102
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2068362264
Short name T1084
Test name
Test status
Simulation time 239751800 ps
CPU time 33.59 seconds
Started Apr 30 02:19:45 PM PDT 24
Finished Apr 30 02:20:19 PM PDT 24
Peak memory 260420 kb
Host smart-fc529a71-8d7b-4c77-8657-3fa3d799e8ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068362264 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.2068362264
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.843418070
Short name T953
Test name
Test status
Simulation time 15373900 ps
CPU time 15.57 seconds
Started Apr 30 02:19:38 PM PDT 24
Finished Apr 30 02:19:55 PM PDT 24
Peak memory 260388 kb
Host smart-9643ba0d-894e-4e9f-9f60-047fe63247fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843418070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.843418070
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1690291682
Short name T1001
Test name
Test status
Simulation time 22892200 ps
CPU time 13.68 seconds
Started Apr 30 02:19:41 PM PDT 24
Finished Apr 30 02:19:55 PM PDT 24
Peak memory 260440 kb
Host smart-9ae90317-3cbd-4a26-843a-046d96dbcf2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690291682 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.1690291682
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2145064812
Short name T210
Test name
Test status
Simulation time 65548800 ps
CPU time 18.97 seconds
Started Apr 30 02:19:39 PM PDT 24
Finished Apr 30 02:19:59 PM PDT 24
Peak memory 263900 kb
Host smart-8fae19bb-9667-4538-98aa-22389b538871
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145064812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.2
145064812
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3305403750
Short name T313
Test name
Test status
Simulation time 117788800 ps
CPU time 16.88 seconds
Started Apr 30 02:19:45 PM PDT 24
Finished Apr 30 02:20:02 PM PDT 24
Peak memory 272080 kb
Host smart-be775aba-533b-4c74-9aac-11a1b679a2a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305403750 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.3305403750
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2680254347
Short name T1035
Test name
Test status
Simulation time 269695600 ps
CPU time 17.41 seconds
Started Apr 30 02:19:46 PM PDT 24
Finished Apr 30 02:20:04 PM PDT 24
Peak memory 260328 kb
Host smart-32188682-fd92-47a2-83b8-81c263210635
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680254347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_csr_rw.2680254347
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.535829040
Short name T351
Test name
Test status
Simulation time 123115200 ps
CPU time 13.74 seconds
Started Apr 30 02:19:46 PM PDT 24
Finished Apr 30 02:20:01 PM PDT 24
Peak memory 262404 kb
Host smart-76c599ed-a377-4089-aba7-d1c0f711969e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535829040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.535829040
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3602603459
Short name T963
Test name
Test status
Simulation time 719636300 ps
CPU time 21.89 seconds
Started Apr 30 02:19:47 PM PDT 24
Finished Apr 30 02:20:09 PM PDT 24
Peak memory 262144 kb
Host smart-08b14a19-26b0-4a79-a62e-83a6721e58de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602603459 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.3602603459
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.4104071347
Short name T1009
Test name
Test status
Simulation time 25129700 ps
CPU time 13.3 seconds
Started Apr 30 02:19:46 PM PDT 24
Finished Apr 30 02:20:00 PM PDT 24
Peak memory 260312 kb
Host smart-cb0857b7-0d58-4414-a91f-21369f9434d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104071347 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.4104071347
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.4225766521
Short name T952
Test name
Test status
Simulation time 14952000 ps
CPU time 15.8 seconds
Started Apr 30 02:19:48 PM PDT 24
Finished Apr 30 02:20:04 PM PDT 24
Peak memory 260400 kb
Host smart-64666033-4d8f-4e32-8eda-49dfb21ef42b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225766521 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.4225766521
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3022736055
Short name T223
Test name
Test status
Simulation time 1403066700 ps
CPU time 470.03 seconds
Started Apr 30 02:19:46 PM PDT 24
Finished Apr 30 02:27:37 PM PDT 24
Peak memory 263916 kb
Host smart-5afc027c-8c76-4eb8-ab3d-511bb6d50388
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022736055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.3022736055
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.4277816212
Short name T676
Test name
Test status
Simulation time 471539400 ps
CPU time 14.73 seconds
Started Apr 30 02:26:21 PM PDT 24
Finished Apr 30 02:26:36 PM PDT 24
Peak memory 264580 kb
Host smart-7195e4f6-ff8f-465f-b1ec-615732d928a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277816212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.4
277816212
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.2157380936
Short name T547
Test name
Test status
Simulation time 14472200 ps
CPU time 15.98 seconds
Started Apr 30 02:26:13 PM PDT 24
Finished Apr 30 02:26:30 PM PDT 24
Peak memory 274764 kb
Host smart-4dc47895-25a4-49c1-b843-49ed3fc125eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157380936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.2157380936
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.2379540398
Short name T124
Test name
Test status
Simulation time 20593800 ps
CPU time 23.15 seconds
Started Apr 30 02:26:14 PM PDT 24
Finished Apr 30 02:26:37 PM PDT 24
Peak memory 272920 kb
Host smart-d364ced8-69fd-461c-81c7-afc83b7033a5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379540398 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.2379540398
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.233877718
Short name T165
Test name
Test status
Simulation time 2132705800 ps
CPU time 439.1 seconds
Started Apr 30 02:25:53 PM PDT 24
Finished Apr 30 02:33:13 PM PDT 24
Peak memory 260412 kb
Host smart-67092120-e76a-49d6-be44-ed8d6571d2cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=233877718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.233877718
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.2093065165
Short name T807
Test name
Test status
Simulation time 119191000 ps
CPU time 23.6 seconds
Started Apr 30 02:25:51 PM PDT 24
Finished Apr 30 02:26:15 PM PDT 24
Peak memory 264488 kb
Host smart-af8c01ca-88c4-42fc-8a47-f3df534a5f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093065165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.2093065165
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.2671134442
Short name T26
Test name
Test status
Simulation time 78285960100 ps
CPU time 2671.85 seconds
Started Apr 30 02:26:00 PM PDT 24
Finished Apr 30 03:10:33 PM PDT 24
Peak memory 261676 kb
Host smart-0c913718-ac69-4eed-9e5c-6d213085beb7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671134442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.2671134442
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.2197364771
Short name T126
Test name
Test status
Simulation time 10012557000 ps
CPU time 142.09 seconds
Started Apr 30 02:26:19 PM PDT 24
Finished Apr 30 02:28:42 PM PDT 24
Peak memory 384792 kb
Host smart-98a777a8-f7cd-46bd-af29-8ed377517c35
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197364771 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.2197364771
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.3481284233
Short name T608
Test name
Test status
Simulation time 160193016000 ps
CPU time 921.25 seconds
Started Apr 30 02:25:53 PM PDT 24
Finished Apr 30 02:41:15 PM PDT 24
Peak memory 263392 kb
Host smart-d26fcfd0-6311-49ee-8ad5-d7c205c967fa
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481284233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.flash_ctrl_hw_rma_reset.3481284233
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.602877468
Short name T481
Test name
Test status
Simulation time 6433405900 ps
CPU time 127.26 seconds
Started Apr 30 02:25:53 PM PDT 24
Finished Apr 30 02:28:01 PM PDT 24
Peak memory 261976 kb
Host smart-6b62c7ce-c8cd-4c59-8ee6-37bec31189f5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602877468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw
_sec_otp.602877468
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.4230755482
Short name T305
Test name
Test status
Simulation time 2451859400 ps
CPU time 174.24 seconds
Started Apr 30 02:26:05 PM PDT 24
Finished Apr 30 02:29:00 PM PDT 24
Peak memory 293456 kb
Host smart-b0ce5df3-4423-41fe-a6e0-4b6f5aa27dd4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230755482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_intr_rd.4230755482
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.4168101724
Short name T558
Test name
Test status
Simulation time 9518176700 ps
CPU time 209.49 seconds
Started Apr 30 02:26:06 PM PDT 24
Finished Apr 30 02:29:36 PM PDT 24
Peak memory 290212 kb
Host smart-25e38cb8-c387-47d4-b8e8-314df04d3763
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168101724 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.4168101724
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.3229070141
Short name T145
Test name
Test status
Simulation time 11605820600 ps
CPU time 71.04 seconds
Started Apr 30 02:25:59 PM PDT 24
Finished Apr 30 02:27:11 PM PDT 24
Peak memory 260016 kb
Host smart-f01c6f02-6936-4780-937f-8a3c95f3162b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229070141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.3229070141
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.2506806794
Short name T762
Test name
Test status
Simulation time 30089802500 ps
CPU time 357.48 seconds
Started Apr 30 02:25:51 PM PDT 24
Finished Apr 30 02:31:50 PM PDT 24
Peak memory 273004 kb
Host smart-4998ee32-2ca9-4948-a57b-312a885ff661
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506806794 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_mp_regions.2506806794
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.362741161
Short name T287
Test name
Test status
Simulation time 61896100 ps
CPU time 130.16 seconds
Started Apr 30 02:25:56 PM PDT 24
Finished Apr 30 02:28:07 PM PDT 24
Peak memory 259480 kb
Host smart-5f74b6b8-1ac1-4e97-86dd-b022242cceb9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362741161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_otp
_reset.362741161
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.4012796954
Short name T128
Test name
Test status
Simulation time 14989500 ps
CPU time 14.07 seconds
Started Apr 30 02:26:18 PM PDT 24
Finished Apr 30 02:26:33 PM PDT 24
Peak memory 276524 kb
Host smart-a1bf168a-c2f8-41e8-965c-2dd310d01803
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=4012796954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.4012796954
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.2160854320
Short name T170
Test name
Test status
Simulation time 176030800 ps
CPU time 406.2 seconds
Started Apr 30 02:25:52 PM PDT 24
Finished Apr 30 02:32:39 PM PDT 24
Peak memory 261720 kb
Host smart-5b39ab01-da6d-4f0b-87fc-3b8a441a5aba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2160854320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.2160854320
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.3899096180
Short name T867
Test name
Test status
Simulation time 66416300 ps
CPU time 106.79 seconds
Started Apr 30 02:25:52 PM PDT 24
Finished Apr 30 02:27:40 PM PDT 24
Peak memory 269660 kb
Host smart-d6949450-7c5d-49ba-9705-48007670cd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899096180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.3899096180
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.571513938
Short name T812
Test name
Test status
Simulation time 104651500 ps
CPU time 97.69 seconds
Started Apr 30 02:25:55 PM PDT 24
Finished Apr 30 02:27:34 PM PDT 24
Peak memory 264248 kb
Host smart-88678781-8ba7-4d06-b7e9-53b086ca2f66
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=571513938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.571513938
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.3677520639
Short name T603
Test name
Test status
Simulation time 74993200 ps
CPU time 47.22 seconds
Started Apr 30 02:26:21 PM PDT 24
Finished Apr 30 02:27:09 PM PDT 24
Peak memory 273432 kb
Host smart-16f9ed25-200d-4f21-9a57-61b44aba2fd6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677520639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.3677520639
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.1276104567
Short name T146
Test name
Test status
Simulation time 115984900 ps
CPU time 39.08 seconds
Started Apr 30 02:26:13 PM PDT 24
Finished Apr 30 02:26:53 PM PDT 24
Peak memory 274076 kb
Host smart-40f90210-718a-4796-8db5-29284575518f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276104567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.1276104567
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.1972271948
Short name T467
Test name
Test status
Simulation time 180640000 ps
CPU time 14.32 seconds
Started Apr 30 02:25:58 PM PDT 24
Finished Apr 30 02:26:14 PM PDT 24
Peak memory 257536 kb
Host smart-ec6fd23c-1e80-49ed-bc60-dfaeb3d61968
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1972271948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.1972271948
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.1737194299
Short name T613
Test name
Test status
Simulation time 18891300 ps
CPU time 21.47 seconds
Started Apr 30 02:25:58 PM PDT 24
Finished Apr 30 02:26:21 PM PDT 24
Peak memory 264792 kb
Host smart-700f3424-ca5d-4ae0-ae78-f9f634a93c32
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737194299 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.1737194299
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.3695066565
Short name T803
Test name
Test status
Simulation time 23147100 ps
CPU time 22.75 seconds
Started Apr 30 02:25:59 PM PDT 24
Finished Apr 30 02:26:23 PM PDT 24
Peak memory 264664 kb
Host smart-40d6c9f7-6a81-40b8-b7ca-f27c066cc4a2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695066565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_read_word_sweep_serr.3695066565
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.1460678582
Short name T111
Test name
Test status
Simulation time 73591619700 ps
CPU time 1207.59 seconds
Started Apr 30 02:26:17 PM PDT 24
Finished Apr 30 02:46:26 PM PDT 24
Peak memory 455996 kb
Host smart-f03fb7e7-30e3-4bb5-8cd2-666ef07612fb
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460678582 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.1460678582
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.3644066869
Short name T663
Test name
Test status
Simulation time 1391325200 ps
CPU time 143.47 seconds
Started Apr 30 02:26:01 PM PDT 24
Finished Apr 30 02:28:25 PM PDT 24
Peak memory 281084 kb
Host smart-0563a674-188e-475c-8fe8-835039006afd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644066869 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_ro.3644066869
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.3980248320
Short name T188
Test name
Test status
Simulation time 3619890300 ps
CPU time 168.07 seconds
Started Apr 30 02:26:01 PM PDT 24
Finished Apr 30 02:28:50 PM PDT 24
Peak memory 282532 kb
Host smart-6bdc6333-c232-483d-9eb2-7756be6966db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3980248320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.3980248320
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.1967735676
Short name T714
Test name
Test status
Simulation time 788483900 ps
CPU time 171.33 seconds
Started Apr 30 02:26:00 PM PDT 24
Finished Apr 30 02:28:53 PM PDT 24
Peak memory 281120 kb
Host smart-0587d959-bbc1-4157-b57e-1d8f9fe8a9d4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967735676 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.1967735676
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.228163318
Short name T408
Test name
Test status
Simulation time 2242131400 ps
CPU time 69.99 seconds
Started Apr 30 02:26:16 PM PDT 24
Finished Apr 30 02:27:27 PM PDT 24
Peak memory 262884 kb
Host smart-f9a73ee4-4108-4027-bf6a-267a537265d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228163318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.228163318
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.2594963953
Short name T5
Test name
Test status
Simulation time 33215300 ps
CPU time 169.54 seconds
Started Apr 30 02:25:52 PM PDT 24
Finished Apr 30 02:28:43 PM PDT 24
Peak memory 275960 kb
Host smart-0857e85a-1d90-4b1c-bd78-8def0afb4e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594963953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.2594963953
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.267695079
Short name T278
Test name
Test status
Simulation time 31885100 ps
CPU time 26.29 seconds
Started Apr 30 02:25:55 PM PDT 24
Finished Apr 30 02:26:23 PM PDT 24
Peak memory 258332 kb
Host smart-80eafc78-ac61-48dc-9cb6-1a28f3e22920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267695079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.267695079
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.1310988236
Short name T568
Test name
Test status
Simulation time 247620000 ps
CPU time 633.34 seconds
Started Apr 30 02:26:15 PM PDT 24
Finished Apr 30 02:36:49 PM PDT 24
Peak memory 281040 kb
Host smart-74335c3a-ea7a-4184-9e69-adcdf2f2d54e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310988236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.1310988236
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.37130370
Short name T825
Test name
Test status
Simulation time 21358600 ps
CPU time 26.95 seconds
Started Apr 30 02:25:51 PM PDT 24
Finished Apr 30 02:26:19 PM PDT 24
Peak memory 261016 kb
Host smart-7c4d2732-90c8-404e-8da9-83b215f420fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37130370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.37130370
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.757545930
Short name T445
Test name
Test status
Simulation time 9394957900 ps
CPU time 214.6 seconds
Started Apr 30 02:26:02 PM PDT 24
Finished Apr 30 02:29:38 PM PDT 24
Peak memory 264644 kb
Host smart-d29befc9-3284-492f-9df6-0d2ac1c74241
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757545930 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.flash_ctrl_wo.757545930
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.2502860864
Short name T701
Test name
Test status
Simulation time 104147600 ps
CPU time 13.81 seconds
Started Apr 30 02:27:02 PM PDT 24
Finished Apr 30 02:27:17 PM PDT 24
Peak memory 257732 kb
Host smart-8290a8e6-23a1-4d96-b7e9-625c2910dde4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502860864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.2
502860864
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_config_regwen.2088524515
Short name T740
Test name
Test status
Simulation time 66283600 ps
CPU time 13.91 seconds
Started Apr 30 02:26:59 PM PDT 24
Finished Apr 30 02:27:14 PM PDT 24
Peak memory 264608 kb
Host smart-16bea39a-0096-4691-8caa-a7e3f2c7fbfb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088524515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.flash_ctrl_config_regwen.2088524515
Directory /workspace/1.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.1042842188
Short name T661
Test name
Test status
Simulation time 15125700 ps
CPU time 15.8 seconds
Started Apr 30 02:26:55 PM PDT 24
Finished Apr 30 02:27:11 PM PDT 24
Peak memory 275324 kb
Host smart-02a55cc8-0f66-47c1-87e2-7d1e5a6e6a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042842188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.1042842188
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.1261268741
Short name T98
Test name
Test status
Simulation time 281165400 ps
CPU time 104.67 seconds
Started Apr 30 02:26:46 PM PDT 24
Finished Apr 30 02:28:31 PM PDT 24
Peak memory 280188 kb
Host smart-b38010b9-e876-4429-a037-c67ca4cbc856
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261268741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_derr_detect.1261268741
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.3065092076
Short name T809
Test name
Test status
Simulation time 1396676800 ps
CPU time 344.02 seconds
Started Apr 30 02:26:26 PM PDT 24
Finished Apr 30 02:32:10 PM PDT 24
Peak memory 260652 kb
Host smart-a4710076-3ad2-44b2-b3f6-c90c366e08eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3065092076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.3065092076
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.2082034917
Short name T799
Test name
Test status
Simulation time 9716348300 ps
CPU time 2210.24 seconds
Started Apr 30 02:26:36 PM PDT 24
Finished Apr 30 03:03:27 PM PDT 24
Peak memory 263184 kb
Host smart-b9ef51f3-2379-4b45-beb9-ab60b379e8bc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082034917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_err
or_mp.2082034917
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.184036787
Short name T771
Test name
Test status
Simulation time 1050209300 ps
CPU time 3078.97 seconds
Started Apr 30 02:26:38 PM PDT 24
Finished Apr 30 03:17:58 PM PDT 24
Peak memory 264168 kb
Host smart-84431395-2ad4-4993-946a-e7359a58fec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184036787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.184036787
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.1015141810
Short name T10
Test name
Test status
Simulation time 2576204200 ps
CPU time 887.67 seconds
Started Apr 30 02:26:35 PM PDT 24
Finished Apr 30 02:41:24 PM PDT 24
Peak memory 272676 kb
Host smart-a4e3ab3a-949d-4b98-ba48-7ee8a2d57633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015141810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.1015141810
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.3243507171
Short name T817
Test name
Test status
Simulation time 309728800 ps
CPU time 25.46 seconds
Started Apr 30 02:26:28 PM PDT 24
Finished Apr 30 02:26:54 PM PDT 24
Peak memory 264400 kb
Host smart-c6f7fe97-1e65-49bc-aba3-000de238d10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243507171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.3243507171
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.2146713807
Short name T671
Test name
Test status
Simulation time 48914056700 ps
CPU time 4041.32 seconds
Started Apr 30 02:26:36 PM PDT 24
Finished Apr 30 03:33:58 PM PDT 24
Peak memory 264380 kb
Host smart-5fe0feef-9118-4cc4-b93a-0af89b3b0b4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146713807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.2146713807
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.1743877612
Short name T540
Test name
Test status
Simulation time 76759900 ps
CPU time 121.91 seconds
Started Apr 30 02:26:25 PM PDT 24
Finished Apr 30 02:28:27 PM PDT 24
Peak memory 261756 kb
Host smart-8135d6c6-4137-4d31-ab4f-87a77d9639e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1743877612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.1743877612
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.69357651
Short name T739
Test name
Test status
Simulation time 15508700 ps
CPU time 13.8 seconds
Started Apr 30 02:27:01 PM PDT 24
Finished Apr 30 02:27:16 PM PDT 24
Peak memory 257704 kb
Host smart-d1af009c-e6bb-482e-a73d-14587da851bc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69357651 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.69357651
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.175623551
Short name T78
Test name
Test status
Simulation time 84654807600 ps
CPU time 1874.53 seconds
Started Apr 30 02:26:28 PM PDT 24
Finished Apr 30 02:57:43 PM PDT 24
Peak memory 262704 kb
Host smart-03495da6-cff8-4a78-ad39-b27c25801faf
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175623551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_hw_rma.175623551
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.4143684898
Short name T560
Test name
Test status
Simulation time 40124925600 ps
CPU time 857.88 seconds
Started Apr 30 02:26:28 PM PDT 24
Finished Apr 30 02:40:46 PM PDT 24
Peak memory 262612 kb
Host smart-73bed75d-28df-4f32-8865-d16125aeb184
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143684898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.4143684898
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.1137900236
Short name T751
Test name
Test status
Simulation time 13707395000 ps
CPU time 93.93 seconds
Started Apr 30 02:26:27 PM PDT 24
Finished Apr 30 02:28:02 PM PDT 24
Peak memory 262012 kb
Host smart-b6c3cf37-da1d-446c-aa81-ae376073f121
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137900236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h
w_sec_otp.1137900236
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.640484450
Short name T745
Test name
Test status
Simulation time 8018944300 ps
CPU time 171.2 seconds
Started Apr 30 02:26:43 PM PDT 24
Finished Apr 30 02:29:35 PM PDT 24
Peak memory 293188 kb
Host smart-fadde09e-9e3a-42f1-841b-5e19af3fa1e7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640484450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash
_ctrl_intr_rd.640484450
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.13540469
Short name T163
Test name
Test status
Simulation time 7742540700 ps
CPU time 231.37 seconds
Started Apr 30 02:26:44 PM PDT 24
Finished Apr 30 02:30:37 PM PDT 24
Peak memory 284412 kb
Host smart-3af99644-32fb-42af-b739-628410ab0485
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13540469 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.13540469
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.167098783
Short name T147
Test name
Test status
Simulation time 997909400 ps
CPU time 88.83 seconds
Started Apr 30 02:26:35 PM PDT 24
Finished Apr 30 02:28:05 PM PDT 24
Peak memory 262044 kb
Host smart-c6206601-6b82-4c80-8dff-91fd85c07515
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167098783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.167098783
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.3580854371
Short name T302
Test name
Test status
Simulation time 10011964200 ps
CPU time 142.75 seconds
Started Apr 30 02:26:29 PM PDT 24
Finished Apr 30 02:28:53 PM PDT 24
Peak memory 262120 kb
Host smart-00857d34-110e-4b92-9de6-0d9b4a2604c0
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580854371 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_mp_regions.3580854371
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.2435580038
Short name T850
Test name
Test status
Simulation time 49002900 ps
CPU time 13.84 seconds
Started Apr 30 02:26:55 PM PDT 24
Finished Apr 30 02:27:09 PM PDT 24
Peak memory 278792 kb
Host smart-267b2cfb-036f-4f80-be1f-70ac16fc8822
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2435580038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.2435580038
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.704007316
Short name T553
Test name
Test status
Simulation time 241120700 ps
CPU time 282.71 seconds
Started Apr 30 02:26:23 PM PDT 24
Finished Apr 30 02:31:06 PM PDT 24
Peak memory 264440 kb
Host smart-b990ea5e-a715-43b1-822d-a6a56d9c2033
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=704007316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.704007316
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.4285788742
Short name T557
Test name
Test status
Simulation time 301165000 ps
CPU time 52.5 seconds
Started Apr 30 02:26:20 PM PDT 24
Finished Apr 30 02:27:13 PM PDT 24
Peak memory 261700 kb
Host smart-4fdec2b2-9643-4ed7-a8e4-03d7d07ea203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285788742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.4285788742
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.2065274712
Short name T221
Test name
Test status
Simulation time 1711879300 ps
CPU time 148.2 seconds
Started Apr 30 02:26:19 PM PDT 24
Finished Apr 30 02:28:47 PM PDT 24
Peak memory 264432 kb
Host smart-81401621-564b-4d0c-968f-17c33492df79
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2065274712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.2065274712
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.3425566724
Short name T90
Test name
Test status
Simulation time 121272300 ps
CPU time 30.66 seconds
Started Apr 30 02:26:57 PM PDT 24
Finished Apr 30 02:27:29 PM PDT 24
Peak memory 279184 kb
Host smart-f53ff3d7-9bf7-4a70-b3b2-3a1db230c019
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425566724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.3425566724
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.1967543831
Short name T708
Test name
Test status
Simulation time 70076400 ps
CPU time 34.84 seconds
Started Apr 30 02:26:53 PM PDT 24
Finished Apr 30 02:27:28 PM PDT 24
Peak memory 266916 kb
Host smart-977e85b8-10eb-478a-90cc-85e2a7964ff4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967543831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_re_evict.1967543831
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.546031540
Short name T47
Test name
Test status
Simulation time 46631200 ps
CPU time 21.89 seconds
Started Apr 30 02:26:44 PM PDT 24
Finished Apr 30 02:27:06 PM PDT 24
Peak memory 264660 kb
Host smart-f888539a-7ff4-49f8-b2d6-82a9094a7a4b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546031540 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.546031540
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.1938242937
Short name T650
Test name
Test status
Simulation time 23455300 ps
CPU time 21.11 seconds
Started Apr 30 02:26:35 PM PDT 24
Finished Apr 30 02:26:57 PM PDT 24
Peak memory 264708 kb
Host smart-4ecb4701-e090-4882-8627-774ff0594274
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938242937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl
ash_ctrl_read_word_sweep_serr.1938242937
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.208285407
Short name T112
Test name
Test status
Simulation time 46756274200 ps
CPU time 955.78 seconds
Started Apr 30 02:27:00 PM PDT 24
Finished Apr 30 02:42:57 PM PDT 24
Peak memory 259264 kb
Host smart-715e2bf0-6aae-4f8b-a702-8f7348603d42
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208285407 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.208285407
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.799660983
Short name T713
Test name
Test status
Simulation time 691406800 ps
CPU time 145.12 seconds
Started Apr 30 02:26:38 PM PDT 24
Finished Apr 30 02:29:04 PM PDT 24
Peak memory 288872 kb
Host smart-1df058ea-004b-41a3-9c9c-442b57fb824b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799660983 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.flash_ctrl_ro.799660983
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.717470902
Short name T189
Test name
Test status
Simulation time 1440768600 ps
CPU time 156.19 seconds
Started Apr 30 02:26:44 PM PDT 24
Finished Apr 30 02:29:21 PM PDT 24
Peak memory 281524 kb
Host smart-2e949a0a-e1fb-417a-bedc-41b5943ac8f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
717470902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.717470902
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.1911179651
Short name T176
Test name
Test status
Simulation time 6100082800 ps
CPU time 150.44 seconds
Started Apr 30 02:26:39 PM PDT 24
Finished Apr 30 02:29:10 PM PDT 24
Peak memory 281076 kb
Host smart-9e26090d-b70e-4108-9c32-9974917c46e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911179651 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.1911179651
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.2791846991
Short name T421
Test name
Test status
Simulation time 9572442800 ps
CPU time 554.55 seconds
Started Apr 30 02:26:38 PM PDT 24
Finished Apr 30 02:35:54 PM PDT 24
Peak memory 313888 kb
Host smart-f0d859f3-98da-44c1-92e5-93ecd2480f15
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791846991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.flash_ctrl_rw.2791846991
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.426772661
Short name T643
Test name
Test status
Simulation time 2716031700 ps
CPU time 64.27 seconds
Started Apr 30 02:26:53 PM PDT 24
Finished Apr 30 02:27:58 PM PDT 24
Peak memory 263844 kb
Host smart-b0990129-0031-449c-8bbb-15bd24673ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426772661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.426772661
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.807658458
Short name T741
Test name
Test status
Simulation time 47747400 ps
CPU time 52.64 seconds
Started Apr 30 02:26:25 PM PDT 24
Finished Apr 30 02:27:18 PM PDT 24
Peak memory 269928 kb
Host smart-7bf14f13-b512-40cb-9980-528e57ea2e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807658458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.807658458
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.2756206233
Short name T862
Test name
Test status
Simulation time 53496200 ps
CPU time 25.6 seconds
Started Apr 30 02:26:24 PM PDT 24
Finished Apr 30 02:26:50 PM PDT 24
Peak memory 258392 kb
Host smart-b87114ca-ec49-4857-8a6d-8cad36dd0426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756206233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.2756206233
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.1478721378
Short name T686
Test name
Test status
Simulation time 1113553400 ps
CPU time 1367.76 seconds
Started Apr 30 02:26:55 PM PDT 24
Finished Apr 30 02:49:44 PM PDT 24
Peak memory 287556 kb
Host smart-facf9400-807e-4b82-a2c1-a94dceb2e132
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478721378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres
s_all.1478721378
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.613022583
Short name T901
Test name
Test status
Simulation time 104061700 ps
CPU time 27.32 seconds
Started Apr 30 02:26:19 PM PDT 24
Finished Apr 30 02:26:47 PM PDT 24
Peak memory 258332 kb
Host smart-ce2d8583-3425-4c8f-a6ea-f579e3e68d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613022583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.613022583
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.3338946321
Short name T391
Test name
Test status
Simulation time 12720841500 ps
CPU time 198.91 seconds
Started Apr 30 02:26:35 PM PDT 24
Finished Apr 30 02:29:54 PM PDT 24
Peak memory 259248 kb
Host smart-c0191201-30e2-4037-bffd-b9346b8e4881
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338946321 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_wo.3338946321
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.4107312344
Short name T7
Test name
Test status
Simulation time 204170900 ps
CPU time 14.23 seconds
Started Apr 30 02:29:42 PM PDT 24
Finished Apr 30 02:30:03 PM PDT 24
Peak memory 264552 kb
Host smart-0f52bb05-b306-4763-979b-b623004b0377
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107312344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
4107312344
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.790521124
Short name T501
Test name
Test status
Simulation time 20607000 ps
CPU time 15.92 seconds
Started Apr 30 02:29:43 PM PDT 24
Finished Apr 30 02:30:06 PM PDT 24
Peak memory 274692 kb
Host smart-cfa00207-62e6-42f7-bc99-765ce60ab27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790521124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.790521124
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.3011020611
Short name T642
Test name
Test status
Simulation time 19486400 ps
CPU time 14.33 seconds
Started Apr 30 02:29:42 PM PDT 24
Finished Apr 30 02:30:03 PM PDT 24
Peak memory 257764 kb
Host smart-bc255b07-6a78-41b6-89fc-97a31a48e0de
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011020611 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.3011020611
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.2344445392
Short name T554
Test name
Test status
Simulation time 160170250100 ps
CPU time 900.78 seconds
Started Apr 30 02:29:31 PM PDT 24
Finished Apr 30 02:44:39 PM PDT 24
Peak memory 263124 kb
Host smart-b8a5e3da-93a5-4932-b8ba-0bc381a5485a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344445392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.flash_ctrl_hw_rma_reset.2344445392
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.3996335245
Short name T60
Test name
Test status
Simulation time 2033601000 ps
CPU time 165.53 seconds
Started Apr 30 02:29:30 PM PDT 24
Finished Apr 30 02:32:22 PM PDT 24
Peak memory 262024 kb
Host smart-79058c2a-e635-4df0-b4f2-de6677a94db7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996335245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.3996335245
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.837825709
Short name T85
Test name
Test status
Simulation time 2299654000 ps
CPU time 156.88 seconds
Started Apr 30 02:29:37 PM PDT 24
Finished Apr 30 02:32:22 PM PDT 24
Peak memory 284540 kb
Host smart-acf5ecd9-565c-4ea9-8be7-f3dffab8bb9a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837825709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flas
h_ctrl_intr_rd.837825709
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.3766565006
Short name T359
Test name
Test status
Simulation time 17107891300 ps
CPU time 209.96 seconds
Started Apr 30 02:29:37 PM PDT 24
Finished Apr 30 02:33:14 PM PDT 24
Peak memory 290240 kb
Host smart-8f3a32eb-0f95-40dd-8c55-19f847ab98da
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766565006 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.3766565006
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.3202458793
Short name T416
Test name
Test status
Simulation time 8860585100 ps
CPU time 91.21 seconds
Started Apr 30 02:29:37 PM PDT 24
Finished Apr 30 02:31:16 PM PDT 24
Peak memory 260208 kb
Host smart-6695559e-3604-48b4-8ce0-e4f0a4b66089
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202458793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.3
202458793
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.3338693160
Short name T103
Test name
Test status
Simulation time 49375200 ps
CPU time 13.49 seconds
Started Apr 30 02:29:40 PM PDT 24
Finished Apr 30 02:30:00 PM PDT 24
Peak memory 259216 kb
Host smart-e6a07d33-3e38-455f-a34d-9062bab4c650
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338693160 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.3338693160
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.3994624532
Short name T135
Test name
Test status
Simulation time 36315706100 ps
CPU time 481.89 seconds
Started Apr 30 02:29:33 PM PDT 24
Finished Apr 30 02:37:43 PM PDT 24
Peak memory 272988 kb
Host smart-26de3412-1e35-47fc-9ddf-5bd673884c4b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994624532 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_mp_regions.3994624532
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.348414294
Short name T630
Test name
Test status
Simulation time 145344400 ps
CPU time 110.13 seconds
Started Apr 30 02:29:30 PM PDT 24
Finished Apr 30 02:31:27 PM PDT 24
Peak memory 259176 kb
Host smart-b4cc4358-24e3-48e6-9a7c-4a7a7236c421
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348414294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ot
p_reset.348414294
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.105394116
Short name T906
Test name
Test status
Simulation time 2121772000 ps
CPU time 552.84 seconds
Started Apr 30 02:29:32 PM PDT 24
Finished Apr 30 02:38:52 PM PDT 24
Peak memory 264472 kb
Host smart-d12814cb-f37d-4910-a1a3-f6692f4100be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105394116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.105394116
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.1000845735
Short name T474
Test name
Test status
Simulation time 919591300 ps
CPU time 328.44 seconds
Started Apr 30 02:29:43 PM PDT 24
Finished Apr 30 02:35:18 PM PDT 24
Peak memory 281380 kb
Host smart-dc54bd9a-ee6c-400d-88c1-57a07d55243f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000845735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.1000845735
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.2587705159
Short name T632
Test name
Test status
Simulation time 643697800 ps
CPU time 104.06 seconds
Started Apr 30 02:29:36 PM PDT 24
Finished Apr 30 02:31:28 PM PDT 24
Peak memory 281144 kb
Host smart-66304412-c2e4-43c3-a1eb-8909b55c09d4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587705159 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.flash_ctrl_ro.2587705159
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.2606066077
Short name T508
Test name
Test status
Simulation time 15762956600 ps
CPU time 466.09 seconds
Started Apr 30 02:29:49 PM PDT 24
Finished Apr 30 02:37:45 PM PDT 24
Peak memory 309044 kb
Host smart-fa9e91be-3011-4eb3-a79e-630f08e10a5d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606066077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.flash_ctrl_rw.2606066077
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.688859805
Short name T431
Test name
Test status
Simulation time 1707444300 ps
CPU time 62.08 seconds
Started Apr 30 02:29:37 PM PDT 24
Finished Apr 30 02:30:46 PM PDT 24
Peak memory 261680 kb
Host smart-4b3c83f3-5cb6-436d-8e2a-562d7244975c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688859805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.688859805
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.2423161825
Short name T216
Test name
Test status
Simulation time 27521300 ps
CPU time 122.97 seconds
Started Apr 30 02:29:31 PM PDT 24
Finished Apr 30 02:31:41 PM PDT 24
Peak memory 278112 kb
Host smart-bd2e7d7f-51b6-44fc-931b-0ec5f61800be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423161825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.2423161825
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.1069237750
Short name T725
Test name
Test status
Simulation time 4433910400 ps
CPU time 175 seconds
Started Apr 30 02:29:49 PM PDT 24
Finished Apr 30 02:32:54 PM PDT 24
Peak memory 264772 kb
Host smart-f7a31d9f-74e2-4b99-9fea-37224d6fb650
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069237750 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.flash_ctrl_wo.1069237750
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.575563165
Short name T180
Test name
Test status
Simulation time 32048600 ps
CPU time 13.78 seconds
Started Apr 30 02:29:58 PM PDT 24
Finished Apr 30 02:30:24 PM PDT 24
Peak memory 264568 kb
Host smart-cb1319a9-1dc5-4a60-973f-d5ab77ea6e56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575563165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.575563165
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.4218534303
Short name T422
Test name
Test status
Simulation time 47081900 ps
CPU time 15.35 seconds
Started Apr 30 02:29:59 PM PDT 24
Finished Apr 30 02:30:27 PM PDT 24
Peak memory 275144 kb
Host smart-18e8209a-c963-4a33-9087-f85c3f339643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218534303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.4218534303
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.1232595566
Short name T678
Test name
Test status
Simulation time 12353900 ps
CPU time 21.29 seconds
Started Apr 30 02:29:57 PM PDT 24
Finished Apr 30 02:30:31 PM PDT 24
Peak memory 279892 kb
Host smart-3b39fba1-4117-4da8-9dfc-ffc31a1b243f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232595566 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.1232595566
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.908941
Short name T500
Test name
Test status
Simulation time 10035240900 ps
CPU time 50.28 seconds
Started Apr 30 02:29:59 PM PDT 24
Finished Apr 30 02:31:03 PM PDT 24
Peak memory 286716 kb
Host smart-9bf67d5f-340e-4812-9e32-714a6da86df7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908941 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.908941
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.314982550
Short name T285
Test name
Test status
Simulation time 15209400 ps
CPU time 13.05 seconds
Started Apr 30 02:30:00 PM PDT 24
Finished Apr 30 02:30:27 PM PDT 24
Peak memory 257668 kb
Host smart-44fa934f-2eb1-4ac3-8898-5b0f530c5e72
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314982550 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.314982550
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.1386729298
Short name T716
Test name
Test status
Simulation time 1952236500 ps
CPU time 157.52 seconds
Started Apr 30 02:29:43 PM PDT 24
Finished Apr 30 02:32:27 PM PDT 24
Peak memory 261472 kb
Host smart-889d01d1-0fbd-4f05-a324-497e7a90f74a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386729298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
hw_sec_otp.1386729298
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.2574271671
Short name T811
Test name
Test status
Simulation time 2382444400 ps
CPU time 160.73 seconds
Started Apr 30 02:29:50 PM PDT 24
Finished Apr 30 02:32:41 PM PDT 24
Peak memory 292636 kb
Host smart-63180e05-5682-49cb-ade3-2e4ec54aa733
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574271671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_intr_rd.2574271671
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.1352458474
Short name T601
Test name
Test status
Simulation time 16939235600 ps
CPU time 218.33 seconds
Started Apr 30 02:29:51 PM PDT 24
Finished Apr 30 02:33:40 PM PDT 24
Peak memory 292540 kb
Host smart-db900c7c-2550-47ee-9abd-865bebb5b711
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352458474 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.1352458474
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.364098171
Short name T875
Test name
Test status
Simulation time 3383944000 ps
CPU time 66.59 seconds
Started Apr 30 02:29:50 PM PDT 24
Finished Apr 30 02:31:08 PM PDT 24
Peak memory 260072 kb
Host smart-b4737d9f-8305-4e00-9234-9d8b61524c99
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364098171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.364098171
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.2754702374
Short name T785
Test name
Test status
Simulation time 127045300 ps
CPU time 13.56 seconds
Started Apr 30 02:29:58 PM PDT 24
Finished Apr 30 02:30:24 PM PDT 24
Peak memory 264664 kb
Host smart-9a58e987-1a34-4266-84a7-f4773c65f4a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754702374 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.2754702374
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.1555243512
Short name T150
Test name
Test status
Simulation time 13020984500 ps
CPU time 442.06 seconds
Started Apr 30 02:29:48 PM PDT 24
Finished Apr 30 02:37:20 PM PDT 24
Peak memory 272812 kb
Host smart-fe8e1f14-e14d-4ef2-8016-d3564b0d0dd3
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555243512 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_mp_regions.1555243512
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.2895969762
Short name T863
Test name
Test status
Simulation time 41494400 ps
CPU time 110.61 seconds
Started Apr 30 02:29:51 PM PDT 24
Finished Apr 30 02:31:52 PM PDT 24
Peak memory 259228 kb
Host smart-6a41622d-695c-4f9b-9e6c-b14afa271965
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895969762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o
tp_reset.2895969762
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.1807491724
Short name T743
Test name
Test status
Simulation time 1445450800 ps
CPU time 407 seconds
Started Apr 30 02:29:43 PM PDT 24
Finished Apr 30 02:36:37 PM PDT 24
Peak memory 261632 kb
Host smart-d7fac78d-ad6c-42e0-8bef-ac9a601b7477
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1807491724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.1807491724
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.2029986629
Short name T152
Test name
Test status
Simulation time 2148383300 ps
CPU time 1385.57 seconds
Started Apr 30 02:29:51 PM PDT 24
Finished Apr 30 02:53:07 PM PDT 24
Peak memory 286544 kb
Host smart-ce1dc7be-0117-4618-9af8-c23e995c0c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029986629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.2029986629
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.1231046367
Short name T556
Test name
Test status
Simulation time 111821200 ps
CPU time 34.26 seconds
Started Apr 30 02:29:57 PM PDT 24
Finished Apr 30 02:30:44 PM PDT 24
Peak memory 273060 kb
Host smart-73546165-4112-4ddd-b236-05f26bba5867
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231046367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_re_evict.1231046367
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.3662868178
Short name T192
Test name
Test status
Simulation time 512920800 ps
CPU time 134.48 seconds
Started Apr 30 02:29:51 PM PDT 24
Finished Apr 30 02:32:17 PM PDT 24
Peak memory 288900 kb
Host smart-9ff7e0aa-639b-48b5-9a34-2c8daf22bca7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662868178 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.flash_ctrl_ro.3662868178
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.2817503568
Short name T823
Test name
Test status
Simulation time 3995981400 ps
CPU time 643.66 seconds
Started Apr 30 02:29:52 PM PDT 24
Finished Apr 30 02:40:47 PM PDT 24
Peak memory 309204 kb
Host smart-38c5435e-7250-40cc-b73d-96615f278e77
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817503568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.flash_ctrl_rw.2817503568
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.975388916
Short name T179
Test name
Test status
Simulation time 12348105800 ps
CPU time 76.31 seconds
Started Apr 30 02:29:59 PM PDT 24
Finished Apr 30 02:31:28 PM PDT 24
Peak memory 261744 kb
Host smart-b8734320-cea3-44d2-b55d-1e4c9714607a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975388916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.975388916
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.2537948586
Short name T443
Test name
Test status
Simulation time 55859000 ps
CPU time 121.12 seconds
Started Apr 30 02:29:42 PM PDT 24
Finished Apr 30 02:31:50 PM PDT 24
Peak memory 275104 kb
Host smart-0e0b8f72-a063-4c0f-8d22-e3de61adfd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537948586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.2537948586
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.3677451324
Short name T34
Test name
Test status
Simulation time 2436427300 ps
CPU time 218.24 seconds
Started Apr 30 02:29:50 PM PDT 24
Finished Apr 30 02:33:40 PM PDT 24
Peak memory 264820 kb
Host smart-c1767664-8758-4388-9e1c-ab9aa7cbf269
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677451324 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.flash_ctrl_wo.3677451324
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.1131864115
Short name T486
Test name
Test status
Simulation time 71279000 ps
CPU time 13.73 seconds
Started Apr 30 02:30:21 PM PDT 24
Finished Apr 30 02:30:53 PM PDT 24
Peak memory 264608 kb
Host smart-996651be-323f-4573-8cc9-3302fbface9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131864115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.
1131864115
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.1738262422
Short name T488
Test name
Test status
Simulation time 25059000 ps
CPU time 16.15 seconds
Started Apr 30 02:30:20 PM PDT 24
Finished Apr 30 02:30:55 PM PDT 24
Peak memory 274600 kb
Host smart-af84a2eb-f9e4-45c3-9c9b-dedd5aeac393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738262422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.1738262422
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.2972479845
Short name T819
Test name
Test status
Simulation time 10016022900 ps
CPU time 79.1 seconds
Started Apr 30 02:30:19 PM PDT 24
Finished Apr 30 02:31:56 PM PDT 24
Peak memory 292148 kb
Host smart-5cb561ef-ca6c-4926-a23e-ad2dedd3da0a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972479845 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.2972479845
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.3357248836
Short name T535
Test name
Test status
Simulation time 40123139700 ps
CPU time 940.28 seconds
Started Apr 30 02:30:04 PM PDT 24
Finished Apr 30 02:46:00 PM PDT 24
Peak memory 263676 kb
Host smart-55642d79-edc4-46c6-9c3f-070d0929ddf4
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357248836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.flash_ctrl_hw_rma_reset.3357248836
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.2580175561
Short name T768
Test name
Test status
Simulation time 18218131200 ps
CPU time 122.21 seconds
Started Apr 30 02:30:05 PM PDT 24
Finished Apr 30 02:32:23 PM PDT 24
Peak memory 262024 kb
Host smart-eab292d4-3257-4ab0-8b9b-efd0c2458d5d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580175561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_
hw_sec_otp.2580175561
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.681216497
Short name T13
Test name
Test status
Simulation time 3909746700 ps
CPU time 173.83 seconds
Started Apr 30 02:30:14 PM PDT 24
Finished Apr 30 02:33:25 PM PDT 24
Peak memory 293552 kb
Host smart-ba3df8ce-418f-4c5d-a154-80a0434fcf71
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681216497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flas
h_ctrl_intr_rd.681216497
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.3771038391
Short name T274
Test name
Test status
Simulation time 18479570700 ps
CPU time 251.95 seconds
Started Apr 30 02:30:13 PM PDT 24
Finished Apr 30 02:34:43 PM PDT 24
Peak memory 290332 kb
Host smart-e0f3b64c-04b2-4837-9e1f-7c0f6e58ee31
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771038391 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.3771038391
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.799073910
Short name T297
Test name
Test status
Simulation time 1697302500 ps
CPU time 101.53 seconds
Started Apr 30 02:30:07 PM PDT 24
Finished Apr 30 02:32:05 PM PDT 24
Peak memory 259116 kb
Host smart-a6c3c665-ed47-4a30-80e6-14e55caca8b2
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799073910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.799073910
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.350021465
Short name T882
Test name
Test status
Simulation time 47533900 ps
CPU time 13.3 seconds
Started Apr 30 02:30:19 PM PDT 24
Finished Apr 30 02:30:51 PM PDT 24
Peak memory 259064 kb
Host smart-812662bd-98b6-48d6-9db0-7460c7df9429
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350021465 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.350021465
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.3533971702
Short name T856
Test name
Test status
Simulation time 24291618200 ps
CPU time 352.87 seconds
Started Apr 30 02:30:05 PM PDT 24
Finished Apr 30 02:36:13 PM PDT 24
Peak memory 273856 kb
Host smart-58fefabc-645d-4621-8d10-b5a943fa7b81
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533971702 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_mp_regions.3533971702
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.1481328317
Short name T113
Test name
Test status
Simulation time 257776000 ps
CPU time 133.89 seconds
Started Apr 30 02:30:05 PM PDT 24
Finished Apr 30 02:32:35 PM PDT 24
Peak memory 259288 kb
Host smart-9a177eeb-3e4d-4372-89fd-4afb5bbacf53
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481328317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o
tp_reset.1481328317
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.2922480181
Short name T511
Test name
Test status
Simulation time 172194200 ps
CPU time 236.78 seconds
Started Apr 30 02:30:04 PM PDT 24
Finished Apr 30 02:34:17 PM PDT 24
Peak memory 260720 kb
Host smart-77005687-5a4e-477f-8b76-04beb7170029
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2922480181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.2922480181
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.784356588
Short name T804
Test name
Test status
Simulation time 8933304600 ps
CPU time 1480.69 seconds
Started Apr 30 02:30:05 PM PDT 24
Finished Apr 30 02:55:02 PM PDT 24
Peak memory 288816 kb
Host smart-7ee5cae9-aafb-41d1-b5af-64a346e8851e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784356588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.784356588
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.3461789455
Short name T92
Test name
Test status
Simulation time 676679100 ps
CPU time 162.6 seconds
Started Apr 30 02:30:13 PM PDT 24
Finished Apr 30 02:33:14 PM PDT 24
Peak memory 281172 kb
Host smart-6c389bc8-9b4d-42ca-bed3-8cab80bd9337
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461789455 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.flash_ctrl_ro.3461789455
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.1451741178
Short name T878
Test name
Test status
Simulation time 58456549700 ps
CPU time 759.88 seconds
Started Apr 30 02:30:14 PM PDT 24
Finished Apr 30 02:43:12 PM PDT 24
Peak memory 313952 kb
Host smart-341dd6c1-6ace-4a7d-8627-44c56a5e0d26
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451741178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.flash_ctrl_rw.1451741178
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.2480051851
Short name T513
Test name
Test status
Simulation time 31660700 ps
CPU time 220.17 seconds
Started Apr 30 02:29:57 PM PDT 24
Finished Apr 30 02:33:49 PM PDT 24
Peak memory 276680 kb
Host smart-c982d9a1-953f-4a04-9878-8ad5ef3a528d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480051851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.2480051851
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.4235766502
Short name T565
Test name
Test status
Simulation time 3789905500 ps
CPU time 206.14 seconds
Started Apr 30 02:30:09 PM PDT 24
Finished Apr 30 02:33:51 PM PDT 24
Peak memory 259000 kb
Host smart-611fd125-8d59-423a-baf7-f78adcaa46bf
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235766502 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.flash_ctrl_wo.4235766502
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.4103720300
Short name T279
Test name
Test status
Simulation time 113273400 ps
CPU time 13.58 seconds
Started Apr 30 02:30:34 PM PDT 24
Finished Apr 30 02:31:07 PM PDT 24
Peak memory 257648 kb
Host smart-c0ec78e0-dbbb-48f9-bf17-d4399470f3d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103720300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
4103720300
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.3716005978
Short name T907
Test name
Test status
Simulation time 62367100 ps
CPU time 15.77 seconds
Started Apr 30 02:30:33 PM PDT 24
Finished Apr 30 02:31:08 PM PDT 24
Peak memory 274492 kb
Host smart-63f8d01b-fa5b-4bd9-8384-38e0afd055b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716005978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.3716005978
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.256622388
Short name T333
Test name
Test status
Simulation time 10031749200 ps
CPU time 53.37 seconds
Started Apr 30 02:30:33 PM PDT 24
Finished Apr 30 02:31:45 PM PDT 24
Peak memory 271752 kb
Host smart-93e5a0cb-6002-4751-a191-089931097dea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256622388 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.256622388
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.771295311
Short name T717
Test name
Test status
Simulation time 32924000 ps
CPU time 13.64 seconds
Started Apr 30 02:30:32 PM PDT 24
Finished Apr 30 02:31:04 PM PDT 24
Peak memory 264632 kb
Host smart-f08d64ad-d396-4486-9eea-a374903b4246
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771295311 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.771295311
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.1391083989
Short name T903
Test name
Test status
Simulation time 160167991700 ps
CPU time 909.21 seconds
Started Apr 30 02:30:20 PM PDT 24
Finished Apr 30 02:45:48 PM PDT 24
Peak memory 262664 kb
Host smart-b7a9c8b0-2a5d-4e29-bac7-a58411e21dbf
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391083989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.flash_ctrl_hw_rma_reset.1391083989
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.3250701843
Short name T874
Test name
Test status
Simulation time 1664876400 ps
CPU time 68.45 seconds
Started Apr 30 02:30:20 PM PDT 24
Finished Apr 30 02:31:47 PM PDT 24
Peak memory 262060 kb
Host smart-5edd5a4d-7076-40e6-8046-96777843de47
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250701843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
hw_sec_otp.3250701843
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd.2000831670
Short name T600
Test name
Test status
Simulation time 2043172100 ps
CPU time 153.4 seconds
Started Apr 30 02:30:26 PM PDT 24
Finished Apr 30 02:33:19 PM PDT 24
Peak memory 290392 kb
Host smart-3b67bdff-4274-4340-8591-47e507bab275
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000831670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_intr_rd.2000831670
Directory /workspace/13.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.3834188105
Short name T354
Test name
Test status
Simulation time 16649156500 ps
CPU time 234.09 seconds
Started Apr 30 02:30:28 PM PDT 24
Finished Apr 30 02:34:42 PM PDT 24
Peak memory 292040 kb
Host smart-2ef33856-4d1a-49a6-a23d-079a2038fb65
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834188105 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.3834188105
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.3834720010
Short name T617
Test name
Test status
Simulation time 7048298400 ps
CPU time 71.32 seconds
Started Apr 30 02:30:28 PM PDT 24
Finished Apr 30 02:31:59 PM PDT 24
Peak memory 259972 kb
Host smart-072257ea-2d80-4373-9b4c-99621891553b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834720010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.3
834720010
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.1811268885
Short name T847
Test name
Test status
Simulation time 48100600 ps
CPU time 14.56 seconds
Started Apr 30 02:30:33 PM PDT 24
Finished Apr 30 02:31:06 PM PDT 24
Peak memory 264616 kb
Host smart-59bb141d-cddf-4540-bfc2-4a20ad3ffe0c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811268885 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.1811268885
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.159940469
Short name T153
Test name
Test status
Simulation time 12135274300 ps
CPU time 277.55 seconds
Started Apr 30 02:30:22 PM PDT 24
Finished Apr 30 02:35:18 PM PDT 24
Peak memory 273640 kb
Host smart-2ae8b0ff-64d3-4bb4-8ca1-e557a14188fa
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159940469 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_mp_regions.159940469
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.2737037413
Short name T286
Test name
Test status
Simulation time 414715400 ps
CPU time 133.21 seconds
Started Apr 30 02:30:21 PM PDT 24
Finished Apr 30 02:32:53 PM PDT 24
Peak memory 259080 kb
Host smart-c02dbf4d-52f1-43c1-b387-0b0922a75066
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737037413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o
tp_reset.2737037413
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.1213197085
Short name T174
Test name
Test status
Simulation time 4578315200 ps
CPU time 194.37 seconds
Started Apr 30 02:30:20 PM PDT 24
Finished Apr 30 02:33:53 PM PDT 24
Peak memory 261052 kb
Host smart-849ba4d1-0089-4a79-a6b1-d6af01b1cc12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1213197085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.1213197085
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.1071758295
Short name T489
Test name
Test status
Simulation time 403151600 ps
CPU time 350.98 seconds
Started Apr 30 02:30:21 PM PDT 24
Finished Apr 30 02:36:31 PM PDT 24
Peak memory 277516 kb
Host smart-df742f28-3a66-434d-a992-4286d299a96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071758295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.1071758295
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.3238627168
Short name T177
Test name
Test status
Simulation time 110821600 ps
CPU time 36.6 seconds
Started Apr 30 02:30:34 PM PDT 24
Finished Apr 30 02:31:30 PM PDT 24
Peak memory 274096 kb
Host smart-ce78c280-9866-4130-90d3-da26063a3579
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238627168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.3238627168
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.3446739787
Short name T559
Test name
Test status
Simulation time 2349623900 ps
CPU time 135.41 seconds
Started Apr 30 02:30:28 PM PDT 24
Finished Apr 30 02:33:03 PM PDT 24
Peak memory 288856 kb
Host smart-74965e15-8c74-44cd-8631-af7c04ed9a0f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446739787 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.flash_ctrl_ro.3446739787
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.658696770
Short name T308
Test name
Test status
Simulation time 4361643800 ps
CPU time 531.11 seconds
Started Apr 30 02:30:27 PM PDT 24
Finished Apr 30 02:39:38 PM PDT 24
Peak memory 309028 kb
Host smart-bed9efa7-77a9-40de-ab13-81574fd54f90
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658696770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.flash_ctrl_rw.658696770
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.1603693147
Short name T213
Test name
Test status
Simulation time 28543000 ps
CPU time 120.43 seconds
Started Apr 30 02:30:20 PM PDT 24
Finished Apr 30 02:32:38 PM PDT 24
Peak memory 275304 kb
Host smart-a35cc149-76f2-4e2c-84c8-1d2be9fd8609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603693147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.1603693147
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.845900817
Short name T144
Test name
Test status
Simulation time 17742051000 ps
CPU time 181.66 seconds
Started Apr 30 02:30:28 PM PDT 24
Finished Apr 30 02:33:49 PM PDT 24
Peak memory 264820 kb
Host smart-4649618d-84de-4228-aabb-40041c207bbb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845900817 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.flash_ctrl_wo.845900817
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.4080059702
Short name T426
Test name
Test status
Simulation time 24356800 ps
CPU time 15.77 seconds
Started Apr 30 02:30:49 PM PDT 24
Finished Apr 30 02:31:22 PM PDT 24
Peak memory 274732 kb
Host smart-843720b9-d329-40ee-b73e-1b98b9a78a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080059702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.4080059702
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.1856339007
Short name T720
Test name
Test status
Simulation time 10013553700 ps
CPU time 102.45 seconds
Started Apr 30 02:30:46 PM PDT 24
Finished Apr 30 02:32:46 PM PDT 24
Peak memory 317740 kb
Host smart-ee9c132d-4e62-496f-b5b9-00574afa6b4e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856339007 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.1856339007
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.4154194177
Short name T748
Test name
Test status
Simulation time 49677300 ps
CPU time 13.57 seconds
Started Apr 30 02:30:50 PM PDT 24
Finished Apr 30 02:31:21 PM PDT 24
Peak memory 258768 kb
Host smart-34eff9c8-c10f-47be-912c-0c3b679241ec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154194177 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.4154194177
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.4260047594
Short name T27
Test name
Test status
Simulation time 160200824200 ps
CPU time 927.64 seconds
Started Apr 30 02:30:33 PM PDT 24
Finished Apr 30 02:46:19 PM PDT 24
Peak memory 263160 kb
Host smart-966eb4dc-7cac-46bd-822f-bc157bb73e68
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260047594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.flash_ctrl_hw_rma_reset.4260047594
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.1160092482
Short name T868
Test name
Test status
Simulation time 20848005500 ps
CPU time 76.41 seconds
Started Apr 30 02:30:34 PM PDT 24
Finished Apr 30 02:32:09 PM PDT 24
Peak memory 261444 kb
Host smart-c517e648-3b43-432b-a115-f62ad22707f6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160092482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.1160092482
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.1876187185
Short name T622
Test name
Test status
Simulation time 16401992800 ps
CPU time 183.5 seconds
Started Apr 30 02:30:40 PM PDT 24
Finished Apr 30 02:34:01 PM PDT 24
Peak memory 284216 kb
Host smart-a8910bc8-ffc6-407e-aa3a-99a8307dc858
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876187185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_intr_rd.1876187185
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.3452090876
Short name T706
Test name
Test status
Simulation time 15557644000 ps
CPU time 217.25 seconds
Started Apr 30 02:30:39 PM PDT 24
Finished Apr 30 02:34:34 PM PDT 24
Peak memory 290328 kb
Host smart-4d2f7ac6-302d-4360-b232-566aea0b9b96
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452090876 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.3452090876
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.4259091318
Short name T417
Test name
Test status
Simulation time 3115593700 ps
CPU time 79.35 seconds
Started Apr 30 02:30:35 PM PDT 24
Finished Apr 30 02:32:13 PM PDT 24
Peak memory 260184 kb
Host smart-15592ee8-f092-47b0-8cdf-d3827c861106
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259091318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.4
259091318
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.2569515322
Short name T784
Test name
Test status
Simulation time 15705400 ps
CPU time 13.62 seconds
Started Apr 30 02:30:48 PM PDT 24
Finished Apr 30 02:31:20 PM PDT 24
Peak memory 264688 kb
Host smart-2b284c1a-fb5c-4c53-ab7c-0dc74f066d9d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569515322 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.2569515322
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.2854519466
Short name T149
Test name
Test status
Simulation time 11069492300 ps
CPU time 666.92 seconds
Started Apr 30 02:30:34 PM PDT 24
Finished Apr 30 02:42:00 PM PDT 24
Peak memory 273372 kb
Host smart-bee4842c-4fd4-4dc7-9a12-dac3b59de839
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854519466 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.2854519466
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.609522372
Short name T736
Test name
Test status
Simulation time 37330300 ps
CPU time 132.01 seconds
Started Apr 30 02:30:34 PM PDT 24
Finished Apr 30 02:33:05 PM PDT 24
Peak memory 263396 kb
Host smart-f637a7c6-8e0e-4079-b41e-7279489d6105
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609522372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ot
p_reset.609522372
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.2294804169
Short name T625
Test name
Test status
Simulation time 91900600 ps
CPU time 70.15 seconds
Started Apr 30 02:30:32 PM PDT 24
Finished Apr 30 02:32:01 PM PDT 24
Peak memory 261860 kb
Host smart-b2467f3c-ec31-423e-bfdb-05b5ca5b2e4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2294804169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.2294804169
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.3171421846
Short name T916
Test name
Test status
Simulation time 43295300 ps
CPU time 274.56 seconds
Started Apr 30 02:30:32 PM PDT 24
Finished Apr 30 02:35:25 PM PDT 24
Peak memory 280832 kb
Host smart-ad8e3327-7394-43cc-857d-3ff5d928af86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171421846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.3171421846
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.2005387874
Short name T595
Test name
Test status
Simulation time 7861616800 ps
CPU time 153.92 seconds
Started Apr 30 02:30:32 PM PDT 24
Finished Apr 30 02:33:25 PM PDT 24
Peak memory 281184 kb
Host smart-7d5253e9-13d2-4a4a-8ca1-7f65c0e95ef0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005387874 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.flash_ctrl_ro.2005387874
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.3462293319
Short name T406
Test name
Test status
Simulation time 2640546200 ps
CPU time 70.8 seconds
Started Apr 30 02:30:49 PM PDT 24
Finished Apr 30 02:32:17 PM PDT 24
Peak memory 262636 kb
Host smart-52024778-9181-4621-9902-68ddf16ddd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462293319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.3462293319
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.1758366755
Short name T214
Test name
Test status
Simulation time 60727200 ps
CPU time 213.76 seconds
Started Apr 30 02:30:33 PM PDT 24
Finished Apr 30 02:34:26 PM PDT 24
Peak memory 276820 kb
Host smart-3d6eb418-3ee9-4340-9ce4-bc97286fc6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758366755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.1758366755
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.3319877878
Short name T921
Test name
Test status
Simulation time 2536337200 ps
CPU time 181.17 seconds
Started Apr 30 02:30:32 PM PDT 24
Finished Apr 30 02:33:52 PM PDT 24
Peak memory 258536 kb
Host smart-817d7269-dd50-4df6-affa-5cae97e80aa1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319877878 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.flash_ctrl_wo.3319877878
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.2002929810
Short name T428
Test name
Test status
Simulation time 53277900 ps
CPU time 14.48 seconds
Started Apr 30 02:31:05 PM PDT 24
Finished Apr 30 02:31:35 PM PDT 24
Peak memory 264552 kb
Host smart-2c9a81e4-01a6-475d-870d-1c7feddaf8ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002929810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
2002929810
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.1216431816
Short name T439
Test name
Test status
Simulation time 22661400 ps
CPU time 15.91 seconds
Started Apr 30 02:31:05 PM PDT 24
Finished Apr 30 02:31:36 PM PDT 24
Peak memory 275336 kb
Host smart-1a01c6dd-a728-490e-b105-60fc54ab9075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216431816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.1216431816
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.105832817
Short name T21
Test name
Test status
Simulation time 28161000 ps
CPU time 20.7 seconds
Started Apr 30 02:30:58 PM PDT 24
Finished Apr 30 02:31:35 PM PDT 24
Peak memory 272932 kb
Host smart-c48003e8-bb49-4558-a5eb-69c4414c2dcb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105832817 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.105832817
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.2779291303
Short name T115
Test name
Test status
Simulation time 10012221700 ps
CPU time 119.68 seconds
Started Apr 30 02:31:05 PM PDT 24
Finished Apr 30 02:33:20 PM PDT 24
Peak memory 340244 kb
Host smart-d634658c-7c88-44b5-8f24-8466cc287bc7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779291303 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.2779291303
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.1843173034
Short name T102
Test name
Test status
Simulation time 45817000 ps
CPU time 13.54 seconds
Started Apr 30 02:31:05 PM PDT 24
Finished Apr 30 02:31:34 PM PDT 24
Peak memory 257984 kb
Host smart-5e1d50c9-1e42-42a1-a9f8-8af2fa318c1a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843173034 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.1843173034
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.656777789
Short name T853
Test name
Test status
Simulation time 1253519100 ps
CPU time 112.97 seconds
Started Apr 30 02:30:52 PM PDT 24
Finished Apr 30 02:33:02 PM PDT 24
Peak memory 262040 kb
Host smart-4b13985e-7d00-4c99-a063-3865a7310397
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656777789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_h
w_sec_otp.656777789
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd.1207825164
Short name T358
Test name
Test status
Simulation time 1900869100 ps
CPU time 152.55 seconds
Started Apr 30 02:30:58 PM PDT 24
Finished Apr 30 02:33:47 PM PDT 24
Peak memory 294444 kb
Host smart-d8872cc5-3f68-4ae0-89a2-0e85a554dfa8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207825164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_intr_rd.1207825164
Directory /workspace/15.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.4199059011
Short name T651
Test name
Test status
Simulation time 8676838900 ps
CPU time 209.65 seconds
Started Apr 30 02:30:58 PM PDT 24
Finished Apr 30 02:34:45 PM PDT 24
Peak memory 284284 kb
Host smart-01af7cac-e0d4-48a6-a59b-4800c2077539
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199059011 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.4199059011
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.486558282
Short name T769
Test name
Test status
Simulation time 18833983500 ps
CPU time 68.44 seconds
Started Apr 30 02:30:53 PM PDT 24
Finished Apr 30 02:32:19 PM PDT 24
Peak memory 259992 kb
Host smart-2c3e9a17-1d6a-4547-bd0a-8ef16296e1a8
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486558282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.486558282
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.3142434998
Short name T653
Test name
Test status
Simulation time 27053000 ps
CPU time 13.89 seconds
Started Apr 30 02:31:04 PM PDT 24
Finished Apr 30 02:31:34 PM PDT 24
Peak memory 259224 kb
Host smart-2c300434-8bc0-4b59-b22a-ed5604276959
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142434998 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.3142434998
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.984694106
Short name T289
Test name
Test status
Simulation time 4314086300 ps
CPU time 122.14 seconds
Started Apr 30 02:30:50 PM PDT 24
Finished Apr 30 02:33:10 PM PDT 24
Peak memory 261492 kb
Host smart-aac9a45b-2a3b-44c1-be53-d2fbf1ed28fd
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984694106 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_mp_regions.984694106
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.2208287279
Short name T569
Test name
Test status
Simulation time 478969000 ps
CPU time 192.42 seconds
Started Apr 30 02:30:48 PM PDT 24
Finished Apr 30 02:34:18 PM PDT 24
Peak memory 261052 kb
Host smart-3cadebd4-6c73-4f10-aef7-d698c0586632
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2208287279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.2208287279
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.2445723775
Short name T846
Test name
Test status
Simulation time 420977000 ps
CPU time 1311.48 seconds
Started Apr 30 02:30:47 PM PDT 24
Finished Apr 30 02:52:57 PM PDT 24
Peak memory 287224 kb
Host smart-43da2891-4c9c-49ff-9c88-2ab54065407b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445723775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.2445723775
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.1769742579
Short name T363
Test name
Test status
Simulation time 311099900 ps
CPU time 35.83 seconds
Started Apr 30 02:30:59 PM PDT 24
Finished Apr 30 02:31:52 PM PDT 24
Peak memory 273028 kb
Host smart-29f4fafd-0392-4713-a4c3-5ea44a00ee20
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769742579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.1769742579
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.1721171058
Short name T202
Test name
Test status
Simulation time 632803700 ps
CPU time 120.48 seconds
Started Apr 30 02:30:50 PM PDT 24
Finished Apr 30 02:33:08 PM PDT 24
Peak memory 281064 kb
Host smart-1a7250d5-5cc8-4eff-a8ad-6411bfc034fe
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721171058 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.flash_ctrl_ro.1721171058
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.3440106994
Short name T172
Test name
Test status
Simulation time 43406519300 ps
CPU time 564.1 seconds
Started Apr 30 02:30:58 PM PDT 24
Finished Apr 30 02:40:39 PM PDT 24
Peak memory 313912 kb
Host smart-3f648c37-9c95-4722-aeb5-87dfb581895b
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440106994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.flash_ctrl_rw.3440106994
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict.4276938968
Short name T366
Test name
Test status
Simulation time 29595000 ps
CPU time 31.82 seconds
Started Apr 30 02:30:58 PM PDT 24
Finished Apr 30 02:31:47 PM PDT 24
Peak memory 273080 kb
Host smart-433d8126-2e69-49d7-8caa-7bab63f50eab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276938968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_rw_evict.4276938968
Directory /workspace/15.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.2689024758
Short name T648
Test name
Test status
Simulation time 421674000 ps
CPU time 55.63 seconds
Started Apr 30 02:31:05 PM PDT 24
Finished Apr 30 02:32:16 PM PDT 24
Peak memory 262656 kb
Host smart-28dc484b-46ad-47b4-931b-205a4f24812c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689024758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.2689024758
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.2049905803
Short name T659
Test name
Test status
Simulation time 69637700 ps
CPU time 123.72 seconds
Started Apr 30 02:30:47 PM PDT 24
Finished Apr 30 02:33:08 PM PDT 24
Peak memory 274908 kb
Host smart-26b8a9c0-0c3d-4672-ab4f-d20c8fa8d039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049905803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.2049905803
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.2529482584
Short name T132
Test name
Test status
Simulation time 7255616200 ps
CPU time 236.79 seconds
Started Apr 30 02:30:53 PM PDT 24
Finished Apr 30 02:35:07 PM PDT 24
Peak memory 259180 kb
Host smart-178bfa03-a753-49ae-8bd6-d4d0e84d07cd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529482584 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.flash_ctrl_wo.2529482584
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.61280891
Short name T277
Test name
Test status
Simulation time 143142800 ps
CPU time 14.36 seconds
Started Apr 30 02:31:28 PM PDT 24
Finished Apr 30 02:32:00 PM PDT 24
Peak memory 257716 kb
Host smart-2cb20f4c-6a77-44b0-92a5-388c49db0e39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61280891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.61280891
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.317598552
Short name T782
Test name
Test status
Simulation time 53718900 ps
CPU time 15.91 seconds
Started Apr 30 02:31:23 PM PDT 24
Finished Apr 30 02:31:56 PM PDT 24
Peak memory 275612 kb
Host smart-3c513a9a-c122-4fce-9fde-d9c56c48f857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317598552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.317598552
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.3281728059
Short name T334
Test name
Test status
Simulation time 10027662000 ps
CPU time 61.02 seconds
Started Apr 30 02:31:28 PM PDT 24
Finished Apr 30 02:32:46 PM PDT 24
Peak memory 275556 kb
Host smart-f426a34f-5805-49d0-ad2e-acebe1b4c92a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281728059 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.3281728059
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.894533668
Short name T888
Test name
Test status
Simulation time 15756700 ps
CPU time 13.45 seconds
Started Apr 30 02:31:27 PM PDT 24
Finished Apr 30 02:31:58 PM PDT 24
Peak memory 258720 kb
Host smart-325d2fae-1634-43a4-82bc-f6e3127812ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894533668 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.894533668
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.4159992159
Short name T693
Test name
Test status
Simulation time 160160447700 ps
CPU time 784.31 seconds
Started Apr 30 02:31:05 PM PDT 24
Finished Apr 30 02:44:25 PM PDT 24
Peak memory 263672 kb
Host smart-e534070b-9ad2-4634-a425-04fb4424b0aa
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159992159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.4159992159
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.1533067505
Short name T454
Test name
Test status
Simulation time 5586241300 ps
CPU time 134 seconds
Started Apr 30 02:31:05 PM PDT 24
Finished Apr 30 02:33:35 PM PDT 24
Peak memory 262120 kb
Host smart-7a4e7dc7-6583-4d6e-9088-0db0bcefbc8d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533067505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.1533067505
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.3866896165
Short name T879
Test name
Test status
Simulation time 2430271800 ps
CPU time 183.66 seconds
Started Apr 30 02:31:14 PM PDT 24
Finished Apr 30 02:34:34 PM PDT 24
Peak memory 284372 kb
Host smart-89127f9f-7482-4c8e-b552-699428d1ff95
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866896165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_intr_rd.3866896165
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.1962375563
Short name T522
Test name
Test status
Simulation time 14753620000 ps
CPU time 181.8 seconds
Started Apr 30 02:31:13 PM PDT 24
Finished Apr 30 02:34:31 PM PDT 24
Peak memory 289284 kb
Host smart-f43ee316-97d8-4181-8a6b-197098792242
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962375563 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.1962375563
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.3540736101
Short name T835
Test name
Test status
Simulation time 1017442700 ps
CPU time 88.74 seconds
Started Apr 30 02:31:13 PM PDT 24
Finished Apr 30 02:32:57 PM PDT 24
Peak memory 262840 kb
Host smart-e3248402-d464-45cf-b731-ea10ad34c345
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540736101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.3
540736101
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.3422692638
Short name T338
Test name
Test status
Simulation time 19012400 ps
CPU time 13.63 seconds
Started Apr 30 02:31:22 PM PDT 24
Finished Apr 30 02:31:53 PM PDT 24
Peak memory 259148 kb
Host smart-2643c9d1-8182-44ca-b679-4321ca1d7d07
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422692638 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.3422692638
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.890103040
Short name T726
Test name
Test status
Simulation time 22331386500 ps
CPU time 382.29 seconds
Started Apr 30 02:31:13 PM PDT 24
Finished Apr 30 02:37:51 PM PDT 24
Peak memory 273816 kb
Host smart-47f87b4d-8acd-4545-9f3f-5de72ff994a0
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890103040 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_mp_regions.890103040
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.129570701
Short name T30
Test name
Test status
Simulation time 40930100 ps
CPU time 109.56 seconds
Started Apr 30 02:31:13 PM PDT 24
Finished Apr 30 02:33:18 PM PDT 24
Peak memory 259312 kb
Host smart-d0e4c4c1-1748-4ef2-8367-8645f409414a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129570701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ot
p_reset.129570701
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.4086449628
Short name T507
Test name
Test status
Simulation time 1392820900 ps
CPU time 576.43 seconds
Started Apr 30 02:31:06 PM PDT 24
Finished Apr 30 02:40:58 PM PDT 24
Peak memory 264476 kb
Host smart-08605c41-6d68-4385-b9b6-6da0986e2f1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4086449628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.4086449628
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.2695814067
Short name T654
Test name
Test status
Simulation time 570433700 ps
CPU time 1147.81 seconds
Started Apr 30 02:31:07 PM PDT 24
Finished Apr 30 02:50:30 PM PDT 24
Peak memory 285264 kb
Host smart-4f888d5e-562f-4864-8571-b093d7c96e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695814067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.2695814067
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.869008864
Short name T485
Test name
Test status
Simulation time 211034500 ps
CPU time 35.92 seconds
Started Apr 30 02:31:25 PM PDT 24
Finished Apr 30 02:32:18 PM PDT 24
Peak memory 275048 kb
Host smart-5bc64abe-c186-4b2f-9095-4c4dde88d16d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869008864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_re_evict.869008864
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.1898284053
Short name T17
Test name
Test status
Simulation time 756469900 ps
CPU time 152.45 seconds
Started Apr 30 02:31:14 PM PDT 24
Finished Apr 30 02:34:02 PM PDT 24
Peak memory 281136 kb
Host smart-86a1c09a-e285-436b-9846-a2dfd1ff85cb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898284053 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.flash_ctrl_ro.1898284053
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.4030473745
Short name T504
Test name
Test status
Simulation time 5280884900 ps
CPU time 732.12 seconds
Started Apr 30 02:31:12 PM PDT 24
Finished Apr 30 02:43:40 PM PDT 24
Peak memory 313956 kb
Host smart-ec0982be-4b4f-4b18-b533-5fea7b2be558
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030473745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.flash_ctrl_rw.4030473745
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.4177424917
Short name T437
Test name
Test status
Simulation time 5980317900 ps
CPU time 61.07 seconds
Started Apr 30 02:31:24 PM PDT 24
Finished Apr 30 02:32:42 PM PDT 24
Peak memory 262064 kb
Host smart-c82d4224-3f02-42db-8271-2d4398077662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177424917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.4177424917
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.2392577166
Short name T288
Test name
Test status
Simulation time 39557500 ps
CPU time 123.09 seconds
Started Apr 30 02:31:07 PM PDT 24
Finished Apr 30 02:33:25 PM PDT 24
Peak memory 276632 kb
Host smart-ba18c921-0468-4dd6-b653-6d9937a211ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392577166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.2392577166
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.3665501093
Short name T684
Test name
Test status
Simulation time 11832744700 ps
CPU time 206.41 seconds
Started Apr 30 02:31:14 PM PDT 24
Finished Apr 30 02:34:57 PM PDT 24
Peak memory 260232 kb
Host smart-695f0f56-e1c4-4d20-847d-51d3941f42eb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665501093 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.flash_ctrl_wo.3665501093
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.2243241328
Short name T845
Test name
Test status
Simulation time 22127200 ps
CPU time 13.69 seconds
Started Apr 30 02:31:36 PM PDT 24
Finished Apr 30 02:32:09 PM PDT 24
Peak memory 264592 kb
Host smart-9d418c03-ef4b-4c71-b3d0-228167aa3d7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243241328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.
2243241328
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.1640105097
Short name T777
Test name
Test status
Simulation time 42685800 ps
CPU time 15.49 seconds
Started Apr 30 02:31:33 PM PDT 24
Finished Apr 30 02:32:07 PM PDT 24
Peak memory 275240 kb
Host smart-57f86cfe-ea44-4f4e-b220-0ac01277c657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640105097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.1640105097
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.1816432341
Short name T57
Test name
Test status
Simulation time 72347200 ps
CPU time 21.48 seconds
Started Apr 30 02:31:33 PM PDT 24
Finished Apr 30 02:32:12 PM PDT 24
Peak memory 273072 kb
Host smart-9c2a6ad6-b99d-4848-bcae-690b7e72373a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816432341 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.1816432341
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.3575243660
Short name T698
Test name
Test status
Simulation time 10043944500 ps
CPU time 94.25 seconds
Started Apr 30 02:31:33 PM PDT 24
Finished Apr 30 02:33:25 PM PDT 24
Peak memory 268104 kb
Host smart-94ff9102-65e6-4ab9-ba23-8901acce8eaa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575243660 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.3575243660
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.3942226575
Short name T518
Test name
Test status
Simulation time 176096300 ps
CPU time 13.81 seconds
Started Apr 30 02:31:33 PM PDT 24
Finished Apr 30 02:32:05 PM PDT 24
Peak memory 257900 kb
Host smart-e3a108be-5209-4fb7-aa1c-a1490d3bbe66
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942226575 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.3942226575
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.2177738123
Short name T772
Test name
Test status
Simulation time 40123440300 ps
CPU time 838.15 seconds
Started Apr 30 02:31:28 PM PDT 24
Finished Apr 30 02:45:44 PM PDT 24
Peak memory 262548 kb
Host smart-ea847ea7-0d13-4b51-b80b-987f9ca8dfc3
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177738123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.flash_ctrl_hw_rma_reset.2177738123
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.2743312547
Short name T320
Test name
Test status
Simulation time 3169252000 ps
CPU time 264.97 seconds
Started Apr 30 02:31:25 PM PDT 24
Finished Apr 30 02:36:07 PM PDT 24
Peak memory 261472 kb
Host smart-b6dcda1b-c75e-402b-a48d-7700c9d3bb80
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743312547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.2743312547
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.2407901220
Short name T744
Test name
Test status
Simulation time 1249405100 ps
CPU time 172.95 seconds
Started Apr 30 02:31:33 PM PDT 24
Finished Apr 30 02:34:44 PM PDT 24
Peak memory 293520 kb
Host smart-8e4a0192-ec2a-42a6-832e-83d7fdafe56a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407901220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.2407901220
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.530987805
Short name T12
Test name
Test status
Simulation time 33215412500 ps
CPU time 226.05 seconds
Started Apr 30 02:31:34 PM PDT 24
Finished Apr 30 02:35:38 PM PDT 24
Peak memory 284440 kb
Host smart-b37c76ef-b220-44d2-ab6b-6e83c2b4d323
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530987805 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.530987805
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.3585299234
Short name T415
Test name
Test status
Simulation time 2172279400 ps
CPU time 67.98 seconds
Started Apr 30 02:31:28 PM PDT 24
Finished Apr 30 02:32:53 PM PDT 24
Peak memory 262244 kb
Host smart-f7cf0818-46be-4119-8958-62b7376ef875
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585299234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.3
585299234
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.1204509634
Short name T564
Test name
Test status
Simulation time 26544600 ps
CPU time 13.39 seconds
Started Apr 30 02:31:32 PM PDT 24
Finished Apr 30 02:32:03 PM PDT 24
Peak memory 264688 kb
Host smart-017a8955-e812-4cc5-a86f-8ee7660c11d6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204509634 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.1204509634
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.2246386645
Short name T848
Test name
Test status
Simulation time 123476899900 ps
CPU time 1043.49 seconds
Started Apr 30 02:31:27 PM PDT 24
Finished Apr 30 02:49:08 PM PDT 24
Peak memory 273456 kb
Host smart-e7780c72-b186-4f90-a4d0-145213d9ac99
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246386645 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_mp_regions.2246386645
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.1677668782
Short name T724
Test name
Test status
Simulation time 115526500 ps
CPU time 235.44 seconds
Started Apr 30 02:31:26 PM PDT 24
Finished Apr 30 02:35:38 PM PDT 24
Peak memory 261868 kb
Host smart-7e9dac7b-1946-4208-9dea-4c1217e20aa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1677668782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.1677668782
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.2035424635
Short name T750
Test name
Test status
Simulation time 802867400 ps
CPU time 23.98 seconds
Started Apr 30 02:31:31 PM PDT 24
Finished Apr 30 02:32:13 PM PDT 24
Peak memory 260324 kb
Host smart-07c24629-33d2-4cf4-be7d-326079425372
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035424635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_re
set.2035424635
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.221145769
Short name T934
Test name
Test status
Simulation time 33910200 ps
CPU time 221.17 seconds
Started Apr 30 02:31:28 PM PDT 24
Finished Apr 30 02:35:26 PM PDT 24
Peak memory 272944 kb
Host smart-50150e47-c814-4bfb-b9e8-70a988c8d1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221145769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.221145769
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.2608105820
Short name T526
Test name
Test status
Simulation time 66069400 ps
CPU time 32.68 seconds
Started Apr 30 02:31:32 PM PDT 24
Finished Apr 30 02:32:23 PM PDT 24
Peak memory 266860 kb
Host smart-1194f556-81cd-41f6-a41e-ef43f69bae5b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608105820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_re_evict.2608105820
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.740060813
Short name T201
Test name
Test status
Simulation time 2575945700 ps
CPU time 131.26 seconds
Started Apr 30 02:31:28 PM PDT 24
Finished Apr 30 02:33:56 PM PDT 24
Peak memory 288892 kb
Host smart-f6c508dd-ba0a-4c96-b58a-d49aaed2c526
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740060813 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.flash_ctrl_ro.740060813
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.196034517
Short name T171
Test name
Test status
Simulation time 16524739100 ps
CPU time 580.21 seconds
Started Apr 30 02:31:25 PM PDT 24
Finished Apr 30 02:41:23 PM PDT 24
Peak memory 313952 kb
Host smart-4f82f579-62c4-4b5c-9c77-61a259884358
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196034517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.flash_ctrl_rw.196034517
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.448154568
Short name T764
Test name
Test status
Simulation time 479693000 ps
CPU time 57.83 seconds
Started Apr 30 02:31:32 PM PDT 24
Finished Apr 30 02:32:48 PM PDT 24
Peak memory 262608 kb
Host smart-29aded6e-ed44-492f-b611-735c19039f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448154568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.448154568
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.402453948
Short name T797
Test name
Test status
Simulation time 76140600 ps
CPU time 95.95 seconds
Started Apr 30 02:31:27 PM PDT 24
Finished Apr 30 02:33:21 PM PDT 24
Peak memory 276004 kb
Host smart-058f675e-e94b-48ed-988a-74882dcf3300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402453948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.402453948
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.1814598037
Short name T131
Test name
Test status
Simulation time 7431738000 ps
CPU time 230.52 seconds
Started Apr 30 02:31:28 PM PDT 24
Finished Apr 30 02:35:36 PM PDT 24
Peak memory 264724 kb
Host smart-644dc75d-1340-4c53-8f77-d182ca6487fb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814598037 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.flash_ctrl_wo.1814598037
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.3320434621
Short name T791
Test name
Test status
Simulation time 288385600 ps
CPU time 14.46 seconds
Started Apr 30 02:31:51 PM PDT 24
Finished Apr 30 02:32:22 PM PDT 24
Peak memory 257584 kb
Host smart-7ecd9d63-cdf0-455e-8375-40af385656bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320434621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
3320434621
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.2193285651
Short name T567
Test name
Test status
Simulation time 24210800 ps
CPU time 13.39 seconds
Started Apr 30 02:31:45 PM PDT 24
Finished Apr 30 02:32:17 PM PDT 24
Peak memory 274772 kb
Host smart-4e9ebd65-8d17-458f-829d-bc2b4f5a0a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193285651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.2193285651
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.3838722236
Short name T802
Test name
Test status
Simulation time 10011753900 ps
CPU time 332.1 seconds
Started Apr 30 02:31:53 PM PDT 24
Finished Apr 30 02:37:41 PM PDT 24
Peak memory 333404 kb
Host smart-0594d493-0fd0-423c-9739-c3adc6b95946
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838722236 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.3838722236
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.4048474394
Short name T828
Test name
Test status
Simulation time 15531000 ps
CPU time 13.71 seconds
Started Apr 30 02:31:52 PM PDT 24
Finished Apr 30 02:32:22 PM PDT 24
Peak memory 257884 kb
Host smart-4496f4af-b0dc-4514-bf3b-f605093e178c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048474394 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.4048474394
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.912342680
Short name T478
Test name
Test status
Simulation time 2802151200 ps
CPU time 99.15 seconds
Started Apr 30 02:31:39 PM PDT 24
Finished Apr 30 02:33:37 PM PDT 24
Peak memory 261744 kb
Host smart-b0da4f7f-c616-421e-944d-ef7ee189494a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912342680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_h
w_sec_otp.912342680
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.2995739777
Short name T307
Test name
Test status
Simulation time 1287955600 ps
CPU time 209.46 seconds
Started Apr 30 02:31:46 PM PDT 24
Finished Apr 30 02:35:34 PM PDT 24
Peak memory 293672 kb
Host smart-84a94b5f-4a7e-443e-8798-a91089a87ec5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995739777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_intr_rd.2995739777
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.2298485884
Short name T798
Test name
Test status
Simulation time 9191857500 ps
CPU time 243.9 seconds
Started Apr 30 02:31:45 PM PDT 24
Finished Apr 30 02:36:07 PM PDT 24
Peak memory 284352 kb
Host smart-180725a9-a3dc-41b8-9ae1-8b5ede0ab1a9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298485884 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.2298485884
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.1532205448
Short name T675
Test name
Test status
Simulation time 28589700 ps
CPU time 13.29 seconds
Started Apr 30 02:31:52 PM PDT 24
Finished Apr 30 02:32:21 PM PDT 24
Peak memory 264692 kb
Host smart-fa723858-387b-4231-8591-1032b5055b87
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532205448 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.1532205448
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.3992427245
Short name T795
Test name
Test status
Simulation time 141077200 ps
CPU time 130.83 seconds
Started Apr 30 02:31:38 PM PDT 24
Finished Apr 30 02:34:07 PM PDT 24
Peak memory 259340 kb
Host smart-6764976d-79f4-4fee-8c76-aad2e69b9583
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992427245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o
tp_reset.3992427245
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.2248999602
Short name T173
Test name
Test status
Simulation time 37100800 ps
CPU time 109.23 seconds
Started Apr 30 02:31:41 PM PDT 24
Finished Apr 30 02:33:49 PM PDT 24
Peak memory 264416 kb
Host smart-6c1e2514-2a1e-42b4-bf0f-e51f26116659
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2248999602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.2248999602
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.2053083348
Short name T461
Test name
Test status
Simulation time 18553500 ps
CPU time 54.09 seconds
Started Apr 30 02:31:37 PM PDT 24
Finished Apr 30 02:32:50 PM PDT 24
Peak memory 261672 kb
Host smart-961b27b2-7669-4262-9849-2d56543c824e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053083348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.2053083348
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.3221767054
Short name T914
Test name
Test status
Simulation time 114139900 ps
CPU time 34.64 seconds
Started Apr 30 02:31:46 PM PDT 24
Finished Apr 30 02:32:39 PM PDT 24
Peak memory 274036 kb
Host smart-d7bed108-9829-4f61-8777-fa22e2939701
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221767054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_re_evict.3221767054
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.2141456970
Short name T645
Test name
Test status
Simulation time 672133800 ps
CPU time 139.9 seconds
Started Apr 30 02:31:45 PM PDT 24
Finished Apr 30 02:34:23 PM PDT 24
Peak memory 281156 kb
Host smart-a9a6d169-8a29-44d3-8290-04e6c4cd23e7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141456970 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.flash_ctrl_ro.2141456970
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.2656516495
Short name T598
Test name
Test status
Simulation time 4652070800 ps
CPU time 558.71 seconds
Started Apr 30 02:31:46 PM PDT 24
Finished Apr 30 02:41:23 PM PDT 24
Peak memory 313860 kb
Host smart-e8634fc5-e6ac-429a-bca8-a0ac3d3ae141
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656516495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.flash_ctrl_rw.2656516495
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.778740068
Short name T407
Test name
Test status
Simulation time 518132900 ps
CPU time 69.75 seconds
Started Apr 30 02:31:45 PM PDT 24
Finished Apr 30 02:33:13 PM PDT 24
Peak memory 261760 kb
Host smart-edf1e36c-b57a-49cd-9906-fb958e8a6636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778740068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.778740068
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.2369506274
Short name T821
Test name
Test status
Simulation time 34796800 ps
CPU time 215.74 seconds
Started Apr 30 02:31:34 PM PDT 24
Finished Apr 30 02:35:28 PM PDT 24
Peak memory 276780 kb
Host smart-0bcf66c7-157f-4400-97db-0405e6d81d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369506274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.2369506274
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.1902067503
Short name T855
Test name
Test status
Simulation time 2256565200 ps
CPU time 171.24 seconds
Started Apr 30 02:31:46 PM PDT 24
Finished Apr 30 02:34:56 PM PDT 24
Peak memory 259164 kb
Host smart-0a5e4573-e4f0-46d4-ab14-ddf2fb1f25ae
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902067503 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.flash_ctrl_wo.1902067503
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.2187655439
Short name T294
Test name
Test status
Simulation time 40215100 ps
CPU time 13.57 seconds
Started Apr 30 02:32:06 PM PDT 24
Finished Apr 30 02:32:29 PM PDT 24
Peak memory 257552 kb
Host smart-84320f4b-20f5-47e7-9a1c-e5298a975962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187655439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
2187655439
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.778973447
Short name T674
Test name
Test status
Simulation time 21596700 ps
CPU time 15.66 seconds
Started Apr 30 02:32:04 PM PDT 24
Finished Apr 30 02:32:31 PM PDT 24
Peak memory 275156 kb
Host smart-78a687cd-d75f-441d-a189-04aa6355aef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778973447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.778973447
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.3412746919
Short name T32
Test name
Test status
Simulation time 11101200 ps
CPU time 22.32 seconds
Started Apr 30 02:32:07 PM PDT 24
Finished Apr 30 02:32:38 PM PDT 24
Peak memory 280180 kb
Host smart-835bc90d-0c6d-426c-a4ed-8c482b6d6025
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412746919 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.3412746919
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.1166668077
Short name T766
Test name
Test status
Simulation time 10019517600 ps
CPU time 168.82 seconds
Started Apr 30 02:32:06 PM PDT 24
Finished Apr 30 02:35:05 PM PDT 24
Peak memory 285672 kb
Host smart-79cb0701-8b97-4fde-ae2c-b19b3e9362b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166668077 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.1166668077
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.4102644733
Short name T184
Test name
Test status
Simulation time 15772800 ps
CPU time 13.54 seconds
Started Apr 30 02:32:05 PM PDT 24
Finished Apr 30 02:32:29 PM PDT 24
Peak memory 257964 kb
Host smart-81e7b541-fc6c-425e-9c80-f2e59cb505be
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102644733 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.4102644733
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.4055791716
Short name T570
Test name
Test status
Simulation time 80146919300 ps
CPU time 782.3 seconds
Started Apr 30 02:32:00 PM PDT 24
Finished Apr 30 02:45:15 PM PDT 24
Peak memory 263248 kb
Host smart-881bb088-02db-4b3e-adce-83686ae69b44
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055791716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.flash_ctrl_hw_rma_reset.4055791716
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.3831862866
Short name T945
Test name
Test status
Simulation time 3185190000 ps
CPU time 37.23 seconds
Started Apr 30 02:31:57 PM PDT 24
Finished Apr 30 02:32:48 PM PDT 24
Peak memory 262096 kb
Host smart-a178d017-8122-428e-95b9-ef718efbf51b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831862866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_
hw_sec_otp.3831862866
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.2997513364
Short name T633
Test name
Test status
Simulation time 3836642300 ps
CPU time 152.4 seconds
Started Apr 30 02:31:58 PM PDT 24
Finished Apr 30 02:34:44 PM PDT 24
Peak memory 290396 kb
Host smart-1090e319-0013-4a7a-abb8-4131e02325f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997513364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_intr_rd.2997513364
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.1209882367
Short name T585
Test name
Test status
Simulation time 143067396600 ps
CPU time 236.68 seconds
Started Apr 30 02:31:57 PM PDT 24
Finished Apr 30 02:36:08 PM PDT 24
Peak memory 284552 kb
Host smart-cbeec257-989c-40d7-a8d5-d0548bffeaac
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209882367 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.1209882367
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.4168289493
Short name T527
Test name
Test status
Simulation time 2125120600 ps
CPU time 68.46 seconds
Started Apr 30 02:32:00 PM PDT 24
Finished Apr 30 02:33:22 PM PDT 24
Peak memory 260156 kb
Host smart-11c95046-8805-4c8c-86ba-d206bdc28764
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168289493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.4
168289493
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.446503354
Short name T140
Test name
Test status
Simulation time 85536032900 ps
CPU time 322.12 seconds
Started Apr 30 02:31:59 PM PDT 24
Finished Apr 30 02:37:34 PM PDT 24
Peak memory 273712 kb
Host smart-a2546683-03f9-4bb4-b99a-0ce818490e19
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446503354 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_mp_regions.446503354
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.365277543
Short name T756
Test name
Test status
Simulation time 71244500 ps
CPU time 111.21 seconds
Started Apr 30 02:31:58 PM PDT 24
Finished Apr 30 02:34:03 PM PDT 24
Peak memory 260476 kb
Host smart-d5d1b1f8-f9a5-4ab0-8392-7556e0dea98d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365277543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ot
p_reset.365277543
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.1773226706
Short name T732
Test name
Test status
Simulation time 89830800 ps
CPU time 433.26 seconds
Started Apr 30 02:31:58 PM PDT 24
Finished Apr 30 02:39:25 PM PDT 24
Peak memory 261868 kb
Host smart-049f10d9-19aa-4de6-9970-591878740592
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1773226706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.1773226706
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.2630690119
Short name T134
Test name
Test status
Simulation time 2861191400 ps
CPU time 864.08 seconds
Started Apr 30 02:31:51 PM PDT 24
Finished Apr 30 02:46:32 PM PDT 24
Peak memory 281968 kb
Host smart-803e0cf6-b895-4512-8834-5ee87de55732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630690119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.2630690119
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.1126824341
Short name T578
Test name
Test status
Simulation time 141415300 ps
CPU time 40.38 seconds
Started Apr 30 02:32:04 PM PDT 24
Finished Apr 30 02:32:55 PM PDT 24
Peak memory 265772 kb
Host smart-19f573be-6225-42a4-bcdd-e17bdcd0cf8d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126824341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.1126824341
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.712190279
Short name T311
Test name
Test status
Simulation time 1026195900 ps
CPU time 121.62 seconds
Started Apr 30 02:31:59 PM PDT 24
Finished Apr 30 02:34:14 PM PDT 24
Peak memory 288996 kb
Host smart-ebdc08ea-bcf6-472f-be87-70d367b172f6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712190279 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.flash_ctrl_ro.712190279
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.1167912160
Short name T498
Test name
Test status
Simulation time 2185328800 ps
CPU time 84.64 seconds
Started Apr 30 02:32:05 PM PDT 24
Finished Apr 30 02:33:40 PM PDT 24
Peak memory 262636 kb
Host smart-d5e3d2fd-2fac-4148-a48f-37f4280c2218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167912160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.1167912160
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.3312831354
Short name T655
Test name
Test status
Simulation time 37857900 ps
CPU time 195.97 seconds
Started Apr 30 02:31:51 PM PDT 24
Finished Apr 30 02:35:24 PM PDT 24
Peak memory 278792 kb
Host smart-dfc681e0-4d37-4420-8500-048d202b2b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312831354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.3312831354
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.1979328759
Short name T495
Test name
Test status
Simulation time 9524488500 ps
CPU time 185.32 seconds
Started Apr 30 02:31:57 PM PDT 24
Finished Apr 30 02:35:16 PM PDT 24
Peak memory 264764 kb
Host smart-5a687690-4b62-4d74-8147-d8b13d2d16f9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979328759 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.flash_ctrl_wo.1979328759
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.686728619
Short name T899
Test name
Test status
Simulation time 151303100 ps
CPU time 14.22 seconds
Started Apr 30 02:27:26 PM PDT 24
Finished Apr 30 02:27:41 PM PDT 24
Peak memory 257704 kb
Host smart-a99c0746-d0ba-4b14-a49a-e87c1a598cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686728619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.686728619
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.993456234
Short name T204
Test name
Test status
Simulation time 20445000 ps
CPU time 13.98 seconds
Started Apr 30 02:27:23 PM PDT 24
Finished Apr 30 02:27:38 PM PDT 24
Peak memory 261140 kb
Host smart-a2d02678-10ee-4978-9611-41f50cb6c985
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993456234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
flash_ctrl_config_regwen.993456234
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.2580712451
Short name T721
Test name
Test status
Simulation time 48994800 ps
CPU time 15.37 seconds
Started Apr 30 02:27:17 PM PDT 24
Finished Apr 30 02:27:34 PM PDT 24
Peak memory 275188 kb
Host smart-9906f413-b407-4ac7-8df1-4dddf8685271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580712451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.2580712451
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.543074066
Short name T801
Test name
Test status
Simulation time 19869045800 ps
CPU time 339.69 seconds
Started Apr 30 02:27:05 PM PDT 24
Finished Apr 30 02:32:45 PM PDT 24
Peak memory 262348 kb
Host smart-47fe494a-e7b4-4c04-a28a-b6bce81b39be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=543074066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.543074066
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.3227786487
Short name T151
Test name
Test status
Simulation time 16269447900 ps
CPU time 2243.01 seconds
Started Apr 30 02:27:13 PM PDT 24
Finished Apr 30 03:04:36 PM PDT 24
Peak memory 263348 kb
Host smart-1dd778b8-a520-4068-94be-3b7682ebc123
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227786487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_err
or_mp.3227786487
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.1095855509
Short name T37
Test name
Test status
Simulation time 550006800 ps
CPU time 2842.1 seconds
Started Apr 30 02:27:14 PM PDT 24
Finished Apr 30 03:14:37 PM PDT 24
Peak memory 264436 kb
Host smart-9fefd68f-0941-4ede-a319-e126d95f0edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095855509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.1095855509
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.3742933036
Short name T913
Test name
Test status
Simulation time 1420964700 ps
CPU time 832.52 seconds
Started Apr 30 02:27:09 PM PDT 24
Finished Apr 30 02:41:03 PM PDT 24
Peak memory 264508 kb
Host smart-ab43217a-9263-4b8e-84a6-f74035697646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742933036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.3742933036
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.3062013272
Short name T658
Test name
Test status
Simulation time 2715475700 ps
CPU time 27.46 seconds
Started Apr 30 02:27:13 PM PDT 24
Finished Apr 30 02:27:41 PM PDT 24
Peak memory 264412 kb
Host smart-6a3db2d4-dcf6-466f-970c-e806d5af2d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062013272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.3062013272
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.535944288
Short name T137
Test name
Test status
Simulation time 67499306400 ps
CPU time 4000.7 seconds
Started Apr 30 02:27:14 PM PDT 24
Finished Apr 30 03:33:56 PM PDT 24
Peak memory 264316 kb
Host smart-ad99ac50-8947-4a94-b793-508c2d767de4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535944288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct
rl_full_mem_access.535944288
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.633150789
Short name T734
Test name
Test status
Simulation time 322814136000 ps
CPU time 1920.02 seconds
Started Apr 30 02:27:12 PM PDT 24
Finished Apr 30 02:59:13 PM PDT 24
Peak memory 264564 kb
Host smart-a3d9cb7b-a379-4110-b94f-7ff8aa0a41df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633150789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.flash_ctrl_host_ctrl_arb.633150789
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.3292100560
Short name T813
Test name
Test status
Simulation time 42881700 ps
CPU time 45.49 seconds
Started Apr 30 02:27:02 PM PDT 24
Finished Apr 30 02:27:49 PM PDT 24
Peak memory 261772 kb
Host smart-abdeb2ee-1be8-4701-9b7c-e7c141bce0ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3292100560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.3292100560
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.4033760765
Short name T566
Test name
Test status
Simulation time 10032948900 ps
CPU time 65.68 seconds
Started Apr 30 02:27:22 PM PDT 24
Finished Apr 30 02:28:29 PM PDT 24
Peak memory 292316 kb
Host smart-a1d6859a-8049-4883-825b-ed0ed6797edb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033760765 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.4033760765
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.939362310
Short name T65
Test name
Test status
Simulation time 219767500 ps
CPU time 14.24 seconds
Started Apr 30 02:27:23 PM PDT 24
Finished Apr 30 02:27:38 PM PDT 24
Peak memory 264896 kb
Host smart-72b95bb3-c6eb-4eb4-b050-7c3273565566
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939362310 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.939362310
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.2005602089
Short name T325
Test name
Test status
Simulation time 85113617700 ps
CPU time 1776.23 seconds
Started Apr 30 02:27:11 PM PDT 24
Finished Apr 30 02:56:48 PM PDT 24
Peak memory 263140 kb
Host smart-40cc4eba-8b75-44c4-b170-1ad042d82577
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005602089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.flash_ctrl_hw_rma.2005602089
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.2010514481
Short name T696
Test name
Test status
Simulation time 380286158800 ps
CPU time 980.74 seconds
Started Apr 30 02:27:10 PM PDT 24
Finished Apr 30 02:43:31 PM PDT 24
Peak memory 262732 kb
Host smart-110606cb-cba1-4c32-bfef-b8596bb1a08d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010514481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.flash_ctrl_hw_rma_reset.2010514481
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.4263659907
Short name T446
Test name
Test status
Simulation time 2043789600 ps
CPU time 75.9 seconds
Started Apr 30 02:27:05 PM PDT 24
Finished Apr 30 02:28:22 PM PDT 24
Peak memory 261564 kb
Host smart-7022362f-dce1-40a2-85ac-a4d8108f962e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263659907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h
w_sec_otp.4263659907
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.3617076475
Short name T814
Test name
Test status
Simulation time 8999961200 ps
CPU time 228.22 seconds
Started Apr 30 02:27:16 PM PDT 24
Finished Apr 30 02:31:05 PM PDT 24
Peak memory 291808 kb
Host smart-b05decda-b993-462b-848b-422875e46c1f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617076475 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.3617076475
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.3618363384
Short name T418
Test name
Test status
Simulation time 2135805200 ps
CPU time 68.01 seconds
Started Apr 30 02:27:11 PM PDT 24
Finished Apr 30 02:28:20 PM PDT 24
Peak memory 259040 kb
Host smart-85cfa3bc-4b6b-4f03-a0bf-4bc2cca05fa1
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618363384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.3618363384
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.1986210871
Short name T922
Test name
Test status
Simulation time 49983500 ps
CPU time 14.27 seconds
Started Apr 30 02:27:23 PM PDT 24
Finished Apr 30 02:27:39 PM PDT 24
Peak memory 259168 kb
Host smart-60475afe-1675-47ac-b18f-0b3a0af9ed77
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986210871 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.1986210871
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.3069965872
Short name T44
Test name
Test status
Simulation time 5271442800 ps
CPU time 69.48 seconds
Started Apr 30 02:27:13 PM PDT 24
Finished Apr 30 02:28:23 PM PDT 24
Peak memory 259124 kb
Host smart-5b5b8230-034c-4594-86fd-919cde0cc469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069965872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.3069965872
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.2650176143
Short name T860
Test name
Test status
Simulation time 219247214000 ps
CPU time 593.28 seconds
Started Apr 30 02:27:10 PM PDT 24
Finished Apr 30 02:37:04 PM PDT 24
Peak memory 272988 kb
Host smart-d9ef1004-8609-459e-9944-1216c0ce15e1
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650176143 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_mp_regions.2650176143
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.3465016467
Short name T105
Test name
Test status
Simulation time 289839600 ps
CPU time 131.57 seconds
Started Apr 30 02:27:08 PM PDT 24
Finished Apr 30 02:29:21 PM PDT 24
Peak memory 260292 kb
Host smart-2a60bcad-a818-4376-a0d9-d2c239fb806a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465016467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot
p_reset.3465016467
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.677268220
Short name T127
Test name
Test status
Simulation time 15616700 ps
CPU time 14.08 seconds
Started Apr 30 02:27:19 PM PDT 24
Finished Apr 30 02:27:34 PM PDT 24
Peak memory 276160 kb
Host smart-4ac5b7f7-9ead-4732-ab7f-4049633d9f32
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=677268220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.677268220
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.1142314302
Short name T280
Test name
Test status
Simulation time 2845588600 ps
CPU time 346.05 seconds
Started Apr 30 02:27:05 PM PDT 24
Finished Apr 30 02:32:52 PM PDT 24
Peak memory 264440 kb
Host smart-362cc731-43c9-413a-8569-eece0804fe47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1142314302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.1142314302
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.4047693225
Short name T158
Test name
Test status
Simulation time 756821100 ps
CPU time 19.54 seconds
Started Apr 30 02:27:18 PM PDT 24
Finished Apr 30 02:27:38 PM PDT 24
Peak memory 262996 kb
Host smart-ddc562ee-49e7-4624-ad17-dae6be06f5ba
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047693225 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.4047693225
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.570980753
Short name T753
Test name
Test status
Simulation time 15242700 ps
CPU time 14.28 seconds
Started Apr 30 02:27:19 PM PDT 24
Finished Apr 30 02:27:34 PM PDT 24
Peak memory 264796 kb
Host smart-45a27ef4-f50b-4a84-a51e-99c7d3c18b59
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570980753 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.570980753
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.4235483247
Short name T669
Test name
Test status
Simulation time 106405400 ps
CPU time 226.2 seconds
Started Apr 30 02:27:01 PM PDT 24
Finished Apr 30 02:30:48 PM PDT 24
Peak memory 280764 kb
Host smart-d8c6fd95-ea4e-44fa-9c30-c5972b8f84b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235483247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.4235483247
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.929333607
Short name T589
Test name
Test status
Simulation time 150186900 ps
CPU time 99.28 seconds
Started Apr 30 02:27:05 PM PDT 24
Finished Apr 30 02:28:45 PM PDT 24
Peak memory 264596 kb
Host smart-5076a919-a922-469b-b928-40cab5233259
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=929333607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.929333607
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.853106694
Short name T917
Test name
Test status
Simulation time 65052800 ps
CPU time 33.43 seconds
Started Apr 30 02:27:19 PM PDT 24
Finished Apr 30 02:27:54 PM PDT 24
Peak memory 271048 kb
Host smart-4eb02e70-1d3c-4921-9df2-48865a7f2605
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853106694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_rd_intg.853106694
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.2488887536
Short name T615
Test name
Test status
Simulation time 351012800 ps
CPU time 33.4 seconds
Started Apr 30 02:27:18 PM PDT 24
Finished Apr 30 02:27:52 PM PDT 24
Peak memory 271484 kb
Host smart-15666cef-64e6-453a-bef7-c46a65d057ad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488887536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.2488887536
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.1555928949
Short name T199
Test name
Test status
Simulation time 57211600 ps
CPU time 21.66 seconds
Started Apr 30 02:27:16 PM PDT 24
Finished Apr 30 02:27:38 PM PDT 24
Peak memory 264804 kb
Host smart-bdb65cb1-9143-4c09-b0cc-7430a07f8a0e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555928949 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.1555928949
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.58755646
Short name T687
Test name
Test status
Simulation time 40104700 ps
CPU time 23.55 seconds
Started Apr 30 02:27:11 PM PDT 24
Finished Apr 30 02:27:35 PM PDT 24
Peak memory 264068 kb
Host smart-0b9496cf-f166-49ce-bc89-5114f6d173ce
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58755646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash
_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_read_word_sweep_serr.58755646
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.4195601961
Short name T700
Test name
Test status
Simulation time 728364100 ps
CPU time 131.04 seconds
Started Apr 30 02:27:09 PM PDT 24
Finished Apr 30 02:29:21 PM PDT 24
Peak memory 281220 kb
Host smart-d4dec157-b6c6-458a-8e54-288d1203e6d8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195601961 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_ro.4195601961
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.1907314764
Short name T946
Test name
Test status
Simulation time 3098187800 ps
CPU time 168.33 seconds
Started Apr 30 02:27:16 PM PDT 24
Finished Apr 30 02:30:05 PM PDT 24
Peak memory 283540 kb
Host smart-0aa76854-6e80-40dc-a585-8175782e3136
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1907314764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.1907314764
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.1240465321
Short name T52
Test name
Test status
Simulation time 747729000 ps
CPU time 167.36 seconds
Started Apr 30 02:27:10 PM PDT 24
Finished Apr 30 02:29:58 PM PDT 24
Peak memory 289276 kb
Host smart-0922927d-a1d3-43f4-8fd5-8dd4f835cb76
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240465321 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.1240465321
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.3887065509
Short name T844
Test name
Test status
Simulation time 4082006400 ps
CPU time 628.35 seconds
Started Apr 30 02:27:09 PM PDT 24
Finished Apr 30 02:37:39 PM PDT 24
Peak memory 313892 kb
Host smart-67c64aab-a5f9-4395-a14c-f7e675dda438
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887065509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.flash_ctrl_rw.3887065509
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.1440718558
Short name T11
Test name
Test status
Simulation time 41570200 ps
CPU time 32.46 seconds
Started Apr 30 02:27:19 PM PDT 24
Finished Apr 30 02:27:52 PM PDT 24
Peak memory 274508 kb
Host smart-51a50231-8568-486c-bb27-aecd3d8a683f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440718558 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.1440718558
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.2517432096
Short name T859
Test name
Test status
Simulation time 31651600 ps
CPU time 76.1 seconds
Started Apr 30 02:27:04 PM PDT 24
Finished Apr 30 02:28:21 PM PDT 24
Peak memory 274648 kb
Host smart-cd5f8e5d-2d71-4fbe-9a49-e8dc0d46a1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517432096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.2517432096
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.3896774448
Short name T87
Test name
Test status
Simulation time 56618100 ps
CPU time 25.95 seconds
Started Apr 30 02:27:00 PM PDT 24
Finished Apr 30 02:27:27 PM PDT 24
Peak memory 258268 kb
Host smart-934f83f7-e594-4586-881a-7fa553f14e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896774448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.3896774448
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.4231914390
Short name T460
Test name
Test status
Simulation time 573013800 ps
CPU time 555.75 seconds
Started Apr 30 02:27:19 PM PDT 24
Finished Apr 30 02:36:35 PM PDT 24
Peak memory 278792 kb
Host smart-2546e126-fb47-4652-a714-ad2d39825311
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231914390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.4231914390
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.4221911532
Short name T779
Test name
Test status
Simulation time 80842100 ps
CPU time 26.92 seconds
Started Apr 30 02:27:20 PM PDT 24
Finished Apr 30 02:27:48 PM PDT 24
Peak memory 261144 kb
Host smart-d2815d17-5218-4fa6-bfcb-754d67136311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221911532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.4221911532
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.588155523
Short name T775
Test name
Test status
Simulation time 5717431200 ps
CPU time 258.86 seconds
Started Apr 30 02:27:09 PM PDT 24
Finished Apr 30 02:31:29 PM PDT 24
Peak memory 264704 kb
Host smart-6795423d-b27f-43a8-8ea7-47e3a3ce3a49
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588155523 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_wo.588155523
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.2500703343
Short name T46
Test name
Test status
Simulation time 85822400 ps
CPU time 15.37 seconds
Started Apr 30 02:27:18 PM PDT 24
Finished Apr 30 02:27:34 PM PDT 24
Peak memory 264640 kb
Host smart-d3f7bbe7-478d-45b9-bc81-cfaf39f23560
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500703343 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.2500703343
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.2168298284
Short name T476
Test name
Test status
Simulation time 131643000 ps
CPU time 14.09 seconds
Started Apr 30 02:32:11 PM PDT 24
Finished Apr 30 02:32:32 PM PDT 24
Peak memory 257704 kb
Host smart-51b6bc86-9e9e-4f16-ac10-dce0bdc213f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168298284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
2168298284
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.1674975590
Short name T794
Test name
Test status
Simulation time 16570900 ps
CPU time 22.21 seconds
Started Apr 30 02:32:10 PM PDT 24
Finished Apr 30 02:32:40 PM PDT 24
Peak memory 272980 kb
Host smart-b4c6969e-c206-4665-907d-16e51af2d3a7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674975590 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.1674975590
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.2744050597
Short name T843
Test name
Test status
Simulation time 2832132000 ps
CPU time 55.15 seconds
Started Apr 30 02:32:05 PM PDT 24
Finished Apr 30 02:33:10 PM PDT 24
Peak memory 261920 kb
Host smart-59bb1883-806f-4ee3-8dee-df0804673999
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744050597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_
hw_sec_otp.2744050597
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.3934241369
Short name T306
Test name
Test status
Simulation time 1295298200 ps
CPU time 166.94 seconds
Started Apr 30 02:32:11 PM PDT 24
Finished Apr 30 02:35:04 PM PDT 24
Peak memory 293704 kb
Host smart-c136a3be-c33e-4a57-b1c8-4b0c93462f24
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934241369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_intr_rd.3934241369
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.2532010575
Short name T291
Test name
Test status
Simulation time 40919700 ps
CPU time 136.84 seconds
Started Apr 30 02:32:03 PM PDT 24
Finished Apr 30 02:34:31 PM PDT 24
Peak memory 259336 kb
Host smart-f7823d93-1804-4e2e-be1d-d13085359f6d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532010575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.2532010575
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.2969978134
Short name T808
Test name
Test status
Simulation time 97572700 ps
CPU time 102.29 seconds
Started Apr 30 02:32:07 PM PDT 24
Finished Apr 30 02:33:59 PM PDT 24
Peak memory 274936 kb
Host smart-67fcc330-7c11-49f9-bdb6-9320b1d9addf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969978134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.2969978134
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.3970614109
Short name T780
Test name
Test status
Simulation time 50009000 ps
CPU time 13.57 seconds
Started Apr 30 02:32:28 PM PDT 24
Finished Apr 30 02:32:43 PM PDT 24
Peak memory 257916 kb
Host smart-cd83137f-a002-46e7-9cd7-4c7130411111
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970614109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
3970614109
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.2881117210
Short name T423
Test name
Test status
Simulation time 13893200 ps
CPU time 13.26 seconds
Started Apr 30 02:32:25 PM PDT 24
Finished Apr 30 02:32:40 PM PDT 24
Peak memory 275276 kb
Host smart-75c62012-a6bf-4787-a9c7-3fba251e747b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881117210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.2881117210
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.1907139390
Short name T40
Test name
Test status
Simulation time 19432000 ps
CPU time 20.94 seconds
Started Apr 30 02:32:28 PM PDT 24
Finished Apr 30 02:32:50 PM PDT 24
Peak memory 280144 kb
Host smart-8e4870ec-a116-4063-88c3-a63c2da21048
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907139390 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.1907139390
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.2851015658
Short name T54
Test name
Test status
Simulation time 10869238700 ps
CPU time 192.88 seconds
Started Apr 30 02:32:11 PM PDT 24
Finished Apr 30 02:35:30 PM PDT 24
Peak memory 262200 kb
Host smart-193cde0d-173a-45c1-826e-b93549bd5ba4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851015658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_
hw_sec_otp.2851015658
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.1729102822
Short name T304
Test name
Test status
Simulation time 4930815500 ps
CPU time 164.79 seconds
Started Apr 30 02:32:20 PM PDT 24
Finished Apr 30 02:35:05 PM PDT 24
Peak memory 293016 kb
Host smart-02875335-e68d-42d6-8f8e-3616b84ec8ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729102822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla
sh_ctrl_intr_rd.1729102822
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.3744579976
Short name T533
Test name
Test status
Simulation time 13675847000 ps
CPU time 196.74 seconds
Started Apr 30 02:32:20 PM PDT 24
Finished Apr 30 02:35:37 PM PDT 24
Peak memory 289920 kb
Host smart-88111519-e969-497e-988f-9152aede47ca
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744579976 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.3744579976
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.1148172565
Short name T895
Test name
Test status
Simulation time 163577800 ps
CPU time 147.53 seconds
Started Apr 30 02:32:13 PM PDT 24
Finished Apr 30 02:34:46 PM PDT 24
Peak memory 275468 kb
Host smart-5261da21-e70f-4386-93fb-950e9baedbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148172565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.1148172565
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.2407231326
Short name T767
Test name
Test status
Simulation time 55086600 ps
CPU time 13.86 seconds
Started Apr 30 02:32:33 PM PDT 24
Finished Apr 30 02:32:47 PM PDT 24
Peak memory 264568 kb
Host smart-52e905f8-f2af-41b4-8453-25dfd53a7bcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407231326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.
2407231326
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.4231826470
Short name T623
Test name
Test status
Simulation time 24422700 ps
CPU time 16.19 seconds
Started Apr 30 02:32:30 PM PDT 24
Finished Apr 30 02:32:46 PM PDT 24
Peak memory 275212 kb
Host smart-bd831104-df41-4be7-9c17-da53a5f2d7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231826470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.4231826470
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.2159465558
Short name T765
Test name
Test status
Simulation time 2015020300 ps
CPU time 176.85 seconds
Started Apr 30 02:32:25 PM PDT 24
Finished Apr 30 02:35:23 PM PDT 24
Peak memory 258692 kb
Host smart-c95d74c4-1192-46fc-880e-3111e7b1a192
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159465558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_
hw_sec_otp.2159465558
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.896545979
Short name T181
Test name
Test status
Simulation time 13813811900 ps
CPU time 182.32 seconds
Started Apr 30 02:32:30 PM PDT 24
Finished Apr 30 02:35:33 PM PDT 24
Peak memory 292440 kb
Host smart-e84737a6-151c-4eca-8b6c-57c509af8a23
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896545979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flas
h_ctrl_intr_rd.896545979
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.2344437986
Short name T106
Test name
Test status
Simulation time 81438300 ps
CPU time 136.42 seconds
Started Apr 30 02:32:31 PM PDT 24
Finished Apr 30 02:34:48 PM PDT 24
Peak memory 259072 kb
Host smart-2bdc4b39-7309-4b0e-9c2e-838bb627b45b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344437986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o
tp_reset.2344437986
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.1134951926
Short name T810
Test name
Test status
Simulation time 8435915000 ps
CPU time 77.13 seconds
Started Apr 30 02:32:33 PM PDT 24
Finished Apr 30 02:33:50 PM PDT 24
Peak memory 263832 kb
Host smart-43245a34-7714-4d3e-87b3-51d82c187791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134951926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.1134951926
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.4078319349
Short name T605
Test name
Test status
Simulation time 27810100 ps
CPU time 122.05 seconds
Started Apr 30 02:32:25 PM PDT 24
Finished Apr 30 02:34:28 PM PDT 24
Peak memory 274936 kb
Host smart-f1734c1c-dd5f-4b3e-b7f7-21e4bfe4abf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078319349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.4078319349
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.1383605809
Short name T389
Test name
Test status
Simulation time 33935600 ps
CPU time 13.5 seconds
Started Apr 30 02:32:40 PM PDT 24
Finished Apr 30 02:32:54 PM PDT 24
Peak memory 257656 kb
Host smart-163826d2-c97b-4a78-a1b4-b2f08fda8818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383605809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.
1383605809
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.3317345475
Short name T25
Test name
Test status
Simulation time 25907000 ps
CPU time 16.09 seconds
Started Apr 30 02:32:41 PM PDT 24
Finished Apr 30 02:32:57 PM PDT 24
Peak memory 274700 kb
Host smart-587a9104-3b8c-4830-80b4-f5839447d099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317345475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.3317345475
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.2950401705
Short name T894
Test name
Test status
Simulation time 90003300 ps
CPU time 22.39 seconds
Started Apr 30 02:32:42 PM PDT 24
Finished Apr 30 02:33:05 PM PDT 24
Peak memory 273092 kb
Host smart-52d43345-47b1-42ba-a194-21a24e79869f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950401705 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.2950401705
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.68035346
Short name T419
Test name
Test status
Simulation time 8043996000 ps
CPU time 43.71 seconds
Started Apr 30 02:32:31 PM PDT 24
Finished Apr 30 02:33:16 PM PDT 24
Peak memory 261956 kb
Host smart-1ee73714-330b-43c7-8d7c-a6058ae88f60
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68035346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_hw
_sec_otp.68035346
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.3361220451
Short name T309
Test name
Test status
Simulation time 1801924800 ps
CPU time 164.14 seconds
Started Apr 30 02:32:32 PM PDT 24
Finished Apr 30 02:35:17 PM PDT 24
Peak memory 292540 kb
Host smart-b9f4d74c-a3f8-422a-9fa6-c8edb9ab418e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361220451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla
sh_ctrl_intr_rd.3361220451
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2973967136
Short name T943
Test name
Test status
Simulation time 7360408400 ps
CPU time 188.53 seconds
Started Apr 30 02:32:30 PM PDT 24
Finished Apr 30 02:35:39 PM PDT 24
Peak memory 284192 kb
Host smart-2e235986-faab-44fe-9a29-c81a8989eef4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973967136 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.2973967136
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.2239257848
Short name T865
Test name
Test status
Simulation time 37905000 ps
CPU time 109.68 seconds
Started Apr 30 02:32:28 PM PDT 24
Finished Apr 30 02:34:18 PM PDT 24
Peak memory 260388 kb
Host smart-816cd739-3d5a-4cb1-92c7-1d50dda7f141
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239257848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o
tp_reset.2239257848
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict.4227846935
Short name T207
Test name
Test status
Simulation time 52902800 ps
CPU time 28.66 seconds
Started Apr 30 02:32:43 PM PDT 24
Finished Apr 30 02:33:12 PM PDT 24
Peak memory 265844 kb
Host smart-1b1c1c1f-4669-4abc-aada-5dec4029f7c1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227846935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fl
ash_ctrl_rw_evict.4227846935
Directory /workspace/23.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.1096455164
Short name T323
Test name
Test status
Simulation time 3224338300 ps
CPU time 67.7 seconds
Started Apr 30 02:32:43 PM PDT 24
Finished Apr 30 02:33:51 PM PDT 24
Peak memory 262568 kb
Host smart-db7cb072-e6f3-445a-88df-9e50354a3b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096455164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.1096455164
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.436747302
Short name T786
Test name
Test status
Simulation time 59636900 ps
CPU time 52.64 seconds
Started Apr 30 02:32:31 PM PDT 24
Finished Apr 30 02:33:24 PM PDT 24
Peak memory 269672 kb
Host smart-1fca4e4d-8bab-456a-a3bc-671fbb7d3c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436747302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.436747302
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.2365614000
Short name T542
Test name
Test status
Simulation time 32733300 ps
CPU time 13.87 seconds
Started Apr 30 02:32:45 PM PDT 24
Finished Apr 30 02:32:59 PM PDT 24
Peak memory 257640 kb
Host smart-1780211f-1398-4a35-8e89-2894090b8526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365614000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.
2365614000
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.2773620335
Short name T681
Test name
Test status
Simulation time 23009300 ps
CPU time 15.93 seconds
Started Apr 30 02:32:46 PM PDT 24
Finished Apr 30 02:33:02 PM PDT 24
Peak memory 275308 kb
Host smart-62e24250-37a1-4b8c-a402-90b11dce3d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773620335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.2773620335
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.691652547
Short name T276
Test name
Test status
Simulation time 13541600 ps
CPU time 23.1 seconds
Started Apr 30 02:32:47 PM PDT 24
Finished Apr 30 02:33:10 PM PDT 24
Peak memory 273000 kb
Host smart-675a349c-9eec-476e-baae-841670de48c1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691652547 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.691652547
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.1996093946
Short name T580
Test name
Test status
Simulation time 1960517000 ps
CPU time 68.27 seconds
Started Apr 30 02:32:43 PM PDT 24
Finished Apr 30 02:33:52 PM PDT 24
Peak memory 261900 kb
Host smart-a7223bb8-1d31-46f9-8fed-60a819f6abe6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996093946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.1996093946
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.368416329
Short name T640
Test name
Test status
Simulation time 1334305600 ps
CPU time 164.53 seconds
Started Apr 30 02:32:41 PM PDT 24
Finished Apr 30 02:35:26 PM PDT 24
Peak memory 290560 kb
Host smart-c09e3733-1fa7-4701-a2ee-8de9d445272e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368416329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flas
h_ctrl_intr_rd.368416329
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.3246103551
Short name T840
Test name
Test status
Simulation time 15362122800 ps
CPU time 200.26 seconds
Started Apr 30 02:32:47 PM PDT 24
Finished Apr 30 02:36:08 PM PDT 24
Peak memory 289252 kb
Host smart-679152a7-7a76-42de-841a-2116bb60fae2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246103551 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.3246103551
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.698391540
Short name T459
Test name
Test status
Simulation time 228317000 ps
CPU time 109.13 seconds
Started Apr 30 02:32:40 PM PDT 24
Finished Apr 30 02:34:30 PM PDT 24
Peak memory 263120 kb
Host smart-6bf7e184-ad92-4134-b11f-4eb463723369
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698391540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_ot
p_reset.698391540
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.2970273837
Short name T884
Test name
Test status
Simulation time 3743522400 ps
CPU time 72.37 seconds
Started Apr 30 02:32:47 PM PDT 24
Finished Apr 30 02:34:00 PM PDT 24
Peak memory 261768 kb
Host smart-7eb245ca-2d84-4df5-b06e-b7f5ba1cf528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970273837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.2970273837
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.1291131870
Short name T939
Test name
Test status
Simulation time 21156700 ps
CPU time 100.3 seconds
Started Apr 30 02:32:41 PM PDT 24
Finished Apr 30 02:34:22 PM PDT 24
Peak memory 275656 kb
Host smart-9019501a-ef28-48bd-80a3-466ac3796ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291131870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.1291131870
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.251739267
Short name T436
Test name
Test status
Simulation time 55536800 ps
CPU time 14.01 seconds
Started Apr 30 02:32:53 PM PDT 24
Finished Apr 30 02:33:07 PM PDT 24
Peak memory 257648 kb
Host smart-d888ce3f-1838-41f9-b643-921dc4c320cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251739267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.251739267
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.4016911512
Short name T588
Test name
Test status
Simulation time 24006800 ps
CPU time 15.99 seconds
Started Apr 30 02:32:54 PM PDT 24
Finished Apr 30 02:33:10 PM PDT 24
Peak memory 275256 kb
Host smart-ac9d126c-e27f-41e2-adef-3e49d11de0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016911512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.4016911512
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.1872417343
Short name T398
Test name
Test status
Simulation time 16362900 ps
CPU time 22.06 seconds
Started Apr 30 02:32:55 PM PDT 24
Finished Apr 30 02:33:17 PM PDT 24
Peak memory 279992 kb
Host smart-262c8fa8-2dd8-44de-b6f0-cf58985ff522
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872417343 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.1872417343
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.94371235
Short name T936
Test name
Test status
Simulation time 1789673000 ps
CPU time 59.32 seconds
Started Apr 30 02:32:47 PM PDT 24
Finished Apr 30 02:33:47 PM PDT 24
Peak memory 262068 kb
Host smart-79e5d4a9-9961-4220-9d2b-3f0328fe913c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94371235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_hw
_sec_otp.94371235
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.23673664
Short name T178
Test name
Test status
Simulation time 11294933100 ps
CPU time 177.55 seconds
Started Apr 30 02:32:46 PM PDT 24
Finished Apr 30 02:35:44 PM PDT 24
Peak memory 293304 kb
Host smart-080fe862-f1ab-4110-bfe1-e7dc2d8467af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23673664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash
_ctrl_intr_rd.23673664
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.2569798384
Short name T612
Test name
Test status
Simulation time 16557412700 ps
CPU time 193.61 seconds
Started Apr 30 02:32:47 PM PDT 24
Finished Apr 30 02:36:02 PM PDT 24
Peak memory 290364 kb
Host smart-41fd19c7-437f-4a82-94ac-249b56ebede3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569798384 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.2569798384
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.1289616538
Short name T866
Test name
Test status
Simulation time 95141900 ps
CPU time 130.46 seconds
Started Apr 30 02:32:46 PM PDT 24
Finished Apr 30 02:34:57 PM PDT 24
Peak memory 260320 kb
Host smart-89ebe296-f367-4fb2-9883-2da623ac2427
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289616538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.1289616538
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.558419896
Short name T596
Test name
Test status
Simulation time 3791626000 ps
CPU time 63.41 seconds
Started Apr 30 02:32:51 PM PDT 24
Finished Apr 30 02:33:55 PM PDT 24
Peak memory 262624 kb
Host smart-f76876c7-c972-4deb-a5e7-726ba1d01f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558419896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.558419896
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.1254420502
Short name T872
Test name
Test status
Simulation time 47429200 ps
CPU time 118.91 seconds
Started Apr 30 02:32:48 PM PDT 24
Finished Apr 30 02:34:47 PM PDT 24
Peak memory 274948 kb
Host smart-6fb75249-0901-4b07-be57-276bd798288f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254420502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.1254420502
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.1670228508
Short name T824
Test name
Test status
Simulation time 129521800 ps
CPU time 14.21 seconds
Started Apr 30 02:33:00 PM PDT 24
Finished Apr 30 02:33:15 PM PDT 24
Peak memory 257708 kb
Host smart-80395add-80d4-4d72-b2cb-751d7a1b2aaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670228508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.
1670228508
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.4156362198
Short name T447
Test name
Test status
Simulation time 56068100 ps
CPU time 16.08 seconds
Started Apr 30 02:32:59 PM PDT 24
Finished Apr 30 02:33:15 PM PDT 24
Peak memory 274708 kb
Host smart-5c9f856d-91bf-4814-bf69-ea62f6ffd6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156362198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.4156362198
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.2948197611
Short name T270
Test name
Test status
Simulation time 11116000 ps
CPU time 22.14 seconds
Started Apr 30 02:33:00 PM PDT 24
Finished Apr 30 02:33:22 PM PDT 24
Peak memory 272960 kb
Host smart-a1144df8-2e05-467b-b163-23c1d88833f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948197611 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.2948197611
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.552991866
Short name T606
Test name
Test status
Simulation time 7720278300 ps
CPU time 152.84 seconds
Started Apr 30 02:32:56 PM PDT 24
Finished Apr 30 02:35:29 PM PDT 24
Peak memory 262000 kb
Host smart-991fca99-1ada-4080-a4b7-bbe10dedfa4e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552991866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_h
w_sec_otp.552991866
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.614949974
Short name T299
Test name
Test status
Simulation time 1641358600 ps
CPU time 184.86 seconds
Started Apr 30 02:32:52 PM PDT 24
Finished Apr 30 02:35:57 PM PDT 24
Peak memory 293340 kb
Host smart-3a21ce1e-90c8-4ec1-a154-ccb7f3ee0b57
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614949974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flas
h_ctrl_intr_rd.614949974
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.180682293
Short name T523
Test name
Test status
Simulation time 11852477200 ps
CPU time 226.19 seconds
Started Apr 30 02:32:53 PM PDT 24
Finished Apr 30 02:36:40 PM PDT 24
Peak memory 284292 kb
Host smart-7b299163-85ca-4152-a5b1-c3fadb0dd24a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180682293 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.180682293
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.3337372671
Short name T438
Test name
Test status
Simulation time 44788300 ps
CPU time 128.96 seconds
Started Apr 30 02:32:52 PM PDT 24
Finished Apr 30 02:35:01 PM PDT 24
Peak memory 259280 kb
Host smart-42d90468-6b87-44ab-822b-3565cf9c569c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337372671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o
tp_reset.3337372671
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.2540311196
Short name T82
Test name
Test status
Simulation time 122086700 ps
CPU time 32.15 seconds
Started Apr 30 02:32:55 PM PDT 24
Finished Apr 30 02:33:28 PM PDT 24
Peak memory 274384 kb
Host smart-c9265454-30a1-4025-b6ad-4d91418d7e6f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540311196 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.2540311196
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.4165924720
Short name T411
Test name
Test status
Simulation time 10623057000 ps
CPU time 85.12 seconds
Started Apr 30 02:33:02 PM PDT 24
Finished Apr 30 02:34:27 PM PDT 24
Peak memory 261988 kb
Host smart-f38ec471-5772-42d5-9fcb-11744d1f8446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165924720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.4165924720
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.2272717626
Short name T839
Test name
Test status
Simulation time 32427400 ps
CPU time 146.66 seconds
Started Apr 30 02:32:54 PM PDT 24
Finished Apr 30 02:35:21 PM PDT 24
Peak memory 272596 kb
Host smart-238ce522-8499-4b2e-bf04-14c4a6ca43a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272717626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.2272717626
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.4146860677
Short name T441
Test name
Test status
Simulation time 91377500 ps
CPU time 14.02 seconds
Started Apr 30 02:33:01 PM PDT 24
Finished Apr 30 02:33:15 PM PDT 24
Peak memory 257652 kb
Host smart-8b5c3a4c-b147-4a21-93d7-e8f3674b26a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146860677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.
4146860677
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.693580065
Short name T449
Test name
Test status
Simulation time 109662900 ps
CPU time 15.5 seconds
Started Apr 30 02:32:59 PM PDT 24
Finished Apr 30 02:33:15 PM PDT 24
Peak memory 275176 kb
Host smart-de548263-a782-40b4-9621-15de7258dbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693580065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.693580065
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.3174169095
Short name T384
Test name
Test status
Simulation time 16148700 ps
CPU time 21.59 seconds
Started Apr 30 02:33:00 PM PDT 24
Finished Apr 30 02:33:23 PM PDT 24
Peak memory 280172 kb
Host smart-2ca09c8d-8f67-4bae-bee6-340a8cc70826
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174169095 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.3174169095
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.1923964906
Short name T524
Test name
Test status
Simulation time 10683453200 ps
CPU time 117.49 seconds
Started Apr 30 02:32:58 PM PDT 24
Finished Apr 30 02:34:56 PM PDT 24
Peak memory 262104 kb
Host smart-167ca9de-a328-4f2e-ba54-f400793e7c85
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923964906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_
hw_sec_otp.1923964906
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.2755129523
Short name T298
Test name
Test status
Simulation time 1246835700 ps
CPU time 165.22 seconds
Started Apr 30 02:33:01 PM PDT 24
Finished Apr 30 02:35:47 PM PDT 24
Peak memory 293532 kb
Host smart-90ac5952-9910-4eb1-b531-d655ef35cc48
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755129523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_intr_rd.2755129523
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1752952163
Short name T925
Test name
Test status
Simulation time 37570411800 ps
CPU time 257.07 seconds
Started Apr 30 02:32:58 PM PDT 24
Finished Apr 30 02:37:16 PM PDT 24
Peak memory 290272 kb
Host smart-a0f8cd19-4549-4a48-aca7-cb1df61ca666
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752952163 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.1752952163
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.1140531895
Short name T837
Test name
Test status
Simulation time 73316500 ps
CPU time 133.1 seconds
Started Apr 30 02:33:00 PM PDT 24
Finished Apr 30 02:35:13 PM PDT 24
Peak memory 259256 kb
Host smart-6100c81c-c3f1-4c79-8114-ffa3f1de8cc2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140531895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o
tp_reset.1140531895
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.1523787812
Short name T403
Test name
Test status
Simulation time 6562005100 ps
CPU time 70.01 seconds
Started Apr 30 02:33:00 PM PDT 24
Finished Apr 30 02:34:10 PM PDT 24
Peak memory 261712 kb
Host smart-a269b213-96fb-4740-b239-778180da4a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523787812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.1523787812
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.3628677042
Short name T497
Test name
Test status
Simulation time 25595000 ps
CPU time 76.07 seconds
Started Apr 30 02:33:00 PM PDT 24
Finished Apr 30 02:34:16 PM PDT 24
Peak memory 277992 kb
Host smart-67a7408c-8e30-457a-b08b-a24e8f781e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628677042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.3628677042
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.3785895969
Short name T841
Test name
Test status
Simulation time 45444100 ps
CPU time 13.53 seconds
Started Apr 30 02:33:09 PM PDT 24
Finished Apr 30 02:33:23 PM PDT 24
Peak memory 257632 kb
Host smart-7b85eed5-cfb2-4fb4-9c93-809c3c7d25d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785895969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.
3785895969
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.603304345
Short name T647
Test name
Test status
Simulation time 125085100 ps
CPU time 15.67 seconds
Started Apr 30 02:33:09 PM PDT 24
Finished Apr 30 02:33:25 PM PDT 24
Peak memory 274820 kb
Host smart-6fa3c2dd-c512-4197-9793-243e895140ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603304345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.603304345
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.2367263003
Short name T281
Test name
Test status
Simulation time 1557204900 ps
CPU time 75.96 seconds
Started Apr 30 02:32:59 PM PDT 24
Finished Apr 30 02:34:15 PM PDT 24
Peak memory 262028 kb
Host smart-9eae8efb-dd6b-423b-89b1-c0202ce8c4f7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367263003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.2367263003
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd.476715385
Short name T858
Test name
Test status
Simulation time 2575059200 ps
CPU time 164.48 seconds
Started Apr 30 02:33:00 PM PDT 24
Finished Apr 30 02:35:45 PM PDT 24
Peak memory 293476 kb
Host smart-1bcd6a22-c916-46e4-8748-4a1225b06c91
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476715385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flas
h_ctrl_intr_rd.476715385
Directory /workspace/28.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.314644511
Short name T275
Test name
Test status
Simulation time 66803143700 ps
CPU time 235.1 seconds
Started Apr 30 02:33:10 PM PDT 24
Finished Apr 30 02:37:05 PM PDT 24
Peak memory 290308 kb
Host smart-6509638a-3304-4b38-b60a-7b7eb599f5e7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314644511 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.314644511
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.234412136
Short name T699
Test name
Test status
Simulation time 71951400 ps
CPU time 132.58 seconds
Started Apr 30 02:33:01 PM PDT 24
Finished Apr 30 02:35:14 PM PDT 24
Peak memory 259260 kb
Host smart-4e53e090-2805-474d-8a6b-2d1fe72bf2a0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234412136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_ot
p_reset.234412136
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict.905782520
Short name T187
Test name
Test status
Simulation time 30467000 ps
CPU time 31.91 seconds
Started Apr 30 02:33:07 PM PDT 24
Finished Apr 30 02:33:40 PM PDT 24
Peak memory 274044 kb
Host smart-81552385-92bf-48ab-a49c-a6e8ea959066
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905782520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla
sh_ctrl_rw_evict.905782520
Directory /workspace/28.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.31211176
Short name T465
Test name
Test status
Simulation time 5681554900 ps
CPU time 65.52 seconds
Started Apr 30 02:33:08 PM PDT 24
Finished Apr 30 02:34:14 PM PDT 24
Peak memory 261876 kb
Host smart-d94a8dc5-9f2d-40e0-be7d-4711857cd915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31211176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.31211176
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.887895905
Short name T833
Test name
Test status
Simulation time 704893800 ps
CPU time 121.09 seconds
Started Apr 30 02:32:59 PM PDT 24
Finished Apr 30 02:35:01 PM PDT 24
Peak memory 280128 kb
Host smart-08edbd6b-abff-4128-a938-396e4c4f31bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887895905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.887895905
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.1161881653
Short name T932
Test name
Test status
Simulation time 62752200 ps
CPU time 13.97 seconds
Started Apr 30 02:33:26 PM PDT 24
Finished Apr 30 02:33:40 PM PDT 24
Peak memory 264516 kb
Host smart-11279c05-7107-4f53-b51c-b9626bd216d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161881653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
1161881653
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.2602844614
Short name T935
Test name
Test status
Simulation time 17101100 ps
CPU time 13.82 seconds
Started Apr 30 02:33:26 PM PDT 24
Finished Apr 30 02:33:40 PM PDT 24
Peak memory 275328 kb
Host smart-1e4a2150-aaaa-4371-bbc0-343378b5c80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602844614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.2602844614
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.2640920273
Short name T282
Test name
Test status
Simulation time 3028523100 ps
CPU time 246.68 seconds
Started Apr 30 02:33:10 PM PDT 24
Finished Apr 30 02:37:17 PM PDT 24
Peak memory 261988 kb
Host smart-5462312e-9e0b-41d8-8b01-21134cbb96c0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640920273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.2640920273
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.2600842523
Short name T703
Test name
Test status
Simulation time 7124826100 ps
CPU time 165.31 seconds
Started Apr 30 02:33:26 PM PDT 24
Finished Apr 30 02:36:12 PM PDT 24
Peak memory 292452 kb
Host smart-bcc5d834-811e-4316-b71d-1dfa0940d54e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600842523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.2600842523
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.717012395
Short name T86
Test name
Test status
Simulation time 17972790300 ps
CPU time 201.07 seconds
Started Apr 30 02:33:25 PM PDT 24
Finished Apr 30 02:36:46 PM PDT 24
Peak memory 290400 kb
Host smart-55668fb1-9733-4483-93e1-731d9d537c72
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717012395 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.717012395
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.2832840781
Short name T575
Test name
Test status
Simulation time 167720500 ps
CPU time 129.9 seconds
Started Apr 30 02:33:24 PM PDT 24
Finished Apr 30 02:35:34 PM PDT 24
Peak memory 259336 kb
Host smart-d72e9c1f-f354-44e7-b45f-0d63e81c63aa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832840781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o
tp_reset.2832840781
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.2693810113
Short name T933
Test name
Test status
Simulation time 6481586400 ps
CPU time 70.1 seconds
Started Apr 30 02:33:26 PM PDT 24
Finished Apr 30 02:34:36 PM PDT 24
Peak memory 262632 kb
Host smart-fd5e9329-c71c-44c0-9655-7e70f0f9031a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693810113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.2693810113
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.2103346118
Short name T705
Test name
Test status
Simulation time 25384100 ps
CPU time 98.2 seconds
Started Apr 30 02:33:08 PM PDT 24
Finished Apr 30 02:34:47 PM PDT 24
Peak memory 275820 kb
Host smart-4c967d53-9d1f-4b24-9aed-6bd824656ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103346118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.2103346118
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.366685272
Short name T295
Test name
Test status
Simulation time 279834500 ps
CPU time 13.9 seconds
Started Apr 30 02:27:48 PM PDT 24
Finished Apr 30 02:28:03 PM PDT 24
Peak memory 257732 kb
Host smart-0ff7d511-5d0d-4c74-9df1-5c24eadfa01e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366685272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.366685272
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.3447422074
Short name T381
Test name
Test status
Simulation time 35049500 ps
CPU time 13.82 seconds
Started Apr 30 02:27:43 PM PDT 24
Finished Apr 30 02:27:58 PM PDT 24
Peak memory 261184 kb
Host smart-0e80d84f-bcae-41a5-a0ef-906750b67e89
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447422074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.flash_ctrl_config_regwen.3447422074
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.4204357573
Short name T926
Test name
Test status
Simulation time 13894200 ps
CPU time 15.52 seconds
Started Apr 30 02:27:43 PM PDT 24
Finished Apr 30 02:27:59 PM PDT 24
Peak memory 274760 kb
Host smart-f2c4f4c1-6a9f-4725-bd82-3719687447c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204357573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.4204357573
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.2562757901
Short name T893
Test name
Test status
Simulation time 28219300 ps
CPU time 22.81 seconds
Started Apr 30 02:27:35 PM PDT 24
Finished Apr 30 02:27:58 PM PDT 24
Peak memory 273040 kb
Host smart-f7f9b6b3-eb48-417c-9007-37550207c463
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562757901 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.2562757901
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.779933919
Short name T166
Test name
Test status
Simulation time 2046590700 ps
CPU time 390.63 seconds
Started Apr 30 02:27:22 PM PDT 24
Finished Apr 30 02:33:54 PM PDT 24
Peak memory 260396 kb
Host smart-c2018886-e529-4c53-92fd-7de54ecfb134
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=779933919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.779933919
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.255017952
Short name T904
Test name
Test status
Simulation time 1780174500 ps
CPU time 2210.09 seconds
Started Apr 30 02:27:30 PM PDT 24
Finished Apr 30 03:04:21 PM PDT 24
Peak memory 261968 kb
Host smart-d581cabf-66e0-4248-903e-a2c965ff9233
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255017952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erro
r_mp.255017952
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.3993584598
Short name T38
Test name
Test status
Simulation time 2520757700 ps
CPU time 2540.83 seconds
Started Apr 30 02:27:30 PM PDT 24
Finished Apr 30 03:09:51 PM PDT 24
Peak memory 264040 kb
Host smart-0b4fb4b3-182b-4bc0-8d75-46e0f711e948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993584598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.3993584598
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.1284602851
Short name T929
Test name
Test status
Simulation time 2410435600 ps
CPU time 905.43 seconds
Started Apr 30 02:27:29 PM PDT 24
Finished Apr 30 02:42:35 PM PDT 24
Peak memory 272752 kb
Host smart-2c083080-dc86-48b0-a423-073cfb69c7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284602851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.1284602851
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.4207738616
Short name T94
Test name
Test status
Simulation time 171524400 ps
CPU time 23.6 seconds
Started Apr 30 02:27:29 PM PDT 24
Finished Apr 30 02:27:53 PM PDT 24
Peak memory 261340 kb
Host smart-1ad2e826-2572-45cc-879d-10a43ebbae56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207738616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.4207738616
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.4132752766
Short name T154
Test name
Test status
Simulation time 81024828800 ps
CPU time 2514.92 seconds
Started Apr 30 02:27:28 PM PDT 24
Finished Apr 30 03:09:24 PM PDT 24
Peak memory 264420 kb
Host smart-0f6dcbb4-f9b2-43ee-87e9-32ea6ab056bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132752766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_full_mem_access.4132752766
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.1541151669
Short name T196
Test name
Test status
Simulation time 348432489100 ps
CPU time 2473.36 seconds
Started Apr 30 02:27:24 PM PDT 24
Finished Apr 30 03:08:38 PM PDT 24
Peak memory 264544 kb
Host smart-63ec1c2d-c142-4c53-89b2-5c08f58be537
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541151669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.1541151669
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.1614458097
Short name T679
Test name
Test status
Simulation time 43782900 ps
CPU time 80.71 seconds
Started Apr 30 02:27:27 PM PDT 24
Finished Apr 30 02:28:48 PM PDT 24
Peak memory 261756 kb
Host smart-16eb98e6-6e5d-4831-9671-eec64d40722c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1614458097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.1614458097
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.2789435545
Short name T787
Test name
Test status
Simulation time 10018817100 ps
CPU time 76.12 seconds
Started Apr 30 02:27:43 PM PDT 24
Finished Apr 30 02:29:00 PM PDT 24
Peak memory 314396 kb
Host smart-9b80c3ed-1ff6-4dff-aa5c-f163d4123a03
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789435545 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.2789435545
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.2085985024
Short name T205
Test name
Test status
Simulation time 33841500 ps
CPU time 13.58 seconds
Started Apr 30 02:27:43 PM PDT 24
Finished Apr 30 02:27:58 PM PDT 24
Peak memory 258712 kb
Host smart-3fe95d6f-5798-4da7-a86e-069a5e0e4119
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085985024 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.2085985024
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.2099607814
Short name T924
Test name
Test status
Simulation time 320244270100 ps
CPU time 1115.94 seconds
Started Apr 30 02:27:22 PM PDT 24
Finished Apr 30 02:45:58 PM PDT 24
Peak memory 263452 kb
Host smart-cf170aaa-06d1-4adb-87e8-ba37bb66f068
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099607814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.flash_ctrl_hw_rma_reset.2099607814
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.2743805279
Short name T551
Test name
Test status
Simulation time 9241394200 ps
CPU time 165.16 seconds
Started Apr 30 02:27:26 PM PDT 24
Finished Apr 30 02:30:12 PM PDT 24
Peak memory 261816 kb
Host smart-aef8385e-4f4d-4abd-b3d7-7e6645d37ac8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743805279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.2743805279
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.1609044001
Short name T908
Test name
Test status
Simulation time 1851982000 ps
CPU time 190.63 seconds
Started Apr 30 02:27:36 PM PDT 24
Finished Apr 30 02:30:48 PM PDT 24
Peak memory 293256 kb
Host smart-0d8ecf69-00b0-469c-9802-43e6077f70ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609044001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_intr_rd.1609044001
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.582462044
Short name T361
Test name
Test status
Simulation time 25085348900 ps
CPU time 200.07 seconds
Started Apr 30 02:27:41 PM PDT 24
Finished Apr 30 02:31:02 PM PDT 24
Peak memory 289132 kb
Host smart-8dc2c2df-d88a-4b51-bdef-d6ce8e9692a8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582462044 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.582462044
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.2881767630
Short name T91
Test name
Test status
Simulation time 4346353300 ps
CPU time 65.32 seconds
Started Apr 30 02:27:30 PM PDT 24
Finished Apr 30 02:28:36 PM PDT 24
Peak memory 259380 kb
Host smart-fe9ec42b-aa9f-4487-8b82-941af2f54a7b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881767630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.2881767630
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.4186357318
Short name T861
Test name
Test status
Simulation time 53083100 ps
CPU time 13.67 seconds
Started Apr 30 02:27:43 PM PDT 24
Finished Apr 30 02:27:57 PM PDT 24
Peak memory 264684 kb
Host smart-a792249a-24dc-4f38-a6a5-7d988b8cb2ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186357318 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.4186357318
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.2640550449
Short name T45
Test name
Test status
Simulation time 3285703900 ps
CPU time 71.86 seconds
Started Apr 30 02:27:29 PM PDT 24
Finished Apr 30 02:28:42 PM PDT 24
Peak memory 259000 kb
Host smart-e092f7dc-5126-4772-ab87-25d856b94d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640550449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.2640550449
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.3402668245
Short name T829
Test name
Test status
Simulation time 56892370700 ps
CPU time 583.24 seconds
Started Apr 30 02:27:30 PM PDT 24
Finished Apr 30 02:37:14 PM PDT 24
Peak memory 273804 kb
Host smart-20eb3865-6a62-4903-b34c-514c10d32f9c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402668245 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_mp_regions.3402668245
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.2430852822
Short name T262
Test name
Test status
Simulation time 120979600 ps
CPU time 131.86 seconds
Started Apr 30 02:27:25 PM PDT 24
Finished Apr 30 02:29:38 PM PDT 24
Peak memory 259492 kb
Host smart-574ab449-e758-4631-979a-19abcf92adb5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430852822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot
p_reset.2430852822
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.1673340702
Short name T781
Test name
Test status
Simulation time 59758600 ps
CPU time 235.79 seconds
Started Apr 30 02:27:25 PM PDT 24
Finished Apr 30 02:31:22 PM PDT 24
Peak memory 261808 kb
Host smart-f8658c68-8bb4-4cd4-b0bc-da937694c3d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1673340702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.1673340702
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.277128522
Short name T310
Test name
Test status
Simulation time 185813600 ps
CPU time 13.88 seconds
Started Apr 30 02:27:42 PM PDT 24
Finished Apr 30 02:27:57 PM PDT 24
Peak memory 262612 kb
Host smart-daa2739f-e15b-4e6a-95b3-c0915a344cd5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277128522 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.277128522
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.1461185731
Short name T707
Test name
Test status
Simulation time 757577700 ps
CPU time 895 seconds
Started Apr 30 02:27:23 PM PDT 24
Finished Apr 30 02:42:19 PM PDT 24
Peak memory 283812 kb
Host smart-39372773-944f-48d6-b53e-7b78a0f7530d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461185731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.1461185731
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.1628973103
Short name T555
Test name
Test status
Simulation time 1358427100 ps
CPU time 206.82 seconds
Started Apr 30 02:27:23 PM PDT 24
Finished Apr 30 02:30:50 PM PDT 24
Peak memory 264356 kb
Host smart-5da35d8f-3039-43ea-8ae3-ff87990cc6b9
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1628973103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.1628973103
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.3674461851
Short name T584
Test name
Test status
Simulation time 226048500 ps
CPU time 39.17 seconds
Started Apr 30 02:27:36 PM PDT 24
Finished Apr 30 02:28:16 PM PDT 24
Peak memory 266760 kb
Host smart-a5a3faa5-f4a7-4a6d-8412-ab16256950cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674461851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_re_evict.3674461851
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.2573609778
Short name T692
Test name
Test status
Simulation time 32041100 ps
CPU time 23.35 seconds
Started Apr 30 02:27:34 PM PDT 24
Finished Apr 30 02:27:59 PM PDT 24
Peak memory 264724 kb
Host smart-2d9b91ab-c0dd-4b14-adde-aa256206fc64
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573609778 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.2573609778
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.1839119931
Short name T89
Test name
Test status
Simulation time 167637500 ps
CPU time 23.46 seconds
Started Apr 30 02:27:37 PM PDT 24
Finished Apr 30 02:28:02 PM PDT 24
Peak memory 264696 kb
Host smart-56638913-89c6-42ae-94a9-707af9e89add
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839119931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_read_word_sweep_serr.1839119931
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.3396216914
Short name T944
Test name
Test status
Simulation time 800393900 ps
CPU time 139.35 seconds
Started Apr 30 02:27:35 PM PDT 24
Finished Apr 30 02:29:56 PM PDT 24
Peak memory 288772 kb
Host smart-8a201629-2c36-448b-ab41-adab3e2afe0f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396216914 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_ro.3396216914
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.2500544368
Short name T815
Test name
Test status
Simulation time 1056058000 ps
CPU time 145.63 seconds
Started Apr 30 02:27:36 PM PDT 24
Finished Apr 30 02:30:03 PM PDT 24
Peak memory 281040 kb
Host smart-cb6d593a-f5a0-45fd-bece-ec5ccd4d8903
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2500544368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.2500544368
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.3101002717
Short name T887
Test name
Test status
Simulation time 3921041100 ps
CPU time 165.97 seconds
Started Apr 30 02:27:36 PM PDT 24
Finished Apr 30 02:30:23 PM PDT 24
Peak memory 293676 kb
Host smart-d52eaafd-ae2b-465d-84ad-76ec8f79586b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101002717 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.3101002717
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.1982479010
Short name T143
Test name
Test status
Simulation time 4315747900 ps
CPU time 635.41 seconds
Started Apr 30 02:27:35 PM PDT 24
Finished Apr 30 02:38:12 PM PDT 24
Peak memory 313904 kb
Host smart-1b413f52-7531-41d5-a8a1-d3b4971abf1e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982479010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.flash_ctrl_rw.1982479010
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.2941730797
Short name T409
Test name
Test status
Simulation time 1259358500 ps
CPU time 54.76 seconds
Started Apr 30 02:27:45 PM PDT 24
Finished Apr 30 02:28:41 PM PDT 24
Peak memory 263916 kb
Host smart-2f6047a4-058c-46ec-9754-000bed9923e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941730797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.2941730797
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.544288498
Short name T516
Test name
Test status
Simulation time 53539100 ps
CPU time 73.59 seconds
Started Apr 30 02:27:22 PM PDT 24
Finished Apr 30 02:28:37 PM PDT 24
Peak memory 274240 kb
Host smart-1c637269-d4ee-4599-aa0b-9aeb328b1284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544288498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.544288498
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.3915576427
Short name T466
Test name
Test status
Simulation time 27646200 ps
CPU time 25.8 seconds
Started Apr 30 02:27:24 PM PDT 24
Finished Apr 30 02:27:50 PM PDT 24
Peak memory 258312 kb
Host smart-7402a7ef-d5a4-4f13-ab76-ab7a834651d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915576427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.3915576427
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.2130909376
Short name T215
Test name
Test status
Simulation time 678220900 ps
CPU time 736.87 seconds
Started Apr 30 02:27:44 PM PDT 24
Finished Apr 30 02:40:01 PM PDT 24
Peak memory 282300 kb
Host smart-c7754f85-f606-4360-a3f3-a8b517746e1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130909376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres
s_all.2130909376
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.3343521196
Short name T471
Test name
Test status
Simulation time 131713700 ps
CPU time 26.87 seconds
Started Apr 30 02:27:23 PM PDT 24
Finished Apr 30 02:27:51 PM PDT 24
Peak memory 260928 kb
Host smart-51595a2f-4cfa-4263-bbb6-5a39a40521b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343521196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.3343521196
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.4133418287
Short name T602
Test name
Test status
Simulation time 9709598500 ps
CPU time 227.64 seconds
Started Apr 30 02:27:31 PM PDT 24
Finished Apr 30 02:31:20 PM PDT 24
Peak memory 259076 kb
Host smart-1b775e1d-200d-42d8-909d-852a3419208e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133418287 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_wo.4133418287
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.3258174444
Short name T869
Test name
Test status
Simulation time 139937100 ps
CPU time 14 seconds
Started Apr 30 02:33:26 PM PDT 24
Finished Apr 30 02:33:41 PM PDT 24
Peak memory 257708 kb
Host smart-381d2dd1-219c-4110-ae69-80d66315ab23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258174444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.
3258174444
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.1619775524
Short name T577
Test name
Test status
Simulation time 42426400 ps
CPU time 13.16 seconds
Started Apr 30 02:33:22 PM PDT 24
Finished Apr 30 02:33:36 PM PDT 24
Peak memory 274748 kb
Host smart-3609a87f-e532-4723-adb2-211a88ab9006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619775524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.1619775524
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.3377018450
Short name T399
Test name
Test status
Simulation time 12786000 ps
CPU time 22.3 seconds
Started Apr 30 02:33:27 PM PDT 24
Finished Apr 30 02:33:50 PM PDT 24
Peak memory 264656 kb
Host smart-91e08f57-7a57-4e85-a739-e131c3048416
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377018450 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.3377018450
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.2119968551
Short name T629
Test name
Test status
Simulation time 802206600 ps
CPU time 65.66 seconds
Started Apr 30 02:33:23 PM PDT 24
Finished Apr 30 02:34:29 PM PDT 24
Peak memory 258784 kb
Host smart-7e81011d-36ec-41a4-839c-678cf506ae33
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119968551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.2119968551
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.462453848
Short name T327
Test name
Test status
Simulation time 4326895700 ps
CPU time 170.47 seconds
Started Apr 30 02:33:23 PM PDT 24
Finished Apr 30 02:36:14 PM PDT 24
Peak memory 292600 kb
Host smart-c596f4ef-fe7f-4863-9dce-93a90ecd855d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462453848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flas
h_ctrl_intr_rd.462453848
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.3285244789
Short name T702
Test name
Test status
Simulation time 17496126800 ps
CPU time 247.63 seconds
Started Apr 30 02:33:26 PM PDT 24
Finished Apr 30 02:37:35 PM PDT 24
Peak memory 284416 kb
Host smart-77a79b22-005d-4ade-a445-003a84ee1aa5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285244789 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.3285244789
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.2746665413
Short name T114
Test name
Test status
Simulation time 77205800 ps
CPU time 129.17 seconds
Started Apr 30 02:33:24 PM PDT 24
Finished Apr 30 02:35:34 PM PDT 24
Peak memory 259120 kb
Host smart-62f7ad2f-cd9c-4f09-a25a-c5221cdfd501
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746665413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.2746665413
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.3668057754
Short name T370
Test name
Test status
Simulation time 73041600 ps
CPU time 31.81 seconds
Started Apr 30 02:33:23 PM PDT 24
Finished Apr 30 02:33:55 PM PDT 24
Peak memory 275112 kb
Host smart-328d98e3-7335-4f9c-b4ff-c59cccecfa28
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668057754 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.3668057754
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.1486882150
Short name T413
Test name
Test status
Simulation time 592274400 ps
CPU time 64.43 seconds
Started Apr 30 02:33:24 PM PDT 24
Finished Apr 30 02:34:29 PM PDT 24
Peak memory 262656 kb
Host smart-514879c1-c680-4a8b-b5cb-8d9615476dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486882150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.1486882150
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.2916497470
Short name T877
Test name
Test status
Simulation time 76579700 ps
CPU time 143.61 seconds
Started Apr 30 02:33:26 PM PDT 24
Finished Apr 30 02:35:50 PM PDT 24
Peak memory 275540 kb
Host smart-e36dcd43-5e55-43ca-9777-92bb86819acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916497470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.2916497470
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.932730438
Short name T265
Test name
Test status
Simulation time 188253300 ps
CPU time 14.37 seconds
Started Apr 30 02:33:29 PM PDT 24
Finished Apr 30 02:33:43 PM PDT 24
Peak memory 257588 kb
Host smart-539a3afc-16ca-4925-a7a9-bb85311d90a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932730438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.932730438
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.3644752910
Short name T480
Test name
Test status
Simulation time 29513700 ps
CPU time 15.72 seconds
Started Apr 30 02:33:33 PM PDT 24
Finished Apr 30 02:33:49 PM PDT 24
Peak memory 274744 kb
Host smart-64206ca9-7d33-4fbb-af84-6571efc5fae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644752910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.3644752910
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.3089138036
Short name T414
Test name
Test status
Simulation time 2451984800 ps
CPU time 157.56 seconds
Started Apr 30 02:33:25 PM PDT 24
Finished Apr 30 02:36:03 PM PDT 24
Peak memory 292388 kb
Host smart-6718a5fc-30c6-4cd3-84b5-1cc46e1b30bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089138036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_intr_rd.3089138036
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.847853001
Short name T357
Test name
Test status
Simulation time 58144614800 ps
CPU time 255.05 seconds
Started Apr 30 02:33:23 PM PDT 24
Finished Apr 30 02:37:39 PM PDT 24
Peak memory 290320 kb
Host smart-0bbde773-2a36-40a0-9d4d-3004046217d2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847853001 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.847853001
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.454050735
Short name T397
Test name
Test status
Simulation time 181672800 ps
CPU time 131.35 seconds
Started Apr 30 02:33:28 PM PDT 24
Finished Apr 30 02:35:39 PM PDT 24
Peak memory 260460 kb
Host smart-fe02bd94-5050-4a42-8f58-a71dbd9df200
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454050735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_ot
p_reset.454050735
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.2004554632
Short name T614
Test name
Test status
Simulation time 1639265500 ps
CPU time 67.79 seconds
Started Apr 30 02:33:28 PM PDT 24
Finished Apr 30 02:34:36 PM PDT 24
Peak memory 261992 kb
Host smart-11740d14-58b0-41ea-bd21-6e65c30b35bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004554632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.2004554632
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.3653207296
Short name T255
Test name
Test status
Simulation time 31197400 ps
CPU time 100.2 seconds
Started Apr 30 02:33:24 PM PDT 24
Finished Apr 30 02:35:05 PM PDT 24
Peak memory 275672 kb
Host smart-3a14b51f-aa77-4eee-b018-0447db1b834a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653207296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.3653207296
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.2532089916
Short name T892
Test name
Test status
Simulation time 69430700 ps
CPU time 14.24 seconds
Started Apr 30 02:33:35 PM PDT 24
Finished Apr 30 02:33:50 PM PDT 24
Peak memory 257620 kb
Host smart-33dc21c7-5cb0-4226-8a14-e662721450cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532089916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
2532089916
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.604340994
Short name T842
Test name
Test status
Simulation time 69277000 ps
CPU time 15.86 seconds
Started Apr 30 02:33:37 PM PDT 24
Finished Apr 30 02:33:53 PM PDT 24
Peak memory 275368 kb
Host smart-06972105-59ad-4c87-ac24-6dd26906be39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604340994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.604340994
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.3155676709
Short name T39
Test name
Test status
Simulation time 10558900 ps
CPU time 21.05 seconds
Started Apr 30 02:33:35 PM PDT 24
Finished Apr 30 02:33:56 PM PDT 24
Peak memory 264752 kb
Host smart-3a91434a-17fc-4409-9fe7-15852cef9fea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155676709 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.3155676709
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.4058026129
Short name T572
Test name
Test status
Simulation time 16140477100 ps
CPU time 100.58 seconds
Started Apr 30 02:33:33 PM PDT 24
Finished Apr 30 02:35:14 PM PDT 24
Peak memory 262056 kb
Host smart-23d7fde4-ae0c-443c-93b1-724e3ee26dde
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058026129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_
hw_sec_otp.4058026129
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.1007656784
Short name T758
Test name
Test status
Simulation time 1725206100 ps
CPU time 135.09 seconds
Started Apr 30 02:33:32 PM PDT 24
Finished Apr 30 02:35:47 PM PDT 24
Peak memory 292244 kb
Host smart-d90428ce-6b51-4127-910e-38d0ecc1d9b1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007656784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_intr_rd.1007656784
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.1167318672
Short name T512
Test name
Test status
Simulation time 93987631000 ps
CPU time 248.22 seconds
Started Apr 30 02:33:29 PM PDT 24
Finished Apr 30 02:37:38 PM PDT 24
Peak memory 284236 kb
Host smart-83fe07e1-3f91-4129-81cb-06db424ece3f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167318672 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.1167318672
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.3608764686
Short name T455
Test name
Test status
Simulation time 182159700 ps
CPU time 110.97 seconds
Started Apr 30 02:33:34 PM PDT 24
Finished Apr 30 02:35:26 PM PDT 24
Peak memory 259212 kb
Host smart-965eb872-a739-4c54-8155-48340346082a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608764686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_o
tp_reset.3608764686
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.2694079452
Short name T896
Test name
Test status
Simulation time 4912975100 ps
CPU time 72.17 seconds
Started Apr 30 02:33:35 PM PDT 24
Finished Apr 30 02:34:47 PM PDT 24
Peak memory 262860 kb
Host smart-d04fb747-c9a3-40f1-914e-e52fc637cc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694079452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.2694079452
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.180184311
Short name T918
Test name
Test status
Simulation time 64596300 ps
CPU time 99.02 seconds
Started Apr 30 02:33:34 PM PDT 24
Finished Apr 30 02:35:14 PM PDT 24
Peak memory 275692 kb
Host smart-326905c7-869f-4ab7-9eb6-eac8f7b02656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180184311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.180184311
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.3466744135
Short name T827
Test name
Test status
Simulation time 47271500 ps
CPU time 13.66 seconds
Started Apr 30 02:33:41 PM PDT 24
Finished Apr 30 02:33:55 PM PDT 24
Peak memory 264588 kb
Host smart-81634070-9431-4c5d-9c0d-f7974c22abe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466744135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.
3466744135
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.332783933
Short name T690
Test name
Test status
Simulation time 13339600 ps
CPU time 15.76 seconds
Started Apr 30 02:33:43 PM PDT 24
Finished Apr 30 02:33:59 PM PDT 24
Peak memory 274536 kb
Host smart-a1f6fb09-f916-4963-ba3e-64f543cb4240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332783933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.332783933
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.3866512046
Short name T900
Test name
Test status
Simulation time 2001490400 ps
CPU time 53.11 seconds
Started Apr 30 02:33:36 PM PDT 24
Finished Apr 30 02:34:29 PM PDT 24
Peak memory 262020 kb
Host smart-e5b0b1de-0784-4c9e-a1b3-b2db82a47561
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866512046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.3866512046
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.1947908893
Short name T763
Test name
Test status
Simulation time 3930098200 ps
CPU time 154.79 seconds
Started Apr 30 02:33:36 PM PDT 24
Finished Apr 30 02:36:12 PM PDT 24
Peak memory 293352 kb
Host smart-c7acddfb-8747-40a7-a13f-3cd232b5853e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947908893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_intr_rd.1947908893
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.2825511347
Short name T502
Test name
Test status
Simulation time 28765935500 ps
CPU time 231.14 seconds
Started Apr 30 02:33:43 PM PDT 24
Finished Apr 30 02:37:35 PM PDT 24
Peak memory 284264 kb
Host smart-2e5d283f-e9d3-4401-af8d-d047ef1fb6cd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825511347 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.2825511347
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.300830114
Short name T268
Test name
Test status
Simulation time 74821100 ps
CPU time 131.93 seconds
Started Apr 30 02:33:35 PM PDT 24
Finished Apr 30 02:35:47 PM PDT 24
Peak memory 259444 kb
Host smart-f6ee9715-de0b-4445-b74d-565f6ee20f33
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300830114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_ot
p_reset.300830114
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.629945810
Short name T401
Test name
Test status
Simulation time 5210399300 ps
CPU time 81.54 seconds
Started Apr 30 02:33:41 PM PDT 24
Finished Apr 30 02:35:03 PM PDT 24
Peak memory 262528 kb
Host smart-889f6321-923a-4918-843c-ad844637525d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629945810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.629945810
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.4183885022
Short name T822
Test name
Test status
Simulation time 41942300 ps
CPU time 172.34 seconds
Started Apr 30 02:33:35 PM PDT 24
Finished Apr 30 02:36:28 PM PDT 24
Peak memory 275852 kb
Host smart-19fdfac9-fff9-4013-98bd-23189cf78e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183885022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.4183885022
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.2519181009
Short name T728
Test name
Test status
Simulation time 143915200 ps
CPU time 14.58 seconds
Started Apr 30 02:33:53 PM PDT 24
Finished Apr 30 02:34:08 PM PDT 24
Peak memory 258772 kb
Host smart-dc195397-0024-4a1d-adc6-5f6d134b35cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519181009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.
2519181009
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.1221121169
Short name T536
Test name
Test status
Simulation time 46685600 ps
CPU time 16.31 seconds
Started Apr 30 02:33:44 PM PDT 24
Finished Apr 30 02:34:01 PM PDT 24
Peak memory 274752 kb
Host smart-9cf81fe6-8123-4c05-9abc-6bcc584050d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221121169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.1221121169
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.1657311565
Short name T624
Test name
Test status
Simulation time 583970900 ps
CPU time 58.7 seconds
Started Apr 30 02:33:39 PM PDT 24
Finished Apr 30 02:34:38 PM PDT 24
Peak memory 261380 kb
Host smart-9c038904-da59-4e4c-ade1-36d8e229bd96
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657311565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.1657311565
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.3964300446
Short name T664
Test name
Test status
Simulation time 4725646100 ps
CPU time 189.59 seconds
Started Apr 30 02:33:53 PM PDT 24
Finished Apr 30 02:37:03 PM PDT 24
Peak memory 293640 kb
Host smart-00d6cad5-0626-477d-8709-3ff4dc1a05b3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964300446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla
sh_ctrl_intr_rd.3964300446
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3295452702
Short name T353
Test name
Test status
Simulation time 8622706300 ps
CPU time 235.63 seconds
Started Apr 30 02:33:45 PM PDT 24
Finished Apr 30 02:37:41 PM PDT 24
Peak memory 290292 kb
Host smart-437971f7-5884-47e4-8ebe-c365c85abbb2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295452702 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.3295452702
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.2221921842
Short name T691
Test name
Test status
Simulation time 315072500 ps
CPU time 130.27 seconds
Started Apr 30 02:33:44 PM PDT 24
Finished Apr 30 02:35:55 PM PDT 24
Peak memory 259156 kb
Host smart-80447a1b-30f2-443b-89ca-eeac12e2c878
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221921842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o
tp_reset.2221921842
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.462143599
Short name T581
Test name
Test status
Simulation time 16870355100 ps
CPU time 85.31 seconds
Started Apr 30 02:33:53 PM PDT 24
Finished Apr 30 02:35:19 PM PDT 24
Peak memory 262224 kb
Host smart-65ab9b07-9db7-4291-8a75-042c187b55ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462143599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.462143599
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.1126551306
Short name T479
Test name
Test status
Simulation time 56325200 ps
CPU time 147.51 seconds
Started Apr 30 02:33:41 PM PDT 24
Finished Apr 30 02:36:09 PM PDT 24
Peak memory 275520 kb
Host smart-b22770e0-25f3-41a6-bceb-69a320edceb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126551306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.1126551306
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.133591454
Short name T519
Test name
Test status
Simulation time 141086900 ps
CPU time 14.59 seconds
Started Apr 30 02:33:51 PM PDT 24
Finished Apr 30 02:34:06 PM PDT 24
Peak memory 264624 kb
Host smart-051ceb4a-2a64-4fd6-8ca9-79925edcd5ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133591454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.133591454
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.2373210227
Short name T458
Test name
Test status
Simulation time 16722200 ps
CPU time 16.06 seconds
Started Apr 30 02:33:51 PM PDT 24
Finished Apr 30 02:34:08 PM PDT 24
Peak memory 275276 kb
Host smart-58e13407-960c-48af-a96f-d18b9a215ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373210227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2373210227
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.3411987171
Short name T604
Test name
Test status
Simulation time 29283500 ps
CPU time 20.9 seconds
Started Apr 30 02:33:52 PM PDT 24
Finished Apr 30 02:34:13 PM PDT 24
Peak memory 264792 kb
Host smart-d2208a43-fb61-4f02-b6d2-aed7974dcc0b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411987171 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.3411987171
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.3406974004
Short name T292
Test name
Test status
Simulation time 967094800 ps
CPU time 36.2 seconds
Started Apr 30 02:33:52 PM PDT 24
Finished Apr 30 02:34:29 PM PDT 24
Peak memory 262272 kb
Host smart-486ef0b7-c142-4bf9-8cf2-7d0d3693b2c0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406974004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_
hw_sec_otp.3406974004
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.1670564088
Short name T610
Test name
Test status
Simulation time 8364544500 ps
CPU time 217.97 seconds
Started Apr 30 02:33:51 PM PDT 24
Finished Apr 30 02:37:29 PM PDT 24
Peak memory 290240 kb
Host smart-aca99954-bc0e-4f96-9367-08b73ab95b4c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670564088 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.1670564088
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.398366123
Short name T885
Test name
Test status
Simulation time 156878000 ps
CPU time 133.02 seconds
Started Apr 30 02:33:53 PM PDT 24
Finished Apr 30 02:36:07 PM PDT 24
Peak memory 259452 kb
Host smart-97ff5db9-c775-4ef9-a426-49dfd1855894
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398366123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_ot
p_reset.398366123
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.1617303188
Short name T514
Test name
Test status
Simulation time 2220798600 ps
CPU time 75.91 seconds
Started Apr 30 02:33:50 PM PDT 24
Finished Apr 30 02:35:07 PM PDT 24
Peak memory 263484 kb
Host smart-de8df174-8078-443f-b7aa-04111af48be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617303188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.1617303188
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.2375182945
Short name T266
Test name
Test status
Simulation time 49712400 ps
CPU time 101.39 seconds
Started Apr 30 02:33:43 PM PDT 24
Finished Apr 30 02:35:25 PM PDT 24
Peak memory 275824 kb
Host smart-9bcf2246-9c2d-45da-ba51-8721d9c69952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375182945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.2375182945
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.1980986600
Short name T854
Test name
Test status
Simulation time 90871200 ps
CPU time 14.95 seconds
Started Apr 30 02:34:00 PM PDT 24
Finished Apr 30 02:34:16 PM PDT 24
Peak memory 264644 kb
Host smart-42a8093b-b245-4311-ad08-91a2aedf76be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980986600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.
1980986600
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.1991657637
Short name T923
Test name
Test status
Simulation time 16095900 ps
CPU time 15.87 seconds
Started Apr 30 02:33:55 PM PDT 24
Finished Apr 30 02:34:12 PM PDT 24
Peak memory 275276 kb
Host smart-0a56021d-37f5-457a-9b20-e523d09da95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991657637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.1991657637
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.2395945197
Short name T783
Test name
Test status
Simulation time 7241389900 ps
CPU time 134.03 seconds
Started Apr 30 02:33:50 PM PDT 24
Finished Apr 30 02:36:05 PM PDT 24
Peak memory 261780 kb
Host smart-9b6b8fc0-0065-45ee-9a2c-442e77b75e17
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395945197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.2395945197
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.3906459848
Short name T303
Test name
Test status
Simulation time 1270932600 ps
CPU time 139.06 seconds
Started Apr 30 02:33:50 PM PDT 24
Finished Apr 30 02:36:09 PM PDT 24
Peak memory 293536 kb
Host smart-6aa931f7-c509-4bb8-a195-7756f5bceccb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906459848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla
sh_ctrl_intr_rd.3906459848
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.3538125128
Short name T849
Test name
Test status
Simulation time 101551590800 ps
CPU time 233.44 seconds
Started Apr 30 02:33:57 PM PDT 24
Finished Apr 30 02:37:51 PM PDT 24
Peak memory 290208 kb
Host smart-477b941f-78ea-43ad-9b15-b2f99a899e3a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538125128 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.3538125128
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.68624535
Short name T432
Test name
Test status
Simulation time 142192600 ps
CPU time 109.94 seconds
Started Apr 30 02:33:51 PM PDT 24
Finished Apr 30 02:35:41 PM PDT 24
Peak memory 259252 kb
Host smart-10db386f-e72c-4b05-bc30-10bc02aa1bb8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68624535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_otp
_reset.68624535
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.3013347790
Short name T371
Test name
Test status
Simulation time 75473100 ps
CPU time 31.66 seconds
Started Apr 30 02:33:59 PM PDT 24
Finished Apr 30 02:34:31 PM PDT 24
Peak memory 274448 kb
Host smart-111f3ee0-141d-4820-880c-f31f4d9bd651
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013347790 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.3013347790
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.52743524
Short name T324
Test name
Test status
Simulation time 1766050700 ps
CPU time 73.17 seconds
Started Apr 30 02:33:56 PM PDT 24
Finished Apr 30 02:35:10 PM PDT 24
Peak memory 261896 kb
Host smart-c0fc9e10-5e24-43d5-85d7-3b3e639ef957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52743524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.52743524
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.621147316
Short name T830
Test name
Test status
Simulation time 69582800 ps
CPU time 72.82 seconds
Started Apr 30 02:33:51 PM PDT 24
Finished Apr 30 02:35:05 PM PDT 24
Peak memory 275344 kb
Host smart-08ac1337-25f8-4433-850d-f1d4610545d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621147316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.621147316
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.534653204
Short name T818
Test name
Test status
Simulation time 106989000 ps
CPU time 13.55 seconds
Started Apr 30 02:34:03 PM PDT 24
Finished Apr 30 02:34:17 PM PDT 24
Peak memory 257772 kb
Host smart-c984f5b2-3db3-4572-8a13-70dc52ee6d6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534653204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.534653204
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.1909784702
Short name T80
Test name
Test status
Simulation time 22885700 ps
CPU time 16.27 seconds
Started Apr 30 02:34:04 PM PDT 24
Finished Apr 30 02:34:21 PM PDT 24
Peak memory 275268 kb
Host smart-17aa44ed-d092-4bc2-9921-a4d77c2ba75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909784702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.1909784702
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.2505448661
Short name T58
Test name
Test status
Simulation time 25302100 ps
CPU time 22.76 seconds
Started Apr 30 02:34:05 PM PDT 24
Finished Apr 30 02:34:28 PM PDT 24
Peak memory 280288 kb
Host smart-e040d812-0ab6-489a-a427-42e2979b3dc5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505448661 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.2505448661
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.2888712491
Short name T506
Test name
Test status
Simulation time 17950038600 ps
CPU time 152.24 seconds
Started Apr 30 02:33:57 PM PDT 24
Finished Apr 30 02:36:29 PM PDT 24
Peak memory 261764 kb
Host smart-effdef8b-b213-4561-b583-8e19556d1ddd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888712491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.2888712491
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.3406959350
Short name T264
Test name
Test status
Simulation time 1080021100 ps
CPU time 182.52 seconds
Started Apr 30 02:33:57 PM PDT 24
Finished Apr 30 02:37:00 PM PDT 24
Peak memory 290352 kb
Host smart-4a014d9b-d244-4170-9134-0c614291abf7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406959350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla
sh_ctrl_intr_rd.3406959350
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.2452099412
Short name T774
Test name
Test status
Simulation time 41670610400 ps
CPU time 212.07 seconds
Started Apr 30 02:33:58 PM PDT 24
Finished Apr 30 02:37:30 PM PDT 24
Peak memory 284084 kb
Host smart-bb486503-da17-4079-8837-c0174089fcd7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452099412 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.2452099412
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.110951601
Short name T620
Test name
Test status
Simulation time 34558200 ps
CPU time 135.1 seconds
Started Apr 30 02:33:58 PM PDT 24
Finished Apr 30 02:36:13 PM PDT 24
Peak memory 259124 kb
Host smart-47426f53-4529-4840-bb20-c21a7c35b502
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110951601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_ot
p_reset.110951601
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.464346234
Short name T590
Test name
Test status
Simulation time 8675419100 ps
CPU time 75.04 seconds
Started Apr 30 02:34:03 PM PDT 24
Finished Apr 30 02:35:19 PM PDT 24
Peak memory 262416 kb
Host smart-c49ff87b-fd1d-4a46-a63f-8beaa8bdbd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464346234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.464346234
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.3227880336
Short name T220
Test name
Test status
Simulation time 704004200 ps
CPU time 204.51 seconds
Started Apr 30 02:33:57 PM PDT 24
Finished Apr 30 02:37:22 PM PDT 24
Peak memory 280816 kb
Host smart-360a9424-1e6f-4908-9909-65a5677f1595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227880336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.3227880336
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.3298165092
Short name T388
Test name
Test status
Simulation time 55341100 ps
CPU time 13.32 seconds
Started Apr 30 02:34:09 PM PDT 24
Finished Apr 30 02:34:23 PM PDT 24
Peak memory 257584 kb
Host smart-abb55295-3163-428d-817e-741229aa3f40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298165092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
3298165092
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.3709049765
Short name T505
Test name
Test status
Simulation time 17399700 ps
CPU time 13.41 seconds
Started Apr 30 02:34:10 PM PDT 24
Finished Apr 30 02:34:24 PM PDT 24
Peak memory 275252 kb
Host smart-8f1a8f67-5ce8-4f6d-842d-f45efed22c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709049765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.3709049765
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.1310808523
Short name T657
Test name
Test status
Simulation time 2720583400 ps
CPU time 96.32 seconds
Started Apr 30 02:34:05 PM PDT 24
Finished Apr 30 02:35:42 PM PDT 24
Peak memory 261936 kb
Host smart-bb3f3194-7115-4251-b473-d78f9fc7197c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310808523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_
hw_sec_otp.1310808523
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.2709279663
Short name T876
Test name
Test status
Simulation time 8056617100 ps
CPU time 204.11 seconds
Started Apr 30 02:34:04 PM PDT 24
Finished Apr 30 02:37:28 PM PDT 24
Peak memory 290312 kb
Host smart-5b276c3d-b599-41df-971e-9b7cb326081b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709279663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_intr_rd.2709279663
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.2721167099
Short name T639
Test name
Test status
Simulation time 16836331900 ps
CPU time 192.09 seconds
Started Apr 30 02:34:04 PM PDT 24
Finished Apr 30 02:37:16 PM PDT 24
Peak memory 291916 kb
Host smart-76de6d06-9a40-4954-8359-739db8dc28c5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721167099 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.2721167099
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.4109331064
Short name T477
Test name
Test status
Simulation time 120936700 ps
CPU time 134.24 seconds
Started Apr 30 02:34:05 PM PDT 24
Finished Apr 30 02:36:19 PM PDT 24
Peak memory 263516 kb
Host smart-e872f39e-1d73-492c-a213-a6133915a11d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109331064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o
tp_reset.4109331064
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.853104206
Short name T63
Test name
Test status
Simulation time 1273950900 ps
CPU time 67.91 seconds
Started Apr 30 02:34:11 PM PDT 24
Finished Apr 30 02:35:19 PM PDT 24
Peak memory 261948 kb
Host smart-ebbb19f1-f6a4-4e42-89b2-7f14c476e7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853104206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.853104206
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.397872684
Short name T218
Test name
Test status
Simulation time 713295400 ps
CPU time 126.37 seconds
Started Apr 30 02:34:04 PM PDT 24
Finished Apr 30 02:36:11 PM PDT 24
Peak memory 280420 kb
Host smart-042f4a62-b79c-44fa-b40c-89dcd37f6daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397872684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.397872684
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.2116237512
Short name T510
Test name
Test status
Simulation time 43508200 ps
CPU time 13.77 seconds
Started Apr 30 02:34:15 PM PDT 24
Finished Apr 30 02:34:29 PM PDT 24
Peak memory 257636 kb
Host smart-7162f91e-3279-437a-b9de-df0e2a401e36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116237512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.
2116237512
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.51599687
Short name T594
Test name
Test status
Simulation time 15363900 ps
CPU time 16.38 seconds
Started Apr 30 02:34:16 PM PDT 24
Finished Apr 30 02:34:33 PM PDT 24
Peak memory 275332 kb
Host smart-e4bf1fb8-24ce-413d-8329-0490318d2c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51599687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.51599687
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.2221064542
Short name T649
Test name
Test status
Simulation time 4469650400 ps
CPU time 139.61 seconds
Started Apr 30 02:34:18 PM PDT 24
Finished Apr 30 02:36:38 PM PDT 24
Peak memory 262000 kb
Host smart-90ae3a65-ce18-4d3c-ba2a-920ef35bc155
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221064542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_
hw_sec_otp.2221064542
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.2441738106
Short name T532
Test name
Test status
Simulation time 2467920500 ps
CPU time 160.46 seconds
Started Apr 30 02:34:16 PM PDT 24
Finished Apr 30 02:36:58 PM PDT 24
Peak memory 293492 kb
Host smart-e89e3440-8c67-4b24-aae6-fe4afc080a26
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441738106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.2441738106
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.1623805139
Short name T369
Test name
Test status
Simulation time 34044800 ps
CPU time 32.11 seconds
Started Apr 30 02:34:16 PM PDT 24
Finished Apr 30 02:34:48 PM PDT 24
Peak memory 273020 kb
Host smart-689d4ab5-ac90-462b-8096-2b7bbaf8fee0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623805139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl
ash_ctrl_rw_evict.1623805139
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.2549692697
Short name T185
Test name
Test status
Simulation time 41673700 ps
CPU time 31.78 seconds
Started Apr 30 02:34:15 PM PDT 24
Finished Apr 30 02:34:47 PM PDT 24
Peak memory 274356 kb
Host smart-a921f9d2-7c5f-499d-a94d-898fc1821a7b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549692697 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.2549692697
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.1464717449
Short name T759
Test name
Test status
Simulation time 1444036400 ps
CPU time 72.47 seconds
Started Apr 30 02:34:16 PM PDT 24
Finished Apr 30 02:35:29 PM PDT 24
Peak memory 262556 kb
Host smart-5f1a87ad-099f-415a-be0a-f7c9fb432e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464717449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.1464717449
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.1766898857
Short name T836
Test name
Test status
Simulation time 27292300 ps
CPU time 49.9 seconds
Started Apr 30 02:34:09 PM PDT 24
Finished Apr 30 02:35:00 PM PDT 24
Peak memory 269896 kb
Host smart-43176484-771b-426b-a715-fe2c11f13702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766898857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.1766898857
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.718363987
Short name T464
Test name
Test status
Simulation time 16677000 ps
CPU time 13.7 seconds
Started Apr 30 02:28:09 PM PDT 24
Finished Apr 30 02:28:24 PM PDT 24
Peak memory 264520 kb
Host smart-e38ac9ae-71d0-4daf-815f-aec3dfb24311
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718363987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.718363987
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.1165226260
Short name T660
Test name
Test status
Simulation time 21523500 ps
CPU time 13.65 seconds
Started Apr 30 02:28:08 PM PDT 24
Finished Apr 30 02:28:23 PM PDT 24
Peak memory 261436 kb
Host smart-eafc9c7d-4502-4c61-95bb-3eea9be77b6e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165226260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.flash_ctrl_config_regwen.1165226260
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.3138823981
Short name T793
Test name
Test status
Simulation time 40301100 ps
CPU time 15.71 seconds
Started Apr 30 02:28:04 PM PDT 24
Finished Apr 30 02:28:20 PM PDT 24
Peak memory 275336 kb
Host smart-639d123c-f267-4fb3-862b-bbc11021cc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138823981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.3138823981
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.934317584
Short name T385
Test name
Test status
Simulation time 33232900 ps
CPU time 22.39 seconds
Started Apr 30 02:27:57 PM PDT 24
Finished Apr 30 02:28:20 PM PDT 24
Peak memory 272812 kb
Host smart-76d88bb7-6fe4-41d3-a3fd-e7b5dfa467f1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934317584 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.934317584
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.2359342195
Short name T528
Test name
Test status
Simulation time 16821164100 ps
CPU time 2461.72 seconds
Started Apr 30 02:27:50 PM PDT 24
Finished Apr 30 03:08:53 PM PDT 24
Peak memory 263904 kb
Host smart-659dae12-081c-4fdd-b798-1e0e71a4b465
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359342195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_err
or_mp.2359342195
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.3991015370
Short name T789
Test name
Test status
Simulation time 3371886000 ps
CPU time 2423.99 seconds
Started Apr 30 02:27:48 PM PDT 24
Finished Apr 30 03:08:14 PM PDT 24
Peak memory 264428 kb
Host smart-3b566dfc-2b71-441d-a5b6-6be8b2804029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991015370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.3991015370
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.3748928618
Short name T168
Test name
Test status
Simulation time 5248540000 ps
CPU time 968.09 seconds
Started Apr 30 02:27:50 PM PDT 24
Finished Apr 30 02:43:59 PM PDT 24
Peak memory 272708 kb
Host smart-a97e540a-409a-4a9c-a2d0-4d1142f235cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748928618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.3748928618
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.1603349565
Short name T138
Test name
Test status
Simulation time 57720842300 ps
CPU time 3452.33 seconds
Started Apr 30 02:27:47 PM PDT 24
Finished Apr 30 03:25:21 PM PDT 24
Peak memory 264308 kb
Host smart-e1b98530-0cd4-44d2-94d1-031b282cf16a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603349565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_full_mem_access.1603349565
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.204132163
Short name T271
Test name
Test status
Simulation time 76012800 ps
CPU time 122.99 seconds
Started Apr 30 02:27:48 PM PDT 24
Finished Apr 30 02:29:52 PM PDT 24
Peak memory 264336 kb
Host smart-684f1059-9292-4956-9790-cd2324640562
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=204132163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.204132163
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.1427763463
Short name T800
Test name
Test status
Simulation time 10014221500 ps
CPU time 238.19 seconds
Started Apr 30 02:28:08 PM PDT 24
Finished Apr 30 02:32:07 PM PDT 24
Peak memory 311812 kb
Host smart-8f0f0933-78fe-450a-bed8-ed20763a3a3d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427763463 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.1427763463
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.4122469234
Short name T790
Test name
Test status
Simulation time 47093000 ps
CPU time 13.52 seconds
Started Apr 30 02:28:08 PM PDT 24
Finished Apr 30 02:28:22 PM PDT 24
Peak memory 264532 kb
Host smart-d1edb810-7a04-4cf3-9d68-34ec8a5a9429
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122469234 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.4122469234
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.3065154636
Short name T561
Test name
Test status
Simulation time 40126876100 ps
CPU time 861.97 seconds
Started Apr 30 02:27:48 PM PDT 24
Finished Apr 30 02:42:11 PM PDT 24
Peak memory 262756 kb
Host smart-210da948-64ab-411e-9aec-069693b4a9b7
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065154636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_hw_rma_reset.3065154636
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.1096526512
Short name T909
Test name
Test status
Simulation time 1851820400 ps
CPU time 36.33 seconds
Started Apr 30 02:27:48 PM PDT 24
Finished Apr 30 02:28:26 PM PDT 24
Peak memory 261944 kb
Host smart-3707b969-bc4a-46b4-9b17-55e0ab020d20
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096526512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.1096526512
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.3574065981
Short name T683
Test name
Test status
Simulation time 4338239300 ps
CPU time 202.85 seconds
Started Apr 30 02:27:57 PM PDT 24
Finished Apr 30 02:31:20 PM PDT 24
Peak memory 292348 kb
Host smart-407f02ff-da85-482d-80b8-8429e37fda59
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574065981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.3574065981
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.1199157374
Short name T593
Test name
Test status
Simulation time 1842125300 ps
CPU time 57.57 seconds
Started Apr 30 02:27:48 PM PDT 24
Finished Apr 30 02:28:47 PM PDT 24
Peak memory 260096 kb
Host smart-8dd467a2-ddcd-4ecf-9f6d-2bb3bfd67f71
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199157374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.1199157374
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.1879239344
Short name T284
Test name
Test status
Simulation time 64182500 ps
CPU time 13.56 seconds
Started Apr 30 02:28:09 PM PDT 24
Finished Apr 30 02:28:23 PM PDT 24
Peak memory 259160 kb
Host smart-23543f4e-e0bb-4c88-97ab-57ae862f1baa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879239344 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.1879239344
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.346830551
Short name T133
Test name
Test status
Simulation time 14228331800 ps
CPU time 343.8 seconds
Started Apr 30 02:27:49 PM PDT 24
Finished Apr 30 02:33:33 PM PDT 24
Peak memory 273860 kb
Host smart-efb1b90c-5c96-4b89-9c0b-1c58d90cefe2
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346830551 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_mp_regions.346830551
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.2518759868
Short name T677
Test name
Test status
Simulation time 41166800 ps
CPU time 109.63 seconds
Started Apr 30 02:27:48 PM PDT 24
Finished Apr 30 02:29:39 PM PDT 24
Peak memory 259392 kb
Host smart-8b9b32fd-f7e7-4640-9d87-4873551b3236
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518759868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.2518759868
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.559077911
Short name T670
Test name
Test status
Simulation time 189801200 ps
CPU time 238.94 seconds
Started Apr 30 02:27:51 PM PDT 24
Finished Apr 30 02:31:50 PM PDT 24
Peak memory 264408 kb
Host smart-505648a4-5a55-4e5a-9a6a-ff5df1c99abf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=559077911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.559077911
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.3791365715
Short name T156
Test name
Test status
Simulation time 766579900 ps
CPU time 17.08 seconds
Started Apr 30 02:28:02 PM PDT 24
Finished Apr 30 02:28:20 PM PDT 24
Peak memory 261876 kb
Host smart-f1dbc044-4208-438b-b966-8dbca1bfe257
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791365715 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.3791365715
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.3675557389
Short name T148
Test name
Test status
Simulation time 3328073000 ps
CPU time 1002.14 seconds
Started Apr 30 02:27:43 PM PDT 24
Finished Apr 30 02:44:26 PM PDT 24
Peak memory 285464 kb
Host smart-05b871d6-f4ec-4747-bd6a-7e8f119fede5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675557389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.3675557389
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.3093164701
Short name T579
Test name
Test status
Simulation time 301089400 ps
CPU time 100.31 seconds
Started Apr 30 02:27:41 PM PDT 24
Finished Apr 30 02:29:23 PM PDT 24
Peak memory 264404 kb
Host smart-b44bcee8-bbc2-4c20-8bf0-7ae4ad302c88
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3093164701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.3093164701
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.3008214496
Short name T950
Test name
Test status
Simulation time 172782200 ps
CPU time 36.03 seconds
Started Apr 30 02:27:56 PM PDT 24
Finished Apr 30 02:28:33 PM PDT 24
Peak memory 268100 kb
Host smart-8b6e1730-46ee-40e6-8b45-9c0bbe86b642
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008214496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.3008214496
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.3844366399
Short name T816
Test name
Test status
Simulation time 18308600 ps
CPU time 21.8 seconds
Started Apr 30 02:27:50 PM PDT 24
Finished Apr 30 02:28:13 PM PDT 24
Peak memory 264740 kb
Host smart-930e7082-d879-4ae2-ab22-460073c95a90
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844366399 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.3844366399
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.677151966
Short name T571
Test name
Test status
Simulation time 25325900 ps
CPU time 22.81 seconds
Started Apr 30 02:27:49 PM PDT 24
Finished Apr 30 02:28:13 PM PDT 24
Peak memory 264708 kb
Host smart-b2813c6a-ed1b-4543-ab0d-87d71ebb50f1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677151966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_read_word_sweep_serr.677151966
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.3149984772
Short name T826
Test name
Test status
Simulation time 1308946800 ps
CPU time 123.55 seconds
Started Apr 30 02:27:52 PM PDT 24
Finished Apr 30 02:29:56 PM PDT 24
Peak memory 296896 kb
Host smart-cf835555-c358-4c2d-b9da-e07633a9b2d2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149984772 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_ro.3149984772
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.1474576404
Short name T194
Test name
Test status
Simulation time 955857500 ps
CPU time 184.37 seconds
Started Apr 30 02:27:50 PM PDT 24
Finished Apr 30 02:30:55 PM PDT 24
Peak memory 283676 kb
Host smart-b7169886-6689-4483-abde-db73c673e305
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1474576404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.1474576404
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.1361793520
Short name T697
Test name
Test status
Simulation time 838027200 ps
CPU time 137.18 seconds
Started Apr 30 02:27:55 PM PDT 24
Finished Apr 30 02:30:12 PM PDT 24
Peak memory 289368 kb
Host smart-630368d0-e159-43c1-ae1d-e00b943ae81f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361793520 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.1361793520
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.810762329
Short name T367
Test name
Test status
Simulation time 52157800 ps
CPU time 32.09 seconds
Started Apr 30 02:27:56 PM PDT 24
Finished Apr 30 02:28:28 PM PDT 24
Peak memory 274512 kb
Host smart-cff53320-1e87-4e8d-9ffb-14d56ad7741b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810762329 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.810762329
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.2918775132
Short name T183
Test name
Test status
Simulation time 1845238300 ps
CPU time 68.8 seconds
Started Apr 30 02:27:55 PM PDT 24
Finished Apr 30 02:29:04 PM PDT 24
Peak memory 262640 kb
Host smart-1f15cc53-8e5f-4c23-9997-eecf279e8c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918775132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.2918775132
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.1150521639
Short name T475
Test name
Test status
Simulation time 861174900 ps
CPU time 84.55 seconds
Started Apr 30 02:27:51 PM PDT 24
Finished Apr 30 02:29:16 PM PDT 24
Peak memory 264776 kb
Host smart-efba1d51-eb00-4012-aca0-b9547a76a8c5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150521639 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_address.1150521639
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.3024461283
Short name T641
Test name
Test status
Simulation time 68063900 ps
CPU time 75.74 seconds
Started Apr 30 02:27:45 PM PDT 24
Finished Apr 30 02:29:01 PM PDT 24
Peak memory 274588 kb
Host smart-3987c28d-f421-4c9f-aaa3-877b0ad2a4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024461283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.3024461283
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.1275535935
Short name T838
Test name
Test status
Simulation time 18518100 ps
CPU time 23.86 seconds
Started Apr 30 02:27:49 PM PDT 24
Finished Apr 30 02:28:14 PM PDT 24
Peak memory 258316 kb
Host smart-405f2539-e476-4a20-9b40-f39665bd9b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275535935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.1275535935
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.921953722
Short name T710
Test name
Test status
Simulation time 3771126500 ps
CPU time 1560.28 seconds
Started Apr 30 02:27:55 PM PDT 24
Finished Apr 30 02:53:56 PM PDT 24
Peak memory 289080 kb
Host smart-ec836821-d108-4cae-8b59-a94d9aa2c363
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921953722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress
_all.921953722
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.2370013213
Short name T871
Test name
Test status
Simulation time 126124600 ps
CPU time 26.73 seconds
Started Apr 30 02:27:44 PM PDT 24
Finished Apr 30 02:28:12 PM PDT 24
Peak memory 258204 kb
Host smart-677482be-fc82-4e96-b141-70d36dc78359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370013213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.2370013213
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.2216265081
Short name T673
Test name
Test status
Simulation time 7664848200 ps
CPU time 176.26 seconds
Started Apr 30 02:27:48 PM PDT 24
Finished Apr 30 02:30:45 PM PDT 24
Peak memory 264712 kb
Host smart-3258eb3b-acd0-4fc5-a2d9-fe63b1c52c73
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216265081 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_wo.2216265081
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.4228059902
Short name T259
Test name
Test status
Simulation time 31119100 ps
CPU time 13.43 seconds
Started Apr 30 02:34:23 PM PDT 24
Finished Apr 30 02:34:37 PM PDT 24
Peak memory 257600 kb
Host smart-82604ea9-7e16-4dd1-8818-5f2773505210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228059902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.
4228059902
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.1382046459
Short name T727
Test name
Test status
Simulation time 158736600 ps
CPU time 15.74 seconds
Started Apr 30 02:34:23 PM PDT 24
Finished Apr 30 02:34:39 PM PDT 24
Peak memory 275748 kb
Host smart-ed9568b5-b9c5-4dfc-81cb-69db8b236e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382046459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.1382046459
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.748111394
Short name T256
Test name
Test status
Simulation time 27872500 ps
CPU time 21.56 seconds
Started Apr 30 02:34:23 PM PDT 24
Finished Apr 30 02:34:46 PM PDT 24
Peak memory 272936 kb
Host smart-a760210a-fb3a-4180-86e2-7ad8e37e5391
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748111394 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.748111394
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.2996933771
Short name T941
Test name
Test status
Simulation time 2282325900 ps
CPU time 183.46 seconds
Started Apr 30 02:34:24 PM PDT 24
Finished Apr 30 02:37:28 PM PDT 24
Peak memory 262176 kb
Host smart-9259b347-e1df-4af1-aac4-0ca87f90a0dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996933771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.2996933771
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.955737598
Short name T74
Test name
Test status
Simulation time 36990800 ps
CPU time 133.46 seconds
Started Apr 30 02:34:24 PM PDT 24
Finished Apr 30 02:36:38 PM PDT 24
Peak memory 259108 kb
Host smart-9823d7f4-b9e4-4867-ac19-9757435558c4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955737598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_ot
p_reset.955737598
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.2599281612
Short name T881
Test name
Test status
Simulation time 31653581000 ps
CPU time 111.26 seconds
Started Apr 30 02:34:24 PM PDT 24
Finished Apr 30 02:36:16 PM PDT 24
Peak memory 261788 kb
Host smart-83168c8e-88e2-4cac-9895-ad080aa6e4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599281612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.2599281612
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.1919097366
Short name T662
Test name
Test status
Simulation time 70056900 ps
CPU time 76.13 seconds
Started Apr 30 02:34:16 PM PDT 24
Finished Apr 30 02:35:33 PM PDT 24
Peak memory 275220 kb
Host smart-ae817c16-35f0-469a-9578-2e464a2773f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919097366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.1919097366
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.291892750
Short name T760
Test name
Test status
Simulation time 42783400 ps
CPU time 14.2 seconds
Started Apr 30 02:34:29 PM PDT 24
Finished Apr 30 02:34:43 PM PDT 24
Peak memory 264580 kb
Host smart-01551428-3d17-4152-99d7-b09a3a1cd04a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291892750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.291892750
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.1102764510
Short name T538
Test name
Test status
Simulation time 26278900 ps
CPU time 13.15 seconds
Started Apr 30 02:34:27 PM PDT 24
Finished Apr 30 02:34:41 PM PDT 24
Peak memory 274548 kb
Host smart-4559c514-134b-4ebc-911f-e01a9a09853e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102764510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.1102764510
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.148542350
Short name T928
Test name
Test status
Simulation time 36226600 ps
CPU time 22.03 seconds
Started Apr 30 02:34:29 PM PDT 24
Finished Apr 30 02:34:52 PM PDT 24
Peak memory 280036 kb
Host smart-3f4ccc17-7ffb-4bee-9f20-f029135a3a6b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148542350 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.148542350
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.3556744807
Short name T599
Test name
Test status
Simulation time 1806500800 ps
CPU time 72.93 seconds
Started Apr 30 02:34:23 PM PDT 24
Finished Apr 30 02:35:37 PM PDT 24
Peak memory 261944 kb
Host smart-41a28a09-402c-462f-a364-00d0f5c19313
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556744807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_
hw_sec_otp.3556744807
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.125110823
Short name T75
Test name
Test status
Simulation time 169555100 ps
CPU time 132.57 seconds
Started Apr 30 02:34:24 PM PDT 24
Finished Apr 30 02:36:37 PM PDT 24
Peak memory 263984 kb
Host smart-68fbbcd0-5b1c-4a18-a4f6-806fa137ce0f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125110823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_ot
p_reset.125110823
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.623312139
Short name T520
Test name
Test status
Simulation time 438773800 ps
CPU time 58.12 seconds
Started Apr 30 02:34:27 PM PDT 24
Finished Apr 30 02:35:26 PM PDT 24
Peak memory 259304 kb
Host smart-5fe40310-193b-4dc1-a990-26963ffb52c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623312139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.623312139
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.1324940568
Short name T562
Test name
Test status
Simulation time 81074200 ps
CPU time 168.54 seconds
Started Apr 30 02:34:23 PM PDT 24
Finished Apr 30 02:37:12 PM PDT 24
Peak memory 277292 kb
Host smart-34d81270-dae6-4128-8227-dae324236b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324940568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.1324940568
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.2342700851
Short name T574
Test name
Test status
Simulation time 228207800 ps
CPU time 14.1 seconds
Started Apr 30 02:34:29 PM PDT 24
Finished Apr 30 02:34:44 PM PDT 24
Peak memory 257640 kb
Host smart-a0d66f92-4081-45ae-a469-db4cf945d6a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342700851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.
2342700851
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.3292925543
Short name T61
Test name
Test status
Simulation time 44607200 ps
CPU time 13.64 seconds
Started Apr 30 02:34:29 PM PDT 24
Finished Apr 30 02:34:43 PM PDT 24
Peak memory 275340 kb
Host smart-827adb94-1867-49a0-b3e0-8427d940f8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292925543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.3292925543
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.823300855
Short name T452
Test name
Test status
Simulation time 84989200 ps
CPU time 22.26 seconds
Started Apr 30 02:34:26 PM PDT 24
Finished Apr 30 02:34:49 PM PDT 24
Peak memory 264652 kb
Host smart-c96e73a0-3378-4ebc-a9ed-b2ff56b2e7b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823300855 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.823300855
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.2778273927
Short name T870
Test name
Test status
Simulation time 7094563800 ps
CPU time 108.44 seconds
Started Apr 30 02:34:30 PM PDT 24
Finished Apr 30 02:36:19 PM PDT 24
Peak memory 262088 kb
Host smart-6436e66a-0156-4a4b-ba53-3e1ab945ceac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778273927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_
hw_sec_otp.2778273927
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.2111143077
Short name T742
Test name
Test status
Simulation time 157472300 ps
CPU time 131.69 seconds
Started Apr 30 02:34:29 PM PDT 24
Finished Apr 30 02:36:41 PM PDT 24
Peak memory 259344 kb
Host smart-8bfae4a4-855a-43a1-aad9-bdfeceed3387
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111143077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.2111143077
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.315070988
Short name T453
Test name
Test status
Simulation time 17462100 ps
CPU time 51.64 seconds
Started Apr 30 02:34:30 PM PDT 24
Finished Apr 30 02:35:22 PM PDT 24
Peak memory 269756 kb
Host smart-685c8160-265c-4d96-96d2-48d33ebb0a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315070988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.315070988
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.1841299470
Short name T722
Test name
Test status
Simulation time 55988300 ps
CPU time 14.04 seconds
Started Apr 30 02:34:32 PM PDT 24
Finished Apr 30 02:34:47 PM PDT 24
Peak memory 257652 kb
Host smart-c670c38b-7468-43f7-a314-a8d82b5568e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841299470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.
1841299470
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.681499423
Short name T530
Test name
Test status
Simulation time 36269700 ps
CPU time 15.71 seconds
Started Apr 30 02:34:29 PM PDT 24
Finished Apr 30 02:34:46 PM PDT 24
Peak memory 275260 kb
Host smart-4438c1f8-78c0-4045-9ca1-1a18cf221f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681499423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.681499423
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.3546233675
Short name T451
Test name
Test status
Simulation time 2970012400 ps
CPU time 104.08 seconds
Started Apr 30 02:34:28 PM PDT 24
Finished Apr 30 02:36:12 PM PDT 24
Peak memory 261888 kb
Host smart-abec1b1e-4af8-4ee4-85c9-5edc475a6712
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546233675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_
hw_sec_otp.3546233675
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.4085541665
Short name T757
Test name
Test status
Simulation time 39183300 ps
CPU time 112.42 seconds
Started Apr 30 02:34:32 PM PDT 24
Finished Apr 30 02:36:25 PM PDT 24
Peak memory 259332 kb
Host smart-62e100f2-09a5-4a6f-9ec8-44e250a1e67c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085541665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o
tp_reset.4085541665
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.619518463
Short name T412
Test name
Test status
Simulation time 13980606300 ps
CPU time 95.62 seconds
Started Apr 30 02:34:29 PM PDT 24
Finished Apr 30 02:36:05 PM PDT 24
Peak memory 262256 kb
Host smart-33eebc2e-070c-4d16-92ac-c3c22d820937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619518463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.619518463
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.2835312138
Short name T429
Test name
Test status
Simulation time 51888900 ps
CPU time 74.51 seconds
Started Apr 30 02:34:31 PM PDT 24
Finished Apr 30 02:35:46 PM PDT 24
Peak memory 274120 kb
Host smart-25f75f97-3cc2-4fae-b012-e5cd3cb6fc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835312138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.2835312138
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.3662456212
Short name T448
Test name
Test status
Simulation time 21592200 ps
CPU time 13.81 seconds
Started Apr 30 02:34:36 PM PDT 24
Finished Apr 30 02:34:51 PM PDT 24
Peak memory 257708 kb
Host smart-ce1f1cc3-1a39-494c-be6e-7d83961ef71b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662456212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
3662456212
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.3737847674
Short name T627
Test name
Test status
Simulation time 46232500 ps
CPU time 15.74 seconds
Started Apr 30 02:34:38 PM PDT 24
Finished Apr 30 02:34:54 PM PDT 24
Peak memory 274776 kb
Host smart-af5ec79c-73c4-4424-a542-f18ecda8f50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737847674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.3737847674
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.1873222799
Short name T737
Test name
Test status
Simulation time 14809600 ps
CPU time 22.14 seconds
Started Apr 30 02:34:37 PM PDT 24
Finished Apr 30 02:34:59 PM PDT 24
Peak memory 280248 kb
Host smart-312caf11-2eda-47c0-913d-6f29f33f5bb4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873222799 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.1873222799
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.22609326
Short name T778
Test name
Test status
Simulation time 1812171900 ps
CPU time 52.08 seconds
Started Apr 30 02:34:29 PM PDT 24
Finished Apr 30 02:35:22 PM PDT 24
Peak memory 261508 kb
Host smart-581c354c-c0c6-4840-8347-80f8c1bf7a55
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22609326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_hw
_sec_otp.22609326
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.2763854153
Short name T891
Test name
Test status
Simulation time 432117100 ps
CPU time 131.07 seconds
Started Apr 30 02:34:27 PM PDT 24
Finished Apr 30 02:36:39 PM PDT 24
Peak memory 259172 kb
Host smart-e56848c1-13aa-4441-917c-e7c7e6ed25ff
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763854153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o
tp_reset.2763854153
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.2617647147
Short name T328
Test name
Test status
Simulation time 13497931400 ps
CPU time 90.75 seconds
Started Apr 30 02:34:34 PM PDT 24
Finished Apr 30 02:36:05 PM PDT 24
Peak memory 262000 kb
Host smart-6f6b8e6b-39d3-49b1-9574-8c0e82fe92e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617647147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.2617647147
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.160567849
Short name T392
Test name
Test status
Simulation time 169892600 ps
CPU time 195.48 seconds
Started Apr 30 02:34:28 PM PDT 24
Finished Apr 30 02:37:44 PM PDT 24
Peak memory 276600 kb
Host smart-4dbd5d7a-0b99-4b98-a489-386be91aa1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160567849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.160567849
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.3489250938
Short name T468
Test name
Test status
Simulation time 95203500 ps
CPU time 13.82 seconds
Started Apr 30 02:34:34 PM PDT 24
Finished Apr 30 02:34:49 PM PDT 24
Peak memory 257728 kb
Host smart-52e21135-1cbb-4b65-ab5b-e107a4f59720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489250938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.
3489250938
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.3705773
Short name T525
Test name
Test status
Simulation time 52199200 ps
CPU time 16.07 seconds
Started Apr 30 02:34:45 PM PDT 24
Finished Apr 30 02:35:02 PM PDT 24
Peak memory 274520 kb
Host smart-6ceddf9f-5a8f-401c-950f-b2e1d731bf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.3705773
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.3708597700
Short name T886
Test name
Test status
Simulation time 12537536000 ps
CPU time 183.26 seconds
Started Apr 30 02:34:38 PM PDT 24
Finished Apr 30 02:37:42 PM PDT 24
Peak memory 261856 kb
Host smart-5709831a-7c07-485f-aa65-67d975e964b8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708597700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.3708597700
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.1881002275
Short name T883
Test name
Test status
Simulation time 46697800 ps
CPU time 113.79 seconds
Started Apr 30 02:34:35 PM PDT 24
Finished Apr 30 02:36:30 PM PDT 24
Peak memory 263244 kb
Host smart-6b748612-431b-4b4a-be82-da0387d8e6fb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881002275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o
tp_reset.1881002275
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.189751471
Short name T314
Test name
Test status
Simulation time 7644811800 ps
CPU time 77.56 seconds
Started Apr 30 02:34:37 PM PDT 24
Finished Apr 30 02:35:55 PM PDT 24
Peak memory 262004 kb
Host smart-d1f869a0-c836-473f-8361-000a827e54bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189751471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.189751471
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.2954153775
Short name T626
Test name
Test status
Simulation time 89186500 ps
CPU time 196.23 seconds
Started Apr 30 02:34:35 PM PDT 24
Finished Apr 30 02:37:52 PM PDT 24
Peak memory 278824 kb
Host smart-7363528f-b81f-45a6-a02c-4157274ce881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954153775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.2954153775
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.1313707671
Short name T435
Test name
Test status
Simulation time 157444800 ps
CPU time 13.91 seconds
Started Apr 30 02:34:41 PM PDT 24
Finished Apr 30 02:34:55 PM PDT 24
Peak memory 257664 kb
Host smart-c816fa58-37bb-48f6-97db-6f9ab9ee089a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313707671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
1313707671
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.2570942609
Short name T72
Test name
Test status
Simulation time 16784300 ps
CPU time 13.74 seconds
Started Apr 30 02:34:41 PM PDT 24
Finished Apr 30 02:34:55 PM PDT 24
Peak memory 274536 kb
Host smart-ebe3b319-2d40-4814-aac3-1b8bd4b16eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570942609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.2570942609
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.942987147
Short name T576
Test name
Test status
Simulation time 21362400 ps
CPU time 22.48 seconds
Started Apr 30 02:34:43 PM PDT 24
Finished Apr 30 02:35:06 PM PDT 24
Peak memory 264816 kb
Host smart-3b44a83d-15f2-44bb-94f0-d5ebf3f8bd51
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942987147 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.942987147
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.1045793014
Short name T776
Test name
Test status
Simulation time 430777900 ps
CPU time 137.35 seconds
Started Apr 30 02:34:43 PM PDT 24
Finished Apr 30 02:37:01 PM PDT 24
Peak memory 262880 kb
Host smart-98a33ad5-e3b9-43b8-9929-0e7447e08575
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045793014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o
tp_reset.1045793014
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.2244072586
Short name T890
Test name
Test status
Simulation time 4229883800 ps
CPU time 74.28 seconds
Started Apr 30 02:34:42 PM PDT 24
Finished Apr 30 02:35:57 PM PDT 24
Peak memory 262512 kb
Host smart-79d0d584-da12-46e5-988e-fdb1ba5e4c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244072586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.2244072586
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.1157106542
Short name T322
Test name
Test status
Simulation time 95060000 ps
CPU time 121.86 seconds
Started Apr 30 02:34:37 PM PDT 24
Finished Apr 30 02:36:39 PM PDT 24
Peak memory 276312 kb
Host smart-155011c9-1d8c-4d59-b342-a2c1dac5dcfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157106542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.1157106542
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.1387001133
Short name T718
Test name
Test status
Simulation time 31605600 ps
CPU time 13.53 seconds
Started Apr 30 02:34:48 PM PDT 24
Finished Apr 30 02:35:03 PM PDT 24
Peak memory 257688 kb
Host smart-e88e50f7-e2c1-496a-aabd-2991420c194c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387001133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
1387001133
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.4228148558
Short name T260
Test name
Test status
Simulation time 28520300 ps
CPU time 15.59 seconds
Started Apr 30 02:34:47 PM PDT 24
Finished Apr 30 02:35:03 PM PDT 24
Peak memory 275432 kb
Host smart-a309274e-0b12-406c-80ed-f17ff8698c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228148558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.4228148558
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.2772654387
Short name T55
Test name
Test status
Simulation time 15633300 ps
CPU time 21.11 seconds
Started Apr 30 02:34:41 PM PDT 24
Finished Apr 30 02:35:02 PM PDT 24
Peak memory 272980 kb
Host smart-98d36057-7503-49a9-81cf-26cb8ecaf339
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772654387 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.2772654387
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.2528785803
Short name T503
Test name
Test status
Simulation time 3551783000 ps
CPU time 60.78 seconds
Started Apr 30 02:34:42 PM PDT 24
Finished Apr 30 02:35:43 PM PDT 24
Peak memory 262064 kb
Host smart-f9ea41bb-9ac8-4c0d-958c-08befee69803
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528785803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.2528785803
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.2286452926
Short name T938
Test name
Test status
Simulation time 82989700 ps
CPU time 111.96 seconds
Started Apr 30 02:34:42 PM PDT 24
Finished Apr 30 02:36:35 PM PDT 24
Peak memory 259308 kb
Host smart-86a6349d-4e24-4924-b45a-6e73a0fb6049
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286452926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_o
tp_reset.2286452926
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.252059730
Short name T73
Test name
Test status
Simulation time 1363062100 ps
CPU time 81.04 seconds
Started Apr 30 02:34:43 PM PDT 24
Finished Apr 30 02:36:05 PM PDT 24
Peak memory 263416 kb
Host smart-e7191203-a3ef-4171-a435-7cb9def00bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252059730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.252059730
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.2075545869
Short name T621
Test name
Test status
Simulation time 702924200 ps
CPU time 175.2 seconds
Started Apr 30 02:34:43 PM PDT 24
Finished Apr 30 02:37:39 PM PDT 24
Peak memory 280788 kb
Host smart-1e016480-efdd-4ffb-b1a6-a7e4e50e9b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075545869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.2075545869
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.1203112781
Short name T541
Test name
Test status
Simulation time 240955900 ps
CPU time 14.4 seconds
Started Apr 30 02:34:56 PM PDT 24
Finished Apr 30 02:35:11 PM PDT 24
Peak memory 257816 kb
Host smart-d185bf16-8817-4839-ab78-5b61d60fd590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203112781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
1203112781
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.974282977
Short name T427
Test name
Test status
Simulation time 82535700 ps
CPU time 15.84 seconds
Started Apr 30 02:34:58 PM PDT 24
Finished Apr 30 02:35:14 PM PDT 24
Peak memory 275444 kb
Host smart-2098c1c5-72b3-4d12-88c7-0affcff73d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974282977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.974282977
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.814116975
Short name T41
Test name
Test status
Simulation time 10150600 ps
CPU time 20.97 seconds
Started Apr 30 02:34:48 PM PDT 24
Finished Apr 30 02:35:10 PM PDT 24
Peak memory 264740 kb
Host smart-e9074bb7-3449-4167-88d1-11da104d685b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814116975 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.814116975
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.695499491
Short name T949
Test name
Test status
Simulation time 10591556800 ps
CPU time 106.89 seconds
Started Apr 30 02:34:50 PM PDT 24
Finished Apr 30 02:36:37 PM PDT 24
Peak memory 261960 kb
Host smart-10057b62-c3f2-442e-9887-d5d674ee0a99
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695499491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_h
w_sec_otp.695499491
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.3484049516
Short name T531
Test name
Test status
Simulation time 39431400 ps
CPU time 134.13 seconds
Started Apr 30 02:34:48 PM PDT 24
Finished Apr 30 02:37:02 PM PDT 24
Peak memory 264364 kb
Host smart-ea8db6f3-797e-4442-9711-c0c64c225f88
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484049516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o
tp_reset.3484049516
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.631696077
Short name T898
Test name
Test status
Simulation time 3743773800 ps
CPU time 71.97 seconds
Started Apr 30 02:34:56 PM PDT 24
Finished Apr 30 02:36:08 PM PDT 24
Peak memory 262952 kb
Host smart-79fb985f-3de0-47b9-be7d-d16e41eb3269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631696077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.631696077
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.3237390147
Short name T672
Test name
Test status
Simulation time 95391700 ps
CPU time 95.99 seconds
Started Apr 30 02:34:49 PM PDT 24
Finished Apr 30 02:36:26 PM PDT 24
Peak memory 274452 kb
Host smart-08b78bd6-8b58-4fa0-9f13-4110d8e9f46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237390147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.3237390147
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.2105452627
Short name T723
Test name
Test status
Simulation time 50839800 ps
CPU time 14.03 seconds
Started Apr 30 02:34:58 PM PDT 24
Finished Apr 30 02:35:12 PM PDT 24
Peak memory 264608 kb
Host smart-2260e91d-c2f4-4bcd-b284-415f3fca293c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105452627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.
2105452627
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.3239652702
Short name T440
Test name
Test status
Simulation time 51108900 ps
CPU time 13.32 seconds
Started Apr 30 02:34:55 PM PDT 24
Finished Apr 30 02:35:08 PM PDT 24
Peak memory 274640 kb
Host smart-279a270d-de25-43e8-9902-2986b43dff7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239652702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.3239652702
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.2311012793
Short name T857
Test name
Test status
Simulation time 36346900 ps
CPU time 22.83 seconds
Started Apr 30 02:34:56 PM PDT 24
Finished Apr 30 02:35:19 PM PDT 24
Peak memory 273092 kb
Host smart-dad4cab6-da2b-4476-bf29-d608322e576d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311012793 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.2311012793
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.3621178456
Short name T942
Test name
Test status
Simulation time 6815601700 ps
CPU time 64.82 seconds
Started Apr 30 02:34:54 PM PDT 24
Finished Apr 30 02:36:00 PM PDT 24
Peak memory 262032 kb
Host smart-48dff0f8-7312-4283-8755-e69bdc614a82
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621178456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.3621178456
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.103153209
Short name T666
Test name
Test status
Simulation time 5482172000 ps
CPU time 74.94 seconds
Started Apr 30 02:34:55 PM PDT 24
Finished Apr 30 02:36:10 PM PDT 24
Peak memory 262604 kb
Host smart-4e7ddb23-82b4-4651-bbf3-bd805f86f369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103153209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.103153209
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.1424541542
Short name T592
Test name
Test status
Simulation time 31863000 ps
CPU time 119.35 seconds
Started Apr 30 02:34:56 PM PDT 24
Finished Apr 30 02:36:56 PM PDT 24
Peak memory 275068 kb
Host smart-dc367aa3-39b7-43e1-a4e8-526df45e2d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424541542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.1424541542
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.2219120913
Short name T831
Test name
Test status
Simulation time 61009200 ps
CPU time 14.46 seconds
Started Apr 30 02:28:24 PM PDT 24
Finished Apr 30 02:28:39 PM PDT 24
Peak memory 264636 kb
Host smart-900eac94-b594-4f87-8d32-4b679c065558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219120913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.2
219120913
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.2342401207
Short name T912
Test name
Test status
Simulation time 26811200 ps
CPU time 13.42 seconds
Started Apr 30 02:28:23 PM PDT 24
Finished Apr 30 02:28:38 PM PDT 24
Peak memory 275600 kb
Host smart-35c6943f-8de9-4846-b769-52b34e50009f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342401207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.2342401207
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.1234165332
Short name T394
Test name
Test status
Simulation time 30770100 ps
CPU time 22.92 seconds
Started Apr 30 02:28:32 PM PDT 24
Finished Apr 30 02:28:55 PM PDT 24
Peak memory 272864 kb
Host smart-206c7728-cad9-4169-975d-cf0e092bac6e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234165332 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.1234165332
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.3396416529
Short name T820
Test name
Test status
Simulation time 8086114200 ps
CPU time 2310.43 seconds
Started Apr 30 02:28:16 PM PDT 24
Finished Apr 30 03:06:47 PM PDT 24
Peak memory 264236 kb
Host smart-7b48f470-4c67-4b47-9423-fde761c3e32e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396416529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_err
or_mp.3396416529
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.1201320595
Short name T715
Test name
Test status
Simulation time 672826700 ps
CPU time 894.94 seconds
Started Apr 30 02:28:18 PM PDT 24
Finished Apr 30 02:43:14 PM PDT 24
Peak memory 272744 kb
Host smart-ed1883fd-21bb-44a3-9b98-6f934c116993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201320595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.1201320595
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.2734742491
Short name T97
Test name
Test status
Simulation time 2066024100 ps
CPU time 24.9 seconds
Started Apr 30 02:28:17 PM PDT 24
Finished Apr 30 02:28:42 PM PDT 24
Peak memory 264444 kb
Host smart-f7425a90-13fe-472b-9e28-a46c71a7135e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734742491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.2734742491
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.3953209347
Short name T749
Test name
Test status
Simulation time 10030041200 ps
CPU time 58.06 seconds
Started Apr 30 02:28:25 PM PDT 24
Finished Apr 30 02:29:24 PM PDT 24
Peak memory 285572 kb
Host smart-b9c67ecf-aab3-4dd3-a99b-79bf1e732815
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953209347 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.3953209347
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.1828537957
Short name T543
Test name
Test status
Simulation time 69079400 ps
CPU time 13.91 seconds
Started Apr 30 02:28:24 PM PDT 24
Finished Apr 30 02:28:38 PM PDT 24
Peak memory 257732 kb
Host smart-ac23308a-6a80-4c53-934e-c91596319d9a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828537957 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.1828537957
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.2630217636
Short name T100
Test name
Test status
Simulation time 40129212800 ps
CPU time 851.69 seconds
Started Apr 30 02:28:11 PM PDT 24
Finished Apr 30 02:42:23 PM PDT 24
Peak memory 262836 kb
Host smart-bf0904d5-1749-4f66-a68d-c8e25f5fc7b8
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630217636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.flash_ctrl_hw_rma_reset.2630217636
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.1602545090
Short name T680
Test name
Test status
Simulation time 8302658000 ps
CPU time 235.64 seconds
Started Apr 30 02:28:10 PM PDT 24
Finished Apr 30 02:32:06 PM PDT 24
Peak memory 262104 kb
Host smart-9cfd216a-80b7-4151-86c5-4452b2e96877
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602545090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.1602545090
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.2552129314
Short name T258
Test name
Test status
Simulation time 2480392800 ps
CPU time 203.5 seconds
Started Apr 30 02:28:16 PM PDT 24
Finished Apr 30 02:31:40 PM PDT 24
Peak memory 292376 kb
Host smart-507f8225-6b9f-4487-9860-0ae6bb3f0928
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552129314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_intr_rd.2552129314
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.4024208191
Short name T920
Test name
Test status
Simulation time 55478537200 ps
CPU time 271.98 seconds
Started Apr 30 02:28:16 PM PDT 24
Finished Apr 30 02:32:49 PM PDT 24
Peak memory 284176 kb
Host smart-216c992b-1bbb-4866-ab0f-46507c061430
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024208191 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.4024208191
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.1584946449
Short name T586
Test name
Test status
Simulation time 1013898500 ps
CPU time 76.67 seconds
Started Apr 30 02:28:19 PM PDT 24
Finished Apr 30 02:29:36 PM PDT 24
Peak memory 262704 kb
Host smart-db575740-ecbd-4f32-89f9-a5e330cc19a0
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584946449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.1584946449
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.3269849888
Short name T635
Test name
Test status
Simulation time 57406800 ps
CPU time 13.56 seconds
Started Apr 30 02:28:24 PM PDT 24
Finished Apr 30 02:28:38 PM PDT 24
Peak memory 264668 kb
Host smart-6de98026-7ed5-4e26-b7c8-ee3ede66079c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269849888 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.3269849888
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.1544324365
Short name T139
Test name
Test status
Simulation time 5359480900 ps
CPU time 459.77 seconds
Started Apr 30 02:28:19 PM PDT 24
Finished Apr 30 02:35:59 PM PDT 24
Peak memory 273244 kb
Host smart-abee4018-352d-4d93-afe6-7032a16b14ae
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544324365 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_mp_regions.1544324365
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.163088173
Short name T668
Test name
Test status
Simulation time 68816600 ps
CPU time 356.79 seconds
Started Apr 30 02:28:09 PM PDT 24
Finished Apr 30 02:34:07 PM PDT 24
Peak memory 264496 kb
Host smart-bf1f28b5-3b19-4e4c-903c-556e714ff56e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=163088173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.163088173
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.4262997125
Short name T851
Test name
Test status
Simulation time 839349900 ps
CPU time 1018.95 seconds
Started Apr 30 02:28:10 PM PDT 24
Finished Apr 30 02:45:09 PM PDT 24
Peak memory 286216 kb
Host smart-66d26758-6316-4637-901a-974d026b8118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262997125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.4262997125
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.1114615048
Short name T493
Test name
Test status
Simulation time 62581800 ps
CPU time 34.21 seconds
Started Apr 30 02:28:26 PM PDT 24
Finished Apr 30 02:29:00 PM PDT 24
Peak memory 271184 kb
Host smart-e308d8e0-cef2-426e-8967-7958fd863721
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114615048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.1114615048
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.2431645265
Short name T948
Test name
Test status
Simulation time 3898846000 ps
CPU time 121.35 seconds
Started Apr 30 02:28:19 PM PDT 24
Finished Apr 30 02:30:20 PM PDT 24
Peak memory 281192 kb
Host smart-b9543a0c-703d-4111-8943-0d1ebcb7d7c5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431645265 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_ro.2431645265
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.1917992988
Short name T616
Test name
Test status
Simulation time 4820896200 ps
CPU time 643.98 seconds
Started Apr 30 02:28:16 PM PDT 24
Finished Apr 30 02:39:00 PM PDT 24
Peak memory 309108 kb
Host smart-0db8579c-6669-4a59-a977-d72abc938dd5
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917992988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.flash_ctrl_rw.1917992988
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.38302811
Short name T273
Test name
Test status
Simulation time 108972700 ps
CPU time 100.15 seconds
Started Apr 30 02:28:11 PM PDT 24
Finished Apr 30 02:29:51 PM PDT 24
Peak memory 274612 kb
Host smart-38dd64bc-ccd5-4a83-9653-e757d62cf264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38302811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.38302811
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.1645297541
Short name T607
Test name
Test status
Simulation time 2669111400 ps
CPU time 240.71 seconds
Started Apr 30 02:28:17 PM PDT 24
Finished Apr 30 02:32:19 PM PDT 24
Peak memory 264708 kb
Host smart-73f29c91-7cec-474f-9bb8-b6f568658e15
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645297541 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.flash_ctrl_wo.1645297541
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.3296191256
Short name T494
Test name
Test status
Simulation time 41335200 ps
CPU time 13.45 seconds
Started Apr 30 02:34:56 PM PDT 24
Finished Apr 30 02:35:10 PM PDT 24
Peak memory 275608 kb
Host smart-433ed968-b2c4-4dff-b4be-29b2b3fc0962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296191256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.3296191256
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.3729912554
Short name T730
Test name
Test status
Simulation time 44236400 ps
CPU time 132.31 seconds
Started Apr 30 02:34:56 PM PDT 24
Finished Apr 30 02:37:09 PM PDT 24
Peak memory 259208 kb
Host smart-07199cb5-0bda-487b-9aed-7d5b59ee898d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729912554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o
tp_reset.3729912554
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.894355753
Short name T263
Test name
Test status
Simulation time 15337200 ps
CPU time 15.83 seconds
Started Apr 30 02:35:02 PM PDT 24
Finished Apr 30 02:35:18 PM PDT 24
Peak memory 275340 kb
Host smart-a83b21fc-d422-4a1e-a7c7-40ab970e71ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894355753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.894355753
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.3026320334
Short name T293
Test name
Test status
Simulation time 242819800 ps
CPU time 133.16 seconds
Started Apr 30 02:34:56 PM PDT 24
Finished Apr 30 02:37:10 PM PDT 24
Peak memory 259176 kb
Host smart-0694f0c4-9698-4ba2-aa9f-1864d3344122
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026320334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o
tp_reset.3026320334
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.4220614526
Short name T544
Test name
Test status
Simulation time 89785600 ps
CPU time 13.4 seconds
Started Apr 30 02:35:02 PM PDT 24
Finished Apr 30 02:35:16 PM PDT 24
Peak memory 275320 kb
Host smart-733d3345-9dac-4fa2-9bdb-d15e8b546963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220614526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.4220614526
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.893001265
Short name T117
Test name
Test status
Simulation time 37699600 ps
CPU time 111.35 seconds
Started Apr 30 02:35:02 PM PDT 24
Finished Apr 30 02:36:54 PM PDT 24
Peak memory 259308 kb
Host smart-6962b702-9778-42cc-8b26-3d5586133849
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893001265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_ot
p_reset.893001265
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.2139677723
Short name T509
Test name
Test status
Simulation time 42199400 ps
CPU time 15.77 seconds
Started Apr 30 02:35:02 PM PDT 24
Finished Apr 30 02:35:18 PM PDT 24
Peak memory 275352 kb
Host smart-a071893b-a49b-4e23-bd00-4eb7601ab8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139677723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.2139677723
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.1836549736
Short name T257
Test name
Test status
Simulation time 333288400 ps
CPU time 129.88 seconds
Started Apr 30 02:35:01 PM PDT 24
Finished Apr 30 02:37:12 PM PDT 24
Peak memory 259452 kb
Host smart-31cc5b1f-6f1d-4142-aa76-eb157eafb392
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836549736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_o
tp_reset.1836549736
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.315397764
Short name T646
Test name
Test status
Simulation time 43628500 ps
CPU time 16.41 seconds
Started Apr 30 02:35:02 PM PDT 24
Finished Apr 30 02:35:19 PM PDT 24
Peak memory 275236 kb
Host smart-50dbf758-7e25-42c8-8567-aa6b690088da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315397764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.315397764
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.3775753595
Short name T864
Test name
Test status
Simulation time 48505800 ps
CPU time 13.56 seconds
Started Apr 30 02:35:01 PM PDT 24
Finished Apr 30 02:35:15 PM PDT 24
Peak memory 275304 kb
Host smart-55c033fe-dd92-487c-b121-a4959b18705e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775753595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.3775753595
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.1422170683
Short name T326
Test name
Test status
Simulation time 147732200 ps
CPU time 134.86 seconds
Started Apr 30 02:35:01 PM PDT 24
Finished Apr 30 02:37:16 PM PDT 24
Peak memory 259388 kb
Host smart-fe40f450-9817-4b0e-b08e-5dc63bc15a53
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422170683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o
tp_reset.1422170683
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.4041370924
Short name T425
Test name
Test status
Simulation time 16467900 ps
CPU time 16.48 seconds
Started Apr 30 02:35:01 PM PDT 24
Finished Apr 30 02:35:18 PM PDT 24
Peak memory 275348 kb
Host smart-3116f9c8-1ca6-4bec-84f2-0a9ab2a287eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041370924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.4041370924
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.581445389
Short name T919
Test name
Test status
Simulation time 212757900 ps
CPU time 133.07 seconds
Started Apr 30 02:35:02 PM PDT 24
Finished Apr 30 02:37:15 PM PDT 24
Peak memory 259464 kb
Host smart-b6f66e0d-5cd6-49b4-af4d-21e3de41ce5b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581445389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_ot
p_reset.581445389
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.6003972
Short name T141
Test name
Test status
Simulation time 124871600 ps
CPU time 13.31 seconds
Started Apr 30 02:35:01 PM PDT 24
Finished Apr 30 02:35:15 PM PDT 24
Peak memory 274760 kb
Host smart-c89fc90f-5ba2-4432-8f69-35567aef6eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6003972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.6003972
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.228456828
Short name T712
Test name
Test status
Simulation time 168526500 ps
CPU time 135.41 seconds
Started Apr 30 02:35:03 PM PDT 24
Finished Apr 30 02:37:19 PM PDT 24
Peak memory 262720 kb
Host smart-6327f579-017d-47bd-837e-94163e6258c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228456828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_ot
p_reset.228456828
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.3796308387
Short name T583
Test name
Test status
Simulation time 27831800 ps
CPU time 15.91 seconds
Started Apr 30 02:35:00 PM PDT 24
Finished Apr 30 02:35:17 PM PDT 24
Peak memory 275564 kb
Host smart-a53aec97-897d-4f3f-9bf0-bb251ac232ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796308387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.3796308387
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.1465759985
Short name T290
Test name
Test status
Simulation time 72298300 ps
CPU time 130.2 seconds
Started Apr 30 02:35:02 PM PDT 24
Finished Apr 30 02:37:12 PM PDT 24
Peak memory 259252 kb
Host smart-775e92d4-edc9-423f-ad32-11d540c1f6a9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465759985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o
tp_reset.1465759985
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.1324212237
Short name T442
Test name
Test status
Simulation time 17583200 ps
CPU time 13.47 seconds
Started Apr 30 02:35:10 PM PDT 24
Finished Apr 30 02:35:23 PM PDT 24
Peak memory 274556 kb
Host smart-6519f0de-58ce-4334-a875-59474535ef11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324212237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.1324212237
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.3349766049
Short name T118
Test name
Test status
Simulation time 139247900 ps
CPU time 129.95 seconds
Started Apr 30 02:35:11 PM PDT 24
Finished Apr 30 02:37:22 PM PDT 24
Peak memory 259292 kb
Host smart-9625b48d-87f0-4da5-80e3-2ff5541f7f6b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349766049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o
tp_reset.3349766049
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.3814260264
Short name T9
Test name
Test status
Simulation time 27088700 ps
CPU time 14.03 seconds
Started Apr 30 02:28:38 PM PDT 24
Finished Apr 30 02:28:53 PM PDT 24
Peak memory 264580 kb
Host smart-f97145eb-995a-4b18-a78f-c41b017c33e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814260264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.3
814260264
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.358874903
Short name T430
Test name
Test status
Simulation time 59371600 ps
CPU time 15.89 seconds
Started Apr 30 02:28:40 PM PDT 24
Finished Apr 30 02:28:56 PM PDT 24
Peak memory 274764 kb
Host smart-71636497-27a1-4a63-aae1-0be9f829e63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358874903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.358874903
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.4102654737
Short name T832
Test name
Test status
Simulation time 26307307500 ps
CPU time 2674.13 seconds
Started Apr 30 02:28:30 PM PDT 24
Finished Apr 30 03:13:05 PM PDT 24
Peak memory 264492 kb
Host smart-a9cceb86-bc77-4fa3-ad77-f12e9ff67594
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102654737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_err
or_mp.4102654737
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.3025076983
Short name T665
Test name
Test status
Simulation time 2393035300 ps
CPU time 973 seconds
Started Apr 30 02:28:31 PM PDT 24
Finished Apr 30 02:44:44 PM PDT 24
Peak memory 271004 kb
Host smart-799446f5-2c3b-4eac-b135-5c5966f015ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025076983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.3025076983
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.2492120122
Short name T93
Test name
Test status
Simulation time 1186404400 ps
CPU time 23.46 seconds
Started Apr 30 02:28:29 PM PDT 24
Finished Apr 30 02:28:53 PM PDT 24
Peak memory 264444 kb
Host smart-5087805b-92f5-417f-8fe1-3f6e6f42c925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492120122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.2492120122
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.546560653
Short name T337
Test name
Test status
Simulation time 10033518200 ps
CPU time 103.97 seconds
Started Apr 30 02:28:40 PM PDT 24
Finished Apr 30 02:30:25 PM PDT 24
Peak memory 272476 kb
Host smart-48defc89-a3cc-4840-b0bb-618a402cc828
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546560653 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.546560653
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.2429603000
Short name T66
Test name
Test status
Simulation time 26021400 ps
CPU time 13.35 seconds
Started Apr 30 02:28:35 PM PDT 24
Finished Apr 30 02:28:49 PM PDT 24
Peak memory 257780 kb
Host smart-8024664e-05e4-400b-8409-67eb0cdb4a4b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429603000 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.2429603000
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.1757998167
Short name T125
Test name
Test status
Simulation time 420271011100 ps
CPU time 996.36 seconds
Started Apr 30 02:28:30 PM PDT 24
Finished Apr 30 02:45:07 PM PDT 24
Peak memory 263816 kb
Host smart-b1f770f8-14f5-49d1-9f06-fb547ff9c72c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757998167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.flash_ctrl_hw_rma_reset.1757998167
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.2882602298
Short name T492
Test name
Test status
Simulation time 2944310000 ps
CPU time 67.38 seconds
Started Apr 30 02:28:30 PM PDT 24
Finished Apr 30 02:29:38 PM PDT 24
Peak memory 261780 kb
Host smart-3d45ab4b-a899-406f-9f78-d02f31a82e32
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882602298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h
w_sec_otp.2882602298
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.2160741923
Short name T947
Test name
Test status
Simulation time 5168722100 ps
CPU time 191.96 seconds
Started Apr 30 02:28:36 PM PDT 24
Finished Apr 30 02:31:48 PM PDT 24
Peak memory 292500 kb
Host smart-3b7622cc-445c-48ff-a772-9cbf4faffed7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160741923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_intr_rd.2160741923
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.1007816737
Short name T496
Test name
Test status
Simulation time 8480295400 ps
CPU time 209.9 seconds
Started Apr 30 02:28:40 PM PDT 24
Finished Apr 30 02:32:11 PM PDT 24
Peak memory 289196 kb
Host smart-3dcdda99-aa96-4f31-a4d4-5bca1192a700
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007816737 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.1007816737
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.126544704
Short name T761
Test name
Test status
Simulation time 4532169400 ps
CPU time 58.92 seconds
Started Apr 30 02:28:28 PM PDT 24
Finished Apr 30 02:29:28 PM PDT 24
Peak memory 262712 kb
Host smart-5f872374-b737-40f0-b333-c1feee1af8a5
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126544704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.126544704
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.2507993289
Short name T685
Test name
Test status
Simulation time 15449100 ps
CPU time 13.47 seconds
Started Apr 30 02:28:39 PM PDT 24
Finished Apr 30 02:28:53 PM PDT 24
Peak memory 264696 kb
Host smart-1b41ee0a-b69d-45fd-8c4a-5ccba61fdeaa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507993289 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.2507993289
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.3700541005
Short name T805
Test name
Test status
Simulation time 20123939800 ps
CPU time 126.53 seconds
Started Apr 30 02:28:31 PM PDT 24
Finished Apr 30 02:30:38 PM PDT 24
Peak memory 260584 kb
Host smart-70656470-0cbb-4cd3-9d14-24cc37bd5fa8
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700541005 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.flash_ctrl_mp_regions.3700541005
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.4200841496
Short name T910
Test name
Test status
Simulation time 297495900 ps
CPU time 129.34 seconds
Started Apr 30 02:28:31 PM PDT 24
Finished Apr 30 02:30:41 PM PDT 24
Peak memory 259284 kb
Host smart-fca1b9b7-ecd2-49c0-8080-42ea90158158
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200841496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot
p_reset.4200841496
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.2673241117
Short name T796
Test name
Test status
Simulation time 129173100 ps
CPU time 318.22 seconds
Started Apr 30 02:28:30 PM PDT 24
Finished Apr 30 02:33:49 PM PDT 24
Peak memory 261764 kb
Host smart-530bc7bf-ef3d-437a-8794-f18b2d9beea6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2673241117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.2673241117
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.3841138087
Short name T733
Test name
Test status
Simulation time 739402000 ps
CPU time 477.14 seconds
Started Apr 30 02:28:28 PM PDT 24
Finished Apr 30 02:36:26 PM PDT 24
Peak memory 282004 kb
Host smart-cf05a6e5-b64a-4561-8ab4-d4ef32aa59e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841138087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.3841138087
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.4010829035
Short name T364
Test name
Test status
Simulation time 1126259600 ps
CPU time 32.91 seconds
Started Apr 30 02:28:38 PM PDT 24
Finished Apr 30 02:29:12 PM PDT 24
Peak memory 272968 kb
Host smart-de41b044-3309-4702-997c-51cc13c5f7ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010829035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_re_evict.4010829035
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.489035070
Short name T16
Test name
Test status
Simulation time 2528985000 ps
CPU time 142.44 seconds
Started Apr 30 02:28:29 PM PDT 24
Finished Apr 30 02:30:52 PM PDT 24
Peak memory 281120 kb
Host smart-a7d7d235-4184-45fa-bb0d-1cc3db2d59f7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489035070 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.flash_ctrl_ro.489035070
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.3607832161
Short name T191
Test name
Test status
Simulation time 6996610800 ps
CPU time 173.64 seconds
Started Apr 30 02:28:39 PM PDT 24
Finished Apr 30 02:31:33 PM PDT 24
Peak memory 284528 kb
Host smart-3adf7cae-2586-4c53-a090-7c07fd772311
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3607832161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.3607832161
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.1515150842
Short name T656
Test name
Test status
Simulation time 728430400 ps
CPU time 139.07 seconds
Started Apr 30 02:28:37 PM PDT 24
Finished Apr 30 02:30:56 PM PDT 24
Peak memory 281096 kb
Host smart-5cb95651-431a-4bc3-bf1a-c94d6adee095
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515150842 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.1515150842
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.1118868193
Short name T754
Test name
Test status
Simulation time 3894514200 ps
CPU time 585.56 seconds
Started Apr 30 02:28:37 PM PDT 24
Finished Apr 30 02:38:23 PM PDT 24
Peak memory 309148 kb
Host smart-bc2175b1-fcd3-49d9-851f-7e525c6ad645
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118868193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.flash_ctrl_rw.1118868193
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.199507014
Short name T410
Test name
Test status
Simulation time 415585400 ps
CPU time 58.68 seconds
Started Apr 30 02:28:38 PM PDT 24
Finished Apr 30 02:29:38 PM PDT 24
Peak memory 263996 kb
Host smart-06ec6efe-2b21-4d3f-a524-a3ec328c10b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199507014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.199507014
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.3242801916
Short name T433
Test name
Test status
Simulation time 316261400 ps
CPU time 52.94 seconds
Started Apr 30 02:28:23 PM PDT 24
Finished Apr 30 02:29:17 PM PDT 24
Peak memory 269920 kb
Host smart-f7f8cd20-ced9-469f-9b33-12c489b2b4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242801916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.3242801916
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.816669879
Short name T390
Test name
Test status
Simulation time 16125788600 ps
CPU time 232.36 seconds
Started Apr 30 02:28:30 PM PDT 24
Finished Apr 30 02:32:23 PM PDT 24
Peak memory 259956 kb
Host smart-98a1b194-47d3-45e9-88fa-817763523afb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816669879 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.flash_ctrl_wo.816669879
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.194710572
Short name T931
Test name
Test status
Simulation time 15916200 ps
CPU time 16.07 seconds
Started Apr 30 02:35:08 PM PDT 24
Finished Apr 30 02:35:25 PM PDT 24
Peak memory 274544 kb
Host smart-dd23d4c5-295c-43ff-b5a4-c6311cec387e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194710572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.194710572
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.516112190
Short name T738
Test name
Test status
Simulation time 117882500 ps
CPU time 112.7 seconds
Started Apr 30 02:35:10 PM PDT 24
Finished Apr 30 02:37:03 PM PDT 24
Peak memory 259348 kb
Host smart-04ce732a-3c79-427a-ab53-4d902034055e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516112190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_ot
p_reset.516112190
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.3458425642
Short name T521
Test name
Test status
Simulation time 17523400 ps
CPU time 15.69 seconds
Started Apr 30 02:35:09 PM PDT 24
Finished Apr 30 02:35:25 PM PDT 24
Peak memory 275504 kb
Host smart-91ffa185-085b-449f-aae6-1018909b2409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458425642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.3458425642
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.3714153634
Short name T487
Test name
Test status
Simulation time 49277800 ps
CPU time 15.8 seconds
Started Apr 30 02:35:11 PM PDT 24
Finished Apr 30 02:35:27 PM PDT 24
Peak memory 275388 kb
Host smart-0d1327ec-5b84-4f60-8a0e-bb09797593b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714153634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.3714153634
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.3574607542
Short name T491
Test name
Test status
Simulation time 450687000 ps
CPU time 130.84 seconds
Started Apr 30 02:35:09 PM PDT 24
Finished Apr 30 02:37:20 PM PDT 24
Peak memory 259252 kb
Host smart-aa932fc7-e463-4fef-96d3-e8f0ff006393
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574607542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.3574607542
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.4250848509
Short name T444
Test name
Test status
Simulation time 231038100 ps
CPU time 16.18 seconds
Started Apr 30 02:35:10 PM PDT 24
Finished Apr 30 02:35:26 PM PDT 24
Peak memory 274740 kb
Host smart-4c48c841-a356-4591-944d-5edcfc793566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250848509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.4250848509
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.2420874335
Short name T499
Test name
Test status
Simulation time 137541000 ps
CPU time 110.94 seconds
Started Apr 30 02:35:09 PM PDT 24
Finished Apr 30 02:37:00 PM PDT 24
Peak memory 263128 kb
Host smart-60dad276-c15d-479a-ae93-fec0ccf1dc84
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420874335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o
tp_reset.2420874335
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.1238230598
Short name T387
Test name
Test status
Simulation time 21928300 ps
CPU time 15.9 seconds
Started Apr 30 02:35:12 PM PDT 24
Finished Apr 30 02:35:28 PM PDT 24
Peak memory 274716 kb
Host smart-a246dc18-2763-4acd-b091-64fdfa0e7137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238230598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.1238230598
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.2446250988
Short name T108
Test name
Test status
Simulation time 42525500 ps
CPU time 134.95 seconds
Started Apr 30 02:35:09 PM PDT 24
Finished Apr 30 02:37:25 PM PDT 24
Peak memory 263228 kb
Host smart-d26c338b-8212-4486-8ea7-f49f15a61a70
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446250988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.2446250988
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.2123158089
Short name T667
Test name
Test status
Simulation time 15506000 ps
CPU time 15.77 seconds
Started Apr 30 02:35:09 PM PDT 24
Finished Apr 30 02:35:26 PM PDT 24
Peak memory 274636 kb
Host smart-2a83df13-be1f-4871-b013-b1bd4fc9af63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123158089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.2123158089
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.1862392135
Short name T121
Test name
Test status
Simulation time 143858100 ps
CPU time 111.5 seconds
Started Apr 30 02:35:11 PM PDT 24
Finished Apr 30 02:37:03 PM PDT 24
Peak memory 259224 kb
Host smart-a0a5c0e6-4cb7-4a58-b0eb-ff890dd23da9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862392135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o
tp_reset.1862392135
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.1412935856
Short name T463
Test name
Test status
Simulation time 13842500 ps
CPU time 15.83 seconds
Started Apr 30 02:35:11 PM PDT 24
Finished Apr 30 02:35:27 PM PDT 24
Peak memory 274512 kb
Host smart-b508a8f8-53de-4e0e-8fb6-b363ee76771f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412935856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.1412935856
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.3202554551
Short name T889
Test name
Test status
Simulation time 127525500 ps
CPU time 109.07 seconds
Started Apr 30 02:35:10 PM PDT 24
Finished Apr 30 02:36:59 PM PDT 24
Peak memory 259160 kb
Host smart-9a38af35-8219-4710-839e-4d82ea731f7e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202554551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_o
tp_reset.3202554551
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.436140235
Short name T434
Test name
Test status
Simulation time 24747800 ps
CPU time 16.04 seconds
Started Apr 30 02:35:20 PM PDT 24
Finished Apr 30 02:35:36 PM PDT 24
Peak memory 274796 kb
Host smart-f98fc109-320a-4bf1-8d1f-9cc85519f3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436140235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.436140235
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.4248262855
Short name T120
Test name
Test status
Simulation time 228979000 ps
CPU time 131.02 seconds
Started Apr 30 02:35:09 PM PDT 24
Finished Apr 30 02:37:21 PM PDT 24
Peak memory 264020 kb
Host smart-55f59bb8-dd3e-42f4-8c85-6a9c6516582e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248262855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o
tp_reset.4248262855
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.2634461328
Short name T300
Test name
Test status
Simulation time 59892000 ps
CPU time 13.57 seconds
Started Apr 30 02:35:20 PM PDT 24
Finished Apr 30 02:35:34 PM PDT 24
Peak memory 275204 kb
Host smart-f00f2e89-70b4-40cb-8fa0-1e9dea6f4f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634461328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.2634461328
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.4040507965
Short name T735
Test name
Test status
Simulation time 43937600 ps
CPU time 132.33 seconds
Started Apr 30 02:35:20 PM PDT 24
Finished Apr 30 02:37:33 PM PDT 24
Peak memory 259380 kb
Host smart-94391e13-7124-4c6b-ba7c-b10a64af4ae2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040507965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o
tp_reset.4040507965
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.2067455078
Short name T873
Test name
Test status
Simulation time 28241700 ps
CPU time 15.82 seconds
Started Apr 30 02:35:20 PM PDT 24
Finished Apr 30 02:35:36 PM PDT 24
Peak memory 275260 kb
Host smart-791ee64d-acaf-46c2-b102-a44d4f4ff4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067455078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.2067455078
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.1323775868
Short name T456
Test name
Test status
Simulation time 36721600 ps
CPU time 135.35 seconds
Started Apr 30 02:35:20 PM PDT 24
Finished Apr 30 02:37:35 PM PDT 24
Peak memory 258976 kb
Host smart-808ebafc-daf2-4673-a1c9-547e99e53eef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323775868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o
tp_reset.1323775868
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.2359113868
Short name T563
Test name
Test status
Simulation time 32849300 ps
CPU time 14.23 seconds
Started Apr 30 02:28:58 PM PDT 24
Finished Apr 30 02:29:17 PM PDT 24
Peak memory 257688 kb
Host smart-fd9db271-3c9e-41e3-bfb6-46cb0814bcb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359113868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.2
359113868
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.1006028466
Short name T62
Test name
Test status
Simulation time 13928800 ps
CPU time 15.85 seconds
Started Apr 30 02:28:55 PM PDT 24
Finished Apr 30 02:29:14 PM PDT 24
Peak memory 275304 kb
Host smart-f3e89e53-16ba-47fe-858e-12ae8d7a6922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006028466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.1006028466
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.1859579915
Short name T217
Test name
Test status
Simulation time 8915398300 ps
CPU time 2224.5 seconds
Started Apr 30 02:28:56 PM PDT 24
Finished Apr 30 03:06:05 PM PDT 24
Peak memory 263740 kb
Host smart-47a4ff8e-01de-4c7b-a803-407671a5f748
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859579915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_err
or_mp.1859579915
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.1097081316
Short name T611
Test name
Test status
Simulation time 1377474400 ps
CPU time 798.45 seconds
Started Apr 30 02:28:43 PM PDT 24
Finished Apr 30 02:42:02 PM PDT 24
Peak memory 264488 kb
Host smart-3c1f936c-14eb-4d37-aa65-85306910487b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097081316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.1097081316
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.3760222163
Short name T548
Test name
Test status
Simulation time 170085000 ps
CPU time 18.33 seconds
Started Apr 30 02:28:41 PM PDT 24
Finished Apr 30 02:29:01 PM PDT 24
Peak memory 264664 kb
Host smart-056e2ebb-90b9-44f4-9732-d122a85e51fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760222163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.3760222163
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3816724375
Short name T36
Test name
Test status
Simulation time 10018391100 ps
CPU time 171.86 seconds
Started Apr 30 02:28:54 PM PDT 24
Finished Apr 30 02:31:49 PM PDT 24
Peak memory 264660 kb
Host smart-09a1f777-a044-4e4a-8210-10a6e78b20c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816724375 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.3816724375
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.3485980491
Short name T197
Test name
Test status
Simulation time 46905300 ps
CPU time 13.59 seconds
Started Apr 30 02:28:54 PM PDT 24
Finished Apr 30 02:29:10 PM PDT 24
Peak memory 264620 kb
Host smart-991647b7-edc8-47af-993f-6c030b3814de
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485980491 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.3485980491
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.1335029258
Short name T28
Test name
Test status
Simulation time 40128710500 ps
CPU time 859.32 seconds
Started Apr 30 02:28:44 PM PDT 24
Finished Apr 30 02:43:04 PM PDT 24
Peak memory 262452 kb
Host smart-37e98f74-64c6-4c7f-a2da-79f55706ecff
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335029258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.flash_ctrl_hw_rma_reset.1335029258
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.3415984507
Short name T951
Test name
Test status
Simulation time 1934404400 ps
CPU time 174.13 seconds
Started Apr 30 02:28:56 PM PDT 24
Finished Apr 30 02:31:54 PM PDT 24
Peak memory 292428 kb
Host smart-ceaef166-9edf-4e16-9f44-b242ecd4a928
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415984507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_intr_rd.3415984507
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.994416887
Short name T927
Test name
Test status
Simulation time 14784009200 ps
CPU time 215.68 seconds
Started Apr 30 02:28:49 PM PDT 24
Finished Apr 30 02:32:26 PM PDT 24
Peak memory 290764 kb
Host smart-d6340263-b66c-4c52-a083-b0459199a6eb
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994416887 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.994416887
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.3350661372
Short name T549
Test name
Test status
Simulation time 16024808400 ps
CPU time 89.67 seconds
Started Apr 30 02:28:51 PM PDT 24
Finished Apr 30 02:30:22 PM PDT 24
Peak memory 260008 kb
Host smart-1c4ca964-8383-49b3-b565-1dcd60531876
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350661372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.3350661372
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.2081552251
Short name T104
Test name
Test status
Simulation time 15557000 ps
CPU time 14.62 seconds
Started Apr 30 02:28:56 PM PDT 24
Finished Apr 30 02:29:15 PM PDT 24
Peak memory 263832 kb
Host smart-09018fc6-1213-4d04-a10d-e34d115ddb65
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081552251 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.2081552251
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.1829394787
Short name T637
Test name
Test status
Simulation time 146812700 ps
CPU time 131.36 seconds
Started Apr 30 02:28:43 PM PDT 24
Finished Apr 30 02:30:55 PM PDT 24
Peak memory 259368 kb
Host smart-89261b31-5325-4d3f-be2b-6d796b4beeb6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829394787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot
p_reset.1829394787
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.2547997810
Short name T515
Test name
Test status
Simulation time 57127800 ps
CPU time 237.62 seconds
Started Apr 30 02:28:41 PM PDT 24
Finished Apr 30 02:32:40 PM PDT 24
Peak memory 261080 kb
Host smart-eef5a8b5-bfca-4221-99fd-aefa5dd929f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2547997810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.2547997810
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.3591285153
Short name T940
Test name
Test status
Simulation time 146354700 ps
CPU time 134.87 seconds
Started Apr 30 02:28:42 PM PDT 24
Finished Apr 30 02:30:58 PM PDT 24
Peak memory 271372 kb
Host smart-11f8c376-ebcf-4732-b073-680a7db05b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591285153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.3591285153
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.3950777064
Short name T755
Test name
Test status
Simulation time 1455860100 ps
CPU time 38.17 seconds
Started Apr 30 02:28:50 PM PDT 24
Finished Apr 30 02:29:29 PM PDT 24
Peak memory 274056 kb
Host smart-77b4dc3c-cbed-4514-8394-1024a345203f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950777064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.3950777064
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.2387059334
Short name T545
Test name
Test status
Simulation time 2339093500 ps
CPU time 123.68 seconds
Started Apr 30 02:28:50 PM PDT 24
Finished Apr 30 02:30:55 PM PDT 24
Peak memory 288832 kb
Host smart-70f209e9-aedb-42bf-8c83-bae792099939
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387059334 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_ro.2387059334
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.4244710873
Short name T190
Test name
Test status
Simulation time 748584400 ps
CPU time 165.76 seconds
Started Apr 30 02:28:50 PM PDT 24
Finished Apr 30 02:31:36 PM PDT 24
Peak memory 281472 kb
Host smart-85046a03-71ca-4601-83c0-4d0c67ba6660
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4244710873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.4244710873
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.2603298973
Short name T746
Test name
Test status
Simulation time 800157200 ps
CPU time 143.93 seconds
Started Apr 30 02:28:51 PM PDT 24
Finished Apr 30 02:31:16 PM PDT 24
Peak memory 281080 kb
Host smart-fb2c1e09-504f-459b-ac41-b95d4e0a8010
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603298973 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.2603298973
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.608479660
Short name T619
Test name
Test status
Simulation time 4491688000 ps
CPU time 659.18 seconds
Started Apr 30 02:28:51 PM PDT 24
Finished Apr 30 02:39:52 PM PDT 24
Peak memory 313844 kb
Host smart-3388e31a-1868-4c84-88da-e705541957bf
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608479660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.flash_ctrl_rw.608479660
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.3114930040
Short name T48
Test name
Test status
Simulation time 79235500 ps
CPU time 28.97 seconds
Started Apr 30 02:28:53 PM PDT 24
Finished Apr 30 02:29:25 PM PDT 24
Peak memory 275064 kb
Host smart-938c8c07-1cf0-41e1-84b7-3dd42f033689
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114930040 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.3114930040
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.4022027767
Short name T550
Test name
Test status
Simulation time 1939149800 ps
CPU time 72.09 seconds
Started Apr 30 02:28:55 PM PDT 24
Finished Apr 30 02:30:10 PM PDT 24
Peak memory 262624 kb
Host smart-27cbfb84-5c73-4bdf-b850-8db3a9a01f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022027767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.4022027767
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.2778352993
Short name T628
Test name
Test status
Simulation time 24687300 ps
CPU time 72.59 seconds
Started Apr 30 02:28:42 PM PDT 24
Finished Apr 30 02:29:55 PM PDT 24
Peak memory 274352 kb
Host smart-a12412ac-47a6-4e3b-8573-15ff9c2c0dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778352993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.2778352993
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.1995664615
Short name T747
Test name
Test status
Simulation time 4949050800 ps
CPU time 222.87 seconds
Started Apr 30 02:28:51 PM PDT 24
Finished Apr 30 02:32:35 PM PDT 24
Peak memory 264736 kb
Host smart-332d2304-a5b4-4c54-932c-290fb5ec8199
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995664615 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.flash_ctrl_wo.1995664615
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.2342783671
Short name T482
Test name
Test status
Simulation time 19341200 ps
CPU time 15.89 seconds
Started Apr 30 02:35:19 PM PDT 24
Finished Apr 30 02:35:35 PM PDT 24
Peak memory 275176 kb
Host smart-7cc2fdbc-a9b6-4e06-84f5-15d355a1dd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342783671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.2342783671
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.3808394736
Short name T937
Test name
Test status
Simulation time 76449700 ps
CPU time 130.34 seconds
Started Apr 30 02:35:21 PM PDT 24
Finished Apr 30 02:37:32 PM PDT 24
Peak memory 259052 kb
Host smart-31cdb30b-141b-4f23-b021-e0d0b1089cde
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808394736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o
tp_reset.3808394736
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.992100327
Short name T470
Test name
Test status
Simulation time 13805300 ps
CPU time 13.5 seconds
Started Apr 30 02:35:19 PM PDT 24
Finished Apr 30 02:35:33 PM PDT 24
Peak memory 274800 kb
Host smart-e66a8514-b194-4f65-9410-3bc75e4b323e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992100327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.992100327
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.1774403589
Short name T792
Test name
Test status
Simulation time 138597000 ps
CPU time 109.11 seconds
Started Apr 30 02:35:19 PM PDT 24
Finished Apr 30 02:37:08 PM PDT 24
Peak memory 259332 kb
Host smart-2ed7437c-a842-4653-b3aa-9f76554b8887
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774403589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o
tp_reset.1774403589
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.1803226068
Short name T517
Test name
Test status
Simulation time 21261100 ps
CPU time 15.68 seconds
Started Apr 30 02:35:18 PM PDT 24
Finished Apr 30 02:35:34 PM PDT 24
Peak memory 275248 kb
Host smart-43995b2c-09e1-48ff-bc3b-01b366f128c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803226068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.1803226068
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.990087828
Short name T788
Test name
Test status
Simulation time 84474700 ps
CPU time 133.09 seconds
Started Apr 30 02:35:22 PM PDT 24
Finished Apr 30 02:37:35 PM PDT 24
Peak memory 259156 kb
Host smart-fa4178eb-8846-487e-95e1-d79ba28e7354
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990087828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_ot
p_reset.990087828
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.159772532
Short name T688
Test name
Test status
Simulation time 16769500 ps
CPU time 16.08 seconds
Started Apr 30 02:35:27 PM PDT 24
Finished Apr 30 02:35:44 PM PDT 24
Peak memory 274840 kb
Host smart-a0a1e48d-c0c2-460e-a7d4-929ba5542445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159772532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.159772532
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.2711386708
Short name T123
Test name
Test status
Simulation time 160391400 ps
CPU time 111.44 seconds
Started Apr 30 02:35:18 PM PDT 24
Finished Apr 30 02:37:10 PM PDT 24
Peak memory 259164 kb
Host smart-f7772140-2bce-444d-b523-99589537b3dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711386708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.2711386708
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.570911247
Short name T902
Test name
Test status
Simulation time 30349500 ps
CPU time 15.7 seconds
Started Apr 30 02:35:27 PM PDT 24
Finished Apr 30 02:35:43 PM PDT 24
Peak memory 275416 kb
Host smart-133511b1-2ecd-48ab-8d31-e944a52624d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570911247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.570911247
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.1105959905
Short name T582
Test name
Test status
Simulation time 40614600 ps
CPU time 131.86 seconds
Started Apr 30 02:35:27 PM PDT 24
Finished Apr 30 02:37:39 PM PDT 24
Peak memory 259152 kb
Host smart-46096af7-31b2-49a5-9b18-5f79720413a7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105959905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o
tp_reset.1105959905
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.984396032
Short name T537
Test name
Test status
Simulation time 21778300 ps
CPU time 15.69 seconds
Started Apr 30 02:35:26 PM PDT 24
Finished Apr 30 02:35:42 PM PDT 24
Peak memory 274732 kb
Host smart-4fc31804-9890-4d49-9cb0-ce0657a12035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984396032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.984396032
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.2828917156
Short name T631
Test name
Test status
Simulation time 354239800 ps
CPU time 131.73 seconds
Started Apr 30 02:35:27 PM PDT 24
Finished Apr 30 02:37:39 PM PDT 24
Peak memory 259488 kb
Host smart-d98092ba-b262-40ae-a4f1-15da2802e3fb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828917156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o
tp_reset.2828917156
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.424948286
Short name T490
Test name
Test status
Simulation time 15058000 ps
CPU time 13.43 seconds
Started Apr 30 02:35:28 PM PDT 24
Finished Apr 30 02:35:42 PM PDT 24
Peak memory 274576 kb
Host smart-3a184e8c-bb5a-40ab-a755-a2ed377012ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424948286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.424948286
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.596301607
Short name T880
Test name
Test status
Simulation time 485930000 ps
CPU time 112.91 seconds
Started Apr 30 02:35:27 PM PDT 24
Finished Apr 30 02:37:20 PM PDT 24
Peak memory 263584 kb
Host smart-caa8a835-9c16-4a3a-a7df-5cda76f9c6f8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596301607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_ot
p_reset.596301607
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.2109185263
Short name T711
Test name
Test status
Simulation time 135753000 ps
CPU time 13.41 seconds
Started Apr 30 02:35:26 PM PDT 24
Finished Apr 30 02:35:40 PM PDT 24
Peak memory 274712 kb
Host smart-f9652c20-d4f4-40d2-b6df-46ad87b5f5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109185263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.2109185263
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.3382814858
Short name T321
Test name
Test status
Simulation time 70297400 ps
CPU time 130.81 seconds
Started Apr 30 02:35:26 PM PDT 24
Finished Apr 30 02:37:37 PM PDT 24
Peak memory 259396 kb
Host smart-f8279409-dbf2-4da3-bfb0-bf0c3025c8d4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382814858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.3382814858
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.3242658263
Short name T272
Test name
Test status
Simulation time 53050600 ps
CPU time 13.53 seconds
Started Apr 30 02:35:27 PM PDT 24
Finished Apr 30 02:35:41 PM PDT 24
Peak memory 275672 kb
Host smart-1893d119-ed45-40d4-88b6-104429e79dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242658263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.3242658263
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.417513334
Short name T424
Test name
Test status
Simulation time 74966500 ps
CPU time 130.48 seconds
Started Apr 30 02:35:28 PM PDT 24
Finished Apr 30 02:37:39 PM PDT 24
Peak memory 259304 kb
Host smart-a234f602-7c3f-461c-b304-394d7451ef5e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417513334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_ot
p_reset.417513334
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.2601801207
Short name T296
Test name
Test status
Simulation time 48152500 ps
CPU time 13.38 seconds
Started Apr 30 02:35:25 PM PDT 24
Finished Apr 30 02:35:39 PM PDT 24
Peak memory 275340 kb
Host smart-0482a288-7ef1-456d-8ce8-0f1f969c2d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601801207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.2601801207
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.2353625199
Short name T806
Test name
Test status
Simulation time 169423900 ps
CPU time 129.53 seconds
Started Apr 30 02:35:25 PM PDT 24
Finished Apr 30 02:37:35 PM PDT 24
Peak memory 263592 kb
Host smart-fa5bb1d5-cce6-482d-9e5b-657caa9453ac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353625199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o
tp_reset.2353625199
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.679765360
Short name T587
Test name
Test status
Simulation time 50273700 ps
CPU time 13.97 seconds
Started Apr 30 02:29:19 PM PDT 24
Finished Apr 30 02:29:39 PM PDT 24
Peak memory 264644 kb
Host smart-1340a943-08fe-476c-9888-ed9489f8ec97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679765360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.679765360
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.2583044835
Short name T254
Test name
Test status
Simulation time 14090100 ps
CPU time 15.43 seconds
Started Apr 30 02:29:20 PM PDT 24
Finished Apr 30 02:29:41 PM PDT 24
Peak memory 274764 kb
Host smart-011c35b7-f863-4fa6-a75c-005bbbe10750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583044835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.2583044835
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.1816353871
Short name T450
Test name
Test status
Simulation time 17070300 ps
CPU time 22.06 seconds
Started Apr 30 02:29:13 PM PDT 24
Finished Apr 30 02:29:42 PM PDT 24
Peak memory 264744 kb
Host smart-9a3ff7ec-3fb5-47f6-a914-241fda2fee0a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816353871 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.1816353871
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.2011866151
Short name T636
Test name
Test status
Simulation time 4195592300 ps
CPU time 2169.07 seconds
Started Apr 30 02:29:02 PM PDT 24
Finished Apr 30 03:05:19 PM PDT 24
Peak memory 264488 kb
Host smart-dc80061e-b483-469e-a1bb-8fa661debfe5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011866151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_err
or_mp.2011866151
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.2448923931
Short name T834
Test name
Test status
Simulation time 313807300 ps
CPU time 773.13 seconds
Started Apr 30 02:29:04 PM PDT 24
Finished Apr 30 02:42:05 PM PDT 24
Peak memory 272752 kb
Host smart-b5d25e22-0ebd-4916-9242-9964fa830eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448923931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.2448923931
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.2784272109
Short name T99
Test name
Test status
Simulation time 1448565100 ps
CPU time 28.84 seconds
Started Apr 30 02:28:57 PM PDT 24
Finished Apr 30 02:29:30 PM PDT 24
Peak memory 264376 kb
Host smart-a28c7946-bd2d-4b22-b0a7-c59706bd3510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784272109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.2784272109
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.1570700488
Short name T552
Test name
Test status
Simulation time 18148500 ps
CPU time 13.35 seconds
Started Apr 30 02:29:24 PM PDT 24
Finished Apr 30 02:29:43 PM PDT 24
Peak memory 257740 kb
Host smart-a490058e-989d-4c58-9bf6-d01168e50546
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570700488 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.1570700488
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.2483888439
Short name T852
Test name
Test status
Simulation time 40117462900 ps
CPU time 827.32 seconds
Started Apr 30 02:28:57 PM PDT 24
Finished Apr 30 02:42:49 PM PDT 24
Peak memory 262832 kb
Host smart-2877f370-d5fa-4ca4-847a-f3199fddb73c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483888439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.flash_ctrl_hw_rma_reset.2483888439
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.3001498426
Short name T618
Test name
Test status
Simulation time 1351042900 ps
CPU time 104.8 seconds
Started Apr 30 02:28:57 PM PDT 24
Finished Apr 30 02:30:47 PM PDT 24
Peak memory 262156 kb
Host smart-fb7fd986-0e38-4ff4-ab95-a5895dafea85
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001498426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.3001498426
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1182328620
Short name T930
Test name
Test status
Simulation time 14224474000 ps
CPU time 231.24 seconds
Started Apr 30 02:29:12 PM PDT 24
Finished Apr 30 02:33:10 PM PDT 24
Peak memory 284280 kb
Host smart-c47dbeaf-2194-412b-a8f4-453e1355e9bf
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182328620 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.1182328620
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.3970767836
Short name T694
Test name
Test status
Simulation time 6555286700 ps
CPU time 71.76 seconds
Started Apr 30 02:29:05 PM PDT 24
Finished Apr 30 02:30:24 PM PDT 24
Peak memory 259168 kb
Host smart-3c764e8c-f0b1-48ed-b7cf-a184baccca2b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970767836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.3970767836
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.2038133679
Short name T573
Test name
Test status
Simulation time 216213200 ps
CPU time 13.43 seconds
Started Apr 30 02:29:18 PM PDT 24
Finished Apr 30 02:29:38 PM PDT 24
Peak memory 259204 kb
Host smart-77579e82-daee-4e15-8caf-aa4d1be228df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038133679 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.2038133679
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.2835231292
Short name T770
Test name
Test status
Simulation time 36152093500 ps
CPU time 481.03 seconds
Started Apr 30 02:28:59 PM PDT 24
Finished Apr 30 02:37:07 PM PDT 24
Peak memory 273164 kb
Host smart-fb84194a-2701-4053-a393-c87c6ba78084
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835231292 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_mp_regions.2835231292
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.274540175
Short name T539
Test name
Test status
Simulation time 41586400 ps
CPU time 131.14 seconds
Started Apr 30 02:28:57 PM PDT 24
Finished Apr 30 02:31:13 PM PDT 24
Peak memory 259408 kb
Host smart-81448d38-6c84-47a5-ae3d-b320c943b20d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274540175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_otp
_reset.274540175
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.3625909169
Short name T773
Test name
Test status
Simulation time 54306100 ps
CPU time 109.1 seconds
Started Apr 30 02:28:56 PM PDT 24
Finished Apr 30 02:30:49 PM PDT 24
Peak memory 260796 kb
Host smart-dc4f8112-1dd0-45fc-b9f7-b04f9020607b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3625909169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.3625909169
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.895186474
Short name T473
Test name
Test status
Simulation time 222589400 ps
CPU time 664.71 seconds
Started Apr 30 02:28:57 PM PDT 24
Finished Apr 30 02:40:07 PM PDT 24
Peak memory 283148 kb
Host smart-2cf57db5-002f-40a9-8333-f1077b76da17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895186474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.895186474
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.3674923706
Short name T84
Test name
Test status
Simulation time 95735300 ps
CPU time 34.89 seconds
Started Apr 30 02:29:10 PM PDT 24
Finished Apr 30 02:29:53 PM PDT 24
Peak memory 271220 kb
Host smart-3f2f3fa2-1d3f-4710-b4ef-5553d79ce1f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674923706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.3674923706
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.1901384062
Short name T283
Test name
Test status
Simulation time 1836221100 ps
CPU time 115.91 seconds
Started Apr 30 02:29:03 PM PDT 24
Finished Apr 30 02:31:07 PM PDT 24
Peak memory 281088 kb
Host smart-87b31b96-f20c-43c2-b6c9-394dc4cf325d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901384062 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_ro.1901384062
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.480264348
Short name T198
Test name
Test status
Simulation time 12049875900 ps
CPU time 140.73 seconds
Started Apr 30 02:29:05 PM PDT 24
Finished Apr 30 02:31:33 PM PDT 24
Peak memory 281292 kb
Host smart-db4bdb35-6e26-4404-80e0-03a5736fabc7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
480264348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.480264348
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.1471898100
Short name T644
Test name
Test status
Simulation time 3349919700 ps
CPU time 160.13 seconds
Started Apr 30 02:29:04 PM PDT 24
Finished Apr 30 02:31:52 PM PDT 24
Peak memory 293652 kb
Host smart-e3ba1fd9-9922-4383-84a9-5143843056c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471898100 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.1471898100
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.394452996
Short name T33
Test name
Test status
Simulation time 16670398200 ps
CPU time 533.26 seconds
Started Apr 30 02:29:03 PM PDT 24
Finished Apr 30 02:38:04 PM PDT 24
Peak memory 313904 kb
Host smart-2b9c48ce-7e9c-4611-b7ca-899eaeb47483
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394452996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.flash_ctrl_rw.394452996
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.886101583
Short name T719
Test name
Test status
Simulation time 89966400 ps
CPU time 31.59 seconds
Started Apr 30 02:29:14 PM PDT 24
Finished Apr 30 02:29:52 PM PDT 24
Peak memory 267772 kb
Host smart-5fc1d931-e690-48bc-b6a0-623b0f30ba16
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886101583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_rw_evict.886101583
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.3333800982
Short name T269
Test name
Test status
Simulation time 4018376900 ps
CPU time 79.24 seconds
Started Apr 30 02:29:17 PM PDT 24
Finished Apr 30 02:30:43 PM PDT 24
Peak memory 262600 kb
Host smart-07260499-f2d0-490e-a227-3c6c3863dcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333800982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.3333800982
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.3388327647
Short name T682
Test name
Test status
Simulation time 26254700 ps
CPU time 99.78 seconds
Started Apr 30 02:28:56 PM PDT 24
Finished Apr 30 02:30:40 PM PDT 24
Peak memory 274676 kb
Host smart-591a1a60-1151-44ab-abd6-597b987d5206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388327647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.3388327647
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.3035275037
Short name T905
Test name
Test status
Simulation time 40658055400 ps
CPU time 272.33 seconds
Started Apr 30 02:29:03 PM PDT 24
Finished Apr 30 02:33:44 PM PDT 24
Peak memory 264692 kb
Host smart-d70d738c-b5b3-4e17-a302-5328d3a20ba6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035275037 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.flash_ctrl_wo.3035275037
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.2475617694
Short name T731
Test name
Test status
Simulation time 88330100 ps
CPU time 14.05 seconds
Started Apr 30 02:29:30 PM PDT 24
Finished Apr 30 02:29:50 PM PDT 24
Peak memory 257736 kb
Host smart-324ac19e-588e-4e79-a058-9bd555e12f99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475617694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.2
475617694
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.1577370596
Short name T709
Test name
Test status
Simulation time 77208400 ps
CPU time 15.7 seconds
Started Apr 30 02:29:30 PM PDT 24
Finished Apr 30 02:29:52 PM PDT 24
Peak memory 275616 kb
Host smart-1c9a6127-aa88-43be-aa42-6622e41842a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577370596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.1577370596
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.2936059909
Short name T383
Test name
Test status
Simulation time 95628900 ps
CPU time 22.01 seconds
Started Apr 30 02:29:30 PM PDT 24
Finished Apr 30 02:29:59 PM PDT 24
Peak memory 280200 kb
Host smart-6e9d453e-b629-4350-b205-a0964c90c4d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936059909 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.2936059909
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.2565779849
Short name T219
Test name
Test status
Simulation time 6809976700 ps
CPU time 2143.41 seconds
Started Apr 30 02:29:17 PM PDT 24
Finished Apr 30 03:05:07 PM PDT 24
Peak memory 264496 kb
Host smart-c4477d84-8e3a-4ba4-80f3-1b0ba8341d3d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565779849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_err
or_mp.2565779849
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.4010018464
Short name T634
Test name
Test status
Simulation time 1721478200 ps
CPU time 895.85 seconds
Started Apr 30 02:29:21 PM PDT 24
Finished Apr 30 02:44:23 PM PDT 24
Peak memory 272688 kb
Host smart-b6aa376a-171a-4644-8618-7a4a32e8a66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010018464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.4010018464
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.1979156981
Short name T546
Test name
Test status
Simulation time 164198400 ps
CPU time 21.12 seconds
Started Apr 30 02:29:24 PM PDT 24
Finished Apr 30 02:29:51 PM PDT 24
Peak memory 264412 kb
Host smart-79e57307-b9c7-43a8-ae63-fce8efc8952a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979156981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.1979156981
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.2400999535
Short name T534
Test name
Test status
Simulation time 10019840100 ps
CPU time 92.26 seconds
Started Apr 30 02:29:30 PM PDT 24
Finished Apr 30 02:31:09 PM PDT 24
Peak memory 330244 kb
Host smart-f0cec02b-4309-4a28-a1bc-de526d5356c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400999535 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.2400999535
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.2071318793
Short name T164
Test name
Test status
Simulation time 15785800 ps
CPU time 13.43 seconds
Started Apr 30 02:29:30 PM PDT 24
Finished Apr 30 02:29:50 PM PDT 24
Peak memory 257632 kb
Host smart-e39d20e4-80ac-4643-80e2-245a7f27a617
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071318793 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.2071318793
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.1078538573
Short name T393
Test name
Test status
Simulation time 80131463100 ps
CPU time 891.47 seconds
Started Apr 30 02:29:17 PM PDT 24
Finished Apr 30 02:44:16 PM PDT 24
Peak memory 258700 kb
Host smart-178ec0b4-653b-4f56-986c-cb3f36cc1cd2
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078538573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.flash_ctrl_hw_rma_reset.1078538573
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.1682777519
Short name T897
Test name
Test status
Simulation time 6914443400 ps
CPU time 63.15 seconds
Started Apr 30 02:29:18 PM PDT 24
Finished Apr 30 02:30:28 PM PDT 24
Peak memory 262088 kb
Host smart-f92b648f-1210-45ca-97a5-372187c916ae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682777519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h
w_sec_otp.1682777519
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.2877940887
Short name T312
Test name
Test status
Simulation time 1006368100 ps
CPU time 160.5 seconds
Started Apr 30 02:29:23 PM PDT 24
Finished Apr 30 02:32:09 PM PDT 24
Peak memory 292716 kb
Host smart-b37b83b2-d39a-45af-93c0-c4f182ea4db8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877940887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_intr_rd.2877940887
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.3610351140
Short name T597
Test name
Test status
Simulation time 21332918600 ps
CPU time 211.82 seconds
Started Apr 30 02:29:24 PM PDT 24
Finished Apr 30 02:33:02 PM PDT 24
Peak memory 284124 kb
Host smart-7f812e91-d676-459a-b156-a85a597ba2c0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610351140 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.3610351140
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.770925643
Short name T752
Test name
Test status
Simulation time 9489021200 ps
CPU time 79.27 seconds
Started Apr 30 02:29:24 PM PDT 24
Finished Apr 30 02:30:49 PM PDT 24
Peak memory 259272 kb
Host smart-4a6d2154-9640-45e4-a577-f7f7f5314753
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770925643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.770925643
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.3057318578
Short name T462
Test name
Test status
Simulation time 34156800 ps
CPU time 13.61 seconds
Started Apr 30 02:29:32 PM PDT 24
Finished Apr 30 02:29:52 PM PDT 24
Peak memory 259228 kb
Host smart-02fa3e36-ccb1-4e7f-b632-b74c05d524f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057318578 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.3057318578
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.432129813
Short name T638
Test name
Test status
Simulation time 71648158000 ps
CPU time 299.67 seconds
Started Apr 30 02:29:16 PM PDT 24
Finished Apr 30 02:34:23 PM PDT 24
Peak memory 273128 kb
Host smart-63a2c742-4d31-48fd-a643-c0cbe3c6fc48
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432129813 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_mp_regions.432129813
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.948170264
Short name T29
Test name
Test status
Simulation time 84215000 ps
CPU time 111.17 seconds
Started Apr 30 02:29:19 PM PDT 24
Finished Apr 30 02:31:17 PM PDT 24
Peak memory 259264 kb
Host smart-66112a18-9132-48a3-aa89-175a9e49354d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948170264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp
_reset.948170264
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.538324213
Short name T591
Test name
Test status
Simulation time 1418926900 ps
CPU time 177.16 seconds
Started Apr 30 02:29:18 PM PDT 24
Finished Apr 30 02:32:22 PM PDT 24
Peak memory 261000 kb
Host smart-5a9d677b-fd7b-4693-8938-4574b38c931e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=538324213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.538324213
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.3027291630
Short name T729
Test name
Test status
Simulation time 121786600 ps
CPU time 57.57 seconds
Started Apr 30 02:29:19 PM PDT 24
Finished Apr 30 02:30:23 PM PDT 24
Peak memory 261624 kb
Host smart-7c8a8848-e741-4fdb-9b05-d3ec6125ba8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027291630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.3027291630
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.4015111756
Short name T483
Test name
Test status
Simulation time 109348700 ps
CPU time 38.55 seconds
Started Apr 30 02:29:30 PM PDT 24
Finished Apr 30 02:30:15 PM PDT 24
Peak memory 273048 kb
Host smart-7e192bc8-39df-48f9-a84e-7bb92e305126
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015111756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_re_evict.4015111756
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.3824043143
Short name T484
Test name
Test status
Simulation time 1627027700 ps
CPU time 128.79 seconds
Started Apr 30 02:29:18 PM PDT 24
Finished Apr 30 02:31:34 PM PDT 24
Peak memory 281060 kb
Host smart-e94f54d5-b769-4a54-8f28-e535e5fd6dc7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824043143 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_ro.3824043143
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.2399041095
Short name T208
Test name
Test status
Simulation time 2976699900 ps
CPU time 125.54 seconds
Started Apr 30 02:29:23 PM PDT 24
Finished Apr 30 02:31:35 PM PDT 24
Peak memory 281292 kb
Host smart-32a63393-9a8a-4fdb-be9a-e0fe36aaf425
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2399041095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.2399041095
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.2547131379
Short name T50
Test name
Test status
Simulation time 739761200 ps
CPU time 148 seconds
Started Apr 30 02:29:23 PM PDT 24
Finished Apr 30 02:31:57 PM PDT 24
Peak memory 289256 kb
Host smart-cae574ed-3f99-4d70-a7d6-7c32c7ca1856
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547131379 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.2547131379
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.3969766963
Short name T175
Test name
Test status
Simulation time 15160537700 ps
CPU time 578.41 seconds
Started Apr 30 02:29:19 PM PDT 24
Finished Apr 30 02:39:04 PM PDT 24
Peak memory 313796 kb
Host smart-de744986-e2e6-4810-b076-c9a864205a7e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969766963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.flash_ctrl_rw.3969766963
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.388824006
Short name T457
Test name
Test status
Simulation time 1263270400 ps
CPU time 69.56 seconds
Started Apr 30 02:29:32 PM PDT 24
Finished Apr 30 02:30:49 PM PDT 24
Peak memory 262824 kb
Host smart-d0e9790a-77b4-4fe4-bce2-752de6175a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388824006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.388824006
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.2614048024
Short name T704
Test name
Test status
Simulation time 17268600 ps
CPU time 51.3 seconds
Started Apr 30 02:29:17 PM PDT 24
Finished Apr 30 02:30:15 PM PDT 24
Peak memory 269900 kb
Host smart-2a3f32e1-38a9-48d3-ac97-6e5c06cb0cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614048024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.2614048024
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.2134515815
Short name T652
Test name
Test status
Simulation time 27247857500 ps
CPU time 173.71 seconds
Started Apr 30 02:29:24 PM PDT 24
Finished Apr 30 02:32:23 PM PDT 24
Peak memory 264684 kb
Host smart-15b6bec2-0a93-4977-9020-bd4ee6640ef3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134515815 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.flash_ctrl_wo.2134515815
Directory /workspace/9.flash_ctrl_wo/latest
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