Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19069558	1		T1	111		T2	141215		T3	57
full_word	7198953	1		T1	1		T2	30397		T3	1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	26268171	1		T1	112		T2	171612		T3	58
auto[TlIntgErrCmd]	124	1		T57	4		T60	5		T206	6
auto[TlIntgErrData]	105	1		T57	3		T60	1		T207	5
auto[TlIntgErrBoth]	111	1		T57	3		T60	4		T206	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	22378881	1		T1	104		T2	150840		T3	57
auto[1]	3889630	1		T1	8		T2	20772		T3	1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18480527	1		T1	104		T2	138990		T3	56
auto[TlIntgErrNone]	partial	auto[1]	588721	1		T1	7		T2	2225		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	3898196	1		T2	11850		T3	1		T6	1056
auto[TlIntgErrNone]	full_word	auto[1]	3300727	1		T1	1		T2	18547		T6	1479
auto[TlIntgErrCmd]	partial	auto[0]	54	1		T57	2		T60	3		T206	2
auto[TlIntgErrCmd]	partial	auto[1]	61	1		T57	2		T60	1		T206	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T267	1		T275	1		T344	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T60	1		T267	1		T279	2
auto[TlIntgErrData]	partial	auto[0]	41	1		T57	3		T207	1		T205	1
auto[TlIntgErrData]	partial	auto[1]	57	1		T60	1		T207	4		T205	5
auto[TlIntgErrData]	full_word	auto[0]	5	1		T205	1		T284	2		T275	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T279	1		T343	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	45	1		T60	3		T206	3		T207	3
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T57	2		T60	1		T206	1
auto[TlIntgErrBoth]	full_word	auto[0]	9	1		T57	1		T275	2		T343	2
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T205	1		T267	1		T273	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20477	1		T57	8		T59	91		T60	7
full_word	3445377	1		T2	41939		T17	16672		T22	11

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3465536	1		T2	41939		T17	16672		T22	11
auto[TlIntgErrCmd]	104	1		T57	3		T60	1		T206	3
auto[TlIntgErrData]	110	1		T57	2		T60	5		T206	4
auto[TlIntgErrBoth]	104	1		T57	4		T60	3		T206	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3440420	1		T2	41939		T17	16672		T22	11
auto[1]	25434	1		T57	7		T59	117		T60	7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1298	1		T59	2		T188	70		T189	4
auto[TlIntgErrNone]	partial	auto[1]	18897	1		T59	89		T188	990		T189	195
auto[TlIntgErrNone]	full_word	auto[0]	3438989	1		T2	41939		T17	16672		T22	11
auto[TlIntgErrNone]	full_word	auto[1]	6352	1		T59	28		T188	258		T189	229
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T57	2		T60	1		T206	2
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T206	1		T207	3		T205	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T284	1		T344	1		T345	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T57	1		T207	1		T267	1
auto[TlIntgErrData]	partial	auto[0]	51	1		T60	1		T206	2		T207	3
auto[TlIntgErrData]	partial	auto[1]	45	1		T57	2		T60	2		T206	1
auto[TlIntgErrData]	full_word	auto[0]	7	1		T206	1		T278	1		T343	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T60	2		T267	1		T343	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T206	2		T205	2		T267	2
auto[TlIntgErrBoth]	partial	auto[1]	63	1		T57	4		T60	3		T205	6
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T207	2		T205	1		T267	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T267	1		T273	1		T278	1