Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T17,T22

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T17,T22
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T17,T22
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T17,T22

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T17,T22
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T17,T18
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T17,T22

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T17,T22

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1455892816	1453193020	0	0
CheckNGreaterZero_A	3492	3492	0	0
GntImpliesReady_A	1455892816	349226371	0	0
GntImpliesValid_A	1455892816	349226371	0	0
GrantKnown_A	1455892816	1453193020	0	0
IdxKnown_A	1455892816	1453193020	0	0
IndexIsCorrect_A	1455892816	349226371	0	0
NoReadyValidNoGrant_A	1455892816	173157102	0	0
Priority_A	1455892816	371567055	0	0
ReadyAndValidImplyGrant_A	1455892816	349226371	0	0
ReqAndReadyImplyGrant_A	1455892816	349226371	0	0
ReqImpliesValid_A	1455892816	371567055	0	0
ValidKnown_A	1455892816	1453193020	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455892816	1453193020	0	0
T1	15324	13020	0	0
T2	1414476	1414120	0	0
T3	4732	4376	0	0
T4	5932	4984	0	0
T5	556364	556360	0	0
T6	3039260	3039032	0	0
T7	524376	524092	0	0
T11	10328	10056	0	0
T17	236852	236540	0	0
T22	3224	2880	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3492	3492	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T11	4	4	0	0
T17	4	4	0	0
T22	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455892816	349226371	0	0
T1	7662	392	0	0
T2	1414476	449162	0	0
T3	4732	64	0	0
T4	5932	130	0	0
T5	556364	1715406	0	0
T6	3039260	1502150	0	0
T7	524376	1608	0	0
T11	10328	646	0	0
T14	0	30068	0	0
T17	236852	44908	0	0
T18	0	21350	0	0
T22	3224	86	0	0
T23	7252	0	0	0
T30	0	217780	0	0
T31	0	180048	0	0
T78	0	292	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455892816	349226371	0	0
T1	7662	392	0	0
T2	1414476	449162	0	0
T3	4732	64	0	0
T4	5932	130	0	0
T5	556364	1715406	0	0
T6	3039260	1502150	0	0
T7	524376	1608	0	0
T11	10328	646	0	0
T14	0	30068	0	0
T17	236852	44908	0	0
T18	0	21350	0	0
T22	3224	86	0	0
T23	7252	0	0	0
T30	0	217780	0	0
T31	0	180048	0	0
T78	0	292	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455892816	1453193020	0	0
T1	15324	13020	0	0
T2	1414476	1414120	0	0
T3	4732	4376	0	0
T4	5932	4984	0	0
T5	556364	556360	0	0
T6	3039260	3039032	0	0
T7	524376	524092	0	0
T11	10328	10056	0	0
T17	236852	236540	0	0
T22	3224	2880	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455892816	1453193020	0	0
T1	15324	13020	0	0
T2	1414476	1414120	0	0
T3	4732	4376	0	0
T4	5932	4984	0	0
T5	556364	556360	0	0
T6	3039260	3039032	0	0
T7	524376	524092	0	0
T11	10328	10056	0	0
T17	236852	236540	0	0
T22	3224	2880	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455892816	349226371	0	0
T1	7662	392	0	0
T2	1414476	449162	0	0
T3	4732	64	0	0
T4	5932	130	0	0
T5	556364	1715406	0	0
T6	3039260	1502150	0	0
T7	524376	1608	0	0
T11	10328	646	0	0
T14	0	30068	0	0
T17	236852	44908	0	0
T18	0	21350	0	0
T22	3224	86	0	0
T23	7252	0	0	0
T30	0	217780	0	0
T31	0	180048	0	0
T78	0	292	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455892816	173157102	0	0
T1	7662	1376	0	0
T2	1414476	193750	0	0
T3	4732	256	0	0
T4	5932	520	0	0
T5	556364	2110516	0	0
T6	3039260	3082	0	0
T7	524376	2688	0	0
T11	10328	290	0	0
T14	0	83744	0	0
T17	236852	59914	0	0
T18	0	27206	0	0
T22	3224	290	0	0
T23	7252	0	0	0
T63	0	284	0	0
T64	0	1002	0	0
T78	0	730	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455892816	371567055	0	0
T1	7662	392	0	0
T2	1414476	550826	0	0
T3	4732	64	0	0
T4	5932	130	0	0
T5	556364	1715406	0	0
T6	3039260	1502150	0	0
T7	524376	1608	0	0
T11	10328	646	0	0
T14	0	32110	0	0
T17	236852	55980	0	0
T18	0	34376	0	0
T22	3224	86	0	0
T23	7252	0	0	0
T30	0	217780	0	0
T31	0	180048	0	0
T78	0	292	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455892816	349226371	0	0
T1	7662	392	0	0
T2	1414476	449162	0	0
T3	4732	64	0	0
T4	5932	130	0	0
T5	556364	1715406	0	0
T6	3039260	1502150	0	0
T7	524376	1608	0	0
T11	10328	646	0	0
T14	0	30068	0	0
T17	236852	44908	0	0
T18	0	21350	0	0
T22	3224	86	0	0
T23	7252	0	0	0
T30	0	217780	0	0
T31	0	180048	0	0
T78	0	292	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455892816	349226371	0	0
T1	7662	392	0	0
T2	1414476	449162	0	0
T3	4732	64	0	0
T4	5932	130	0	0
T5	556364	1715406	0	0
T6	3039260	1502150	0	0
T7	524376	1608	0	0
T11	10328	646	0	0
T14	0	30068	0	0
T17	236852	44908	0	0
T18	0	21350	0	0
T22	3224	86	0	0
T23	7252	0	0	0
T30	0	217780	0	0
T31	0	180048	0	0
T78	0	292	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455892816	371567055	0	0
T1	7662	392	0	0
T2	1414476	550826	0	0
T3	4732	64	0	0
T4	5932	130	0	0
T5	556364	1715406	0	0
T6	3039260	1502150	0	0
T7	524376	1608	0	0
T11	10328	646	0	0
T14	0	32110	0	0
T17	236852	55980	0	0
T18	0	34376	0	0
T22	3224	86	0	0
T23	7252	0	0	0
T30	0	217780	0	0
T31	0	180048	0	0
T78	0	292	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455892816	1453193020	0	0
T1	15324	13020	0	0
T2	1414476	1414120	0	0
T3	4732	4376	0	0
T4	5932	4984	0	0
T5	556364	556360	0	0
T6	3039260	3039032	0	0
T7	524376	524092	0	0
T11	10328	10056	0	0
T17	236852	236540	0	0
T22	3224	2880	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T17,T25

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T17,T25
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T17,T25
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T17,T25

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T17,T25
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T17,T18
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T17,T25

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T17,T25

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	363973204	363298255	0	0
CheckNGreaterZero_A	873	873	0	0
GntImpliesReady_A	363973204	88645934	0	0
GntImpliesValid_A	363973204	88645934	0	0
GrantKnown_A	363973204	363298255	0	0
IdxKnown_A	363973204	363298255	0	0
IndexIsCorrect_A	363973204	88645934	0	0
NoReadyValidNoGrant_A	363973204	44853799	0	0
Priority_A	363973204	94413752	0	0
ReadyAndValidImplyGrant_A	363973204	88645934	0	0
ReqAndReadyImplyGrant_A	363973204	88645934	0	0
ReqImpliesValid_A	363973204	94413752	0	0
ValidKnown_A	363973204	363298255	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	363298255	0	0
T1	3831	3255	0	0
T2	353619	353530	0	0
T3	1183	1094	0	0
T4	1483	1246	0	0
T5	139091	139090	0	0
T6	759815	759758	0	0
T7	131094	131023	0	0
T11	2582	2514	0	0
T17	59213	59135	0	0
T22	806	720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	88645934	0	0
T1	3831	196	0	0
T2	353619	87135	0	0
T3	1183	32	0	0
T4	1483	65	0	0
T5	139091	431343	0	0
T6	759815	470949	0	0
T7	131094	804	0	0
T11	2582	323	0	0
T17	59213	11775	0	0
T22	806	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	88645934	0	0
T1	3831	196	0	0
T2	353619	87135	0	0
T3	1183	32	0	0
T4	1483	65	0	0
T5	139091	431343	0	0
T6	759815	470949	0	0
T7	131094	804	0	0
T11	2582	323	0	0
T17	59213	11775	0	0
T22	806	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	363298255	0	0
T1	3831	3255	0	0
T2	353619	353530	0	0
T3	1183	1094	0	0
T4	1483	1246	0	0
T5	139091	139090	0	0
T6	759815	759758	0	0
T7	131094	131023	0	0
T11	2582	2514	0	0
T17	59213	59135	0	0
T22	806	720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	363298255	0	0
T1	3831	3255	0	0
T2	353619	353530	0	0
T3	1183	1094	0	0
T4	1483	1246	0	0
T5	139091	139090	0	0
T6	759815	759758	0	0
T7	131094	131023	0	0
T11	2582	2514	0	0
T17	59213	59135	0	0
T22	806	720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	88645934	0	0
T1	3831	196	0	0
T2	353619	87135	0	0
T3	1183	32	0	0
T4	1483	65	0	0
T5	139091	431343	0	0
T6	759815	470949	0	0
T7	131094	804	0	0
T11	2582	323	0	0
T17	59213	11775	0	0
T22	806	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	44853799	0	0
T1	3831	688	0	0
T2	353619	48454	0	0
T3	1183	128	0	0
T4	1483	260	0	0
T5	139091	530777	0	0
T6	759815	655	0	0
T7	131094	1344	0	0
T11	2582	145	0	0
T17	59213	15582	0	0
T22	806	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	94413752	0	0
T1	3831	196	0	0
T2	353619	112325	0	0
T3	1183	32	0	0
T4	1483	65	0	0
T5	139091	431343	0	0
T6	759815	470949	0	0
T7	131094	804	0	0
T11	2582	323	0	0
T17	59213	14747	0	0
T22	806	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	88645934	0	0
T1	3831	196	0	0
T2	353619	87135	0	0
T3	1183	32	0	0
T4	1483	65	0	0
T5	139091	431343	0	0
T6	759815	470949	0	0
T7	131094	804	0	0
T11	2582	323	0	0
T17	59213	11775	0	0
T22	806	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	88645934	0	0
T1	3831	196	0	0
T2	353619	87135	0	0
T3	1183	32	0	0
T4	1483	65	0	0
T5	139091	431343	0	0
T6	759815	470949	0	0
T7	131094	804	0	0
T11	2582	323	0	0
T17	59213	11775	0	0
T22	806	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	94413752	0	0
T1	3831	196	0	0
T2	353619	112325	0	0
T3	1183	32	0	0
T4	1483	65	0	0
T5	139091	431343	0	0
T6	759815	470949	0	0
T7	131094	804	0	0
T11	2582	323	0	0
T17	59213	14747	0	0
T22	806	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	363298255	0	0
T1	3831	3255	0	0
T2	353619	353530	0	0
T3	1183	1094	0	0
T4	1483	1246	0	0
T5	139091	139090	0	0
T6	759815	759758	0	0
T7	131094	131023	0	0
T11	2582	2514	0	0
T17	59213	59135	0	0
T22	806	720	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T17,T25

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T17,T25
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T17,T25
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T17,T25

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T17,T25
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T17,T18
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T17,T25

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T17,T25

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	363973204	363298255	0	0
CheckNGreaterZero_A	873	873	0	0
GntImpliesReady_A	363973204	88645934	0	0
GntImpliesValid_A	363973204	88645934	0	0
GrantKnown_A	363973204	363298255	0	0
IdxKnown_A	363973204	363298255	0	0
IndexIsCorrect_A	363973204	88645934	0	0
NoReadyValidNoGrant_A	363973204	44853799	0	0
Priority_A	363973204	94413752	0	0
ReadyAndValidImplyGrant_A	363973204	88645934	0	0
ReqAndReadyImplyGrant_A	363973204	88645934	0	0
ReqImpliesValid_A	363973204	94413752	0	0
ValidKnown_A	363973204	363298255	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	363298255	0	0
T1	3831	3255	0	0
T2	353619	353530	0	0
T3	1183	1094	0	0
T4	1483	1246	0	0
T5	139091	139090	0	0
T6	759815	759758	0	0
T7	131094	131023	0	0
T11	2582	2514	0	0
T17	59213	59135	0	0
T22	806	720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	88645934	0	0
T1	3831	196	0	0
T2	353619	87135	0	0
T3	1183	32	0	0
T4	1483	65	0	0
T5	139091	431343	0	0
T6	759815	470949	0	0
T7	131094	804	0	0
T11	2582	323	0	0
T17	59213	11775	0	0
T22	806	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	88645934	0	0
T1	3831	196	0	0
T2	353619	87135	0	0
T3	1183	32	0	0
T4	1483	65	0	0
T5	139091	431343	0	0
T6	759815	470949	0	0
T7	131094	804	0	0
T11	2582	323	0	0
T17	59213	11775	0	0
T22	806	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	363298255	0	0
T1	3831	3255	0	0
T2	353619	353530	0	0
T3	1183	1094	0	0
T4	1483	1246	0	0
T5	139091	139090	0	0
T6	759815	759758	0	0
T7	131094	131023	0	0
T11	2582	2514	0	0
T17	59213	59135	0	0
T22	806	720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	363298255	0	0
T1	3831	3255	0	0
T2	353619	353530	0	0
T3	1183	1094	0	0
T4	1483	1246	0	0
T5	139091	139090	0	0
T6	759815	759758	0	0
T7	131094	131023	0	0
T11	2582	2514	0	0
T17	59213	59135	0	0
T22	806	720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	88645934	0	0
T1	3831	196	0	0
T2	353619	87135	0	0
T3	1183	32	0	0
T4	1483	65	0	0
T5	139091	431343	0	0
T6	759815	470949	0	0
T7	131094	804	0	0
T11	2582	323	0	0
T17	59213	11775	0	0
T22	806	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	44853799	0	0
T1	3831	688	0	0
T2	353619	48454	0	0
T3	1183	128	0	0
T4	1483	260	0	0
T5	139091	530777	0	0
T6	759815	655	0	0
T7	131094	1344	0	0
T11	2582	145	0	0
T17	59213	15582	0	0
T22	806	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	94413752	0	0
T1	3831	196	0	0
T2	353619	112325	0	0
T3	1183	32	0	0
T4	1483	65	0	0
T5	139091	431343	0	0
T6	759815	470949	0	0
T7	131094	804	0	0
T11	2582	323	0	0
T17	59213	14747	0	0
T22	806	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	88645934	0	0
T1	3831	196	0	0
T2	353619	87135	0	0
T3	1183	32	0	0
T4	1483	65	0	0
T5	139091	431343	0	0
T6	759815	470949	0	0
T7	131094	804	0	0
T11	2582	323	0	0
T17	59213	11775	0	0
T22	806	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	88645934	0	0
T1	3831	196	0	0
T2	353619	87135	0	0
T3	1183	32	0	0
T4	1483	65	0	0
T5	139091	431343	0	0
T6	759815	470949	0	0
T7	131094	804	0	0
T11	2582	323	0	0
T17	59213	11775	0	0
T22	806	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	94413752	0	0
T1	3831	196	0	0
T2	353619	112325	0	0
T3	1183	32	0	0
T4	1483	65	0	0
T5	139091	431343	0	0
T6	759815	470949	0	0
T7	131094	804	0	0
T11	2582	323	0	0
T17	59213	14747	0	0
T22	806	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	363298255	0	0
T1	3831	3255	0	0
T2	353619	353530	0	0
T3	1183	1094	0	0
T4	1483	1246	0	0
T5	139091	139090	0	0
T6	759815	759758	0	0
T7	131094	131023	0	0
T11	2582	2514	0	0
T17	59213	59135	0	0
T22	806	720	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T5
1	0	Covered	T2,T17,T22

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T17,T22
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T17,T22
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T18
1	0	Covered	T2,T6,T5
1	1	Covered	T2,T17,T22

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T17,T22
1	1	Covered	T2,T6,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T17,T18
1	1	Covered	T2,T6,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T17,T22

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T17,T22

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	363973204	363298255	0	0
CheckNGreaterZero_A	873	873	0	0
GntImpliesReady_A	363973204	85967291	0	0
GntImpliesValid_A	363973204	85967291	0	0
GrantKnown_A	363973204	363298255	0	0
IdxKnown_A	363973204	363298255	0	0
IndexIsCorrect_A	363973204	85967291	0	0
NoReadyValidNoGrant_A	363973204	41724752	0	0
Priority_A	363973204	91369815	0	0
ReadyAndValidImplyGrant_A	363973204	85967291	0	0
ReqAndReadyImplyGrant_A	363973204	85967291	0	0
ReqImpliesValid_A	363973204	91369815	0	0
ValidKnown_A	363973204	363298255	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	363298255	0	0
T1	3831	3255	0	0
T2	353619	353530	0	0
T3	1183	1094	0	0
T4	1483	1246	0	0
T5	139091	139090	0	0
T6	759815	759758	0	0
T7	131094	131023	0	0
T11	2582	2514	0	0
T17	59213	59135	0	0
T22	806	720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	85967291	0	0
T2	353619	137446	0	0
T3	1183	0	0	0
T4	1483	0	0	0
T5	139091	426360	0	0
T6	759815	280126	0	0
T7	131094	0	0	0
T11	2582	0	0	0
T14	0	15034	0	0
T17	59213	10679	0	0
T18	0	10675	0	0
T22	806	11	0	0
T23	3626	0	0	0
T30	0	108890	0	0
T31	0	90024	0	0
T78	0	146	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	85967291	0	0
T2	353619	137446	0	0
T3	1183	0	0	0
T4	1483	0	0	0
T5	139091	426360	0	0
T6	759815	280126	0	0
T7	131094	0	0	0
T11	2582	0	0	0
T14	0	15034	0	0
T17	59213	10679	0	0
T18	0	10675	0	0
T22	806	11	0	0
T23	3626	0	0	0
T30	0	108890	0	0
T31	0	90024	0	0
T78	0	146	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	363298255	0	0
T1	3831	3255	0	0
T2	353619	353530	0	0
T3	1183	1094	0	0
T4	1483	1246	0	0
T5	139091	139090	0	0
T6	759815	759758	0	0
T7	131094	131023	0	0
T11	2582	2514	0	0
T17	59213	59135	0	0
T22	806	720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	363298255	0	0
T1	3831	3255	0	0
T2	353619	353530	0	0
T3	1183	1094	0	0
T4	1483	1246	0	0
T5	139091	139090	0	0
T6	759815	759758	0	0
T7	131094	131023	0	0
T11	2582	2514	0	0
T17	59213	59135	0	0
T22	806	720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	85967291	0	0
T2	353619	137446	0	0
T3	1183	0	0	0
T4	1483	0	0	0
T5	139091	426360	0	0
T6	759815	280126	0	0
T7	131094	0	0	0
T11	2582	0	0	0
T14	0	15034	0	0
T17	59213	10679	0	0
T18	0	10675	0	0
T22	806	11	0	0
T23	3626	0	0	0
T30	0	108890	0	0
T31	0	90024	0	0
T78	0	146	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	41724752	0	0
T2	353619	48421	0	0
T3	1183	0	0	0
T4	1483	0	0	0
T5	139091	524481	0	0
T6	759815	886	0	0
T7	131094	0	0	0
T11	2582	0	0	0
T14	0	41872	0	0
T17	59213	14375	0	0
T18	0	13603	0	0
T22	806	17	0	0
T23	3626	0	0	0
T63	0	142	0	0
T64	0	501	0	0
T78	0	365	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	91369815	0	0
T2	353619	163088	0	0
T3	1183	0	0	0
T4	1483	0	0	0
T5	139091	426360	0	0
T6	759815	280126	0	0
T7	131094	0	0	0
T11	2582	0	0	0
T14	0	16055	0	0
T17	59213	13243	0	0
T18	0	17188	0	0
T22	806	11	0	0
T23	3626	0	0	0
T30	0	108890	0	0
T31	0	90024	0	0
T78	0	146	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	85967291	0	0
T2	353619	137446	0	0
T3	1183	0	0	0
T4	1483	0	0	0
T5	139091	426360	0	0
T6	759815	280126	0	0
T7	131094	0	0	0
T11	2582	0	0	0
T14	0	15034	0	0
T17	59213	10679	0	0
T18	0	10675	0	0
T22	806	11	0	0
T23	3626	0	0	0
T30	0	108890	0	0
T31	0	90024	0	0
T78	0	146	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	85967291	0	0
T2	353619	137446	0	0
T3	1183	0	0	0
T4	1483	0	0	0
T5	139091	426360	0	0
T6	759815	280126	0	0
T7	131094	0	0	0
T11	2582	0	0	0
T14	0	15034	0	0
T17	59213	10679	0	0
T18	0	10675	0	0
T22	806	11	0	0
T23	3626	0	0	0
T30	0	108890	0	0
T31	0	90024	0	0
T78	0	146	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	91369815	0	0
T2	353619	163088	0	0
T3	1183	0	0	0
T4	1483	0	0	0
T5	139091	426360	0	0
T6	759815	280126	0	0
T7	131094	0	0	0
T11	2582	0	0	0
T14	0	16055	0	0
T17	59213	13243	0	0
T18	0	17188	0	0
T22	806	11	0	0
T23	3626	0	0	0
T30	0	108890	0	0
T31	0	90024	0	0
T78	0	146	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	363298255	0	0
T1	3831	3255	0	0
T2	353619	353530	0	0
T3	1183	1094	0	0
T4	1483	1246	0	0
T5	139091	139090	0	0
T6	759815	759758	0	0
T7	131094	131023	0	0
T11	2582	2514	0	0
T17	59213	59135	0	0
T22	806	720	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T5
1	0	Covered	T2,T17,T22

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T17,T22
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T17,T22
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T18
1	0	Covered	T2,T6,T5
1	1	Covered	T2,T17,T22

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T17,T22
1	1	Covered	T2,T6,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T17,T18
1	1	Covered	T2,T6,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T17,T22

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T17,T22

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	363973204	363298255	0	0
CheckNGreaterZero_A	873	873	0	0
GntImpliesReady_A	363973204	85967212	0	0
GntImpliesValid_A	363973204	85967212	0	0
GrantKnown_A	363973204	363298255	0	0
IdxKnown_A	363973204	363298255	0	0
IndexIsCorrect_A	363973204	85967212	0	0
NoReadyValidNoGrant_A	363973204	41724752	0	0
Priority_A	363973204	91369736	0	0
ReadyAndValidImplyGrant_A	363973204	85967212	0	0
ReqAndReadyImplyGrant_A	363973204	85967212	0	0
ReqImpliesValid_A	363973204	91369736	0	0
ValidKnown_A	363973204	363298255	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	363298255	0	0
T1	3831	3255	0	0
T2	353619	353530	0	0
T3	1183	1094	0	0
T4	1483	1246	0	0
T5	139091	139090	0	0
T6	759815	759758	0	0
T7	131094	131023	0	0
T11	2582	2514	0	0
T17	59213	59135	0	0
T22	806	720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	85967212	0	0
T2	353619	137446	0	0
T3	1183	0	0	0
T4	1483	0	0	0
T5	139091	426360	0	0
T6	759815	280126	0	0
T7	131094	0	0	0
T11	2582	0	0	0
T14	0	15034	0	0
T17	59213	10679	0	0
T18	0	10675	0	0
T22	806	11	0	0
T23	3626	0	0	0
T30	0	108890	0	0
T31	0	90024	0	0
T78	0	146	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	85967212	0	0
T2	353619	137446	0	0
T3	1183	0	0	0
T4	1483	0	0	0
T5	139091	426360	0	0
T6	759815	280126	0	0
T7	131094	0	0	0
T11	2582	0	0	0
T14	0	15034	0	0
T17	59213	10679	0	0
T18	0	10675	0	0
T22	806	11	0	0
T23	3626	0	0	0
T30	0	108890	0	0
T31	0	90024	0	0
T78	0	146	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	363298255	0	0
T1	3831	3255	0	0
T2	353619	353530	0	0
T3	1183	1094	0	0
T4	1483	1246	0	0
T5	139091	139090	0	0
T6	759815	759758	0	0
T7	131094	131023	0	0
T11	2582	2514	0	0
T17	59213	59135	0	0
T22	806	720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	363298255	0	0
T1	3831	3255	0	0
T2	353619	353530	0	0
T3	1183	1094	0	0
T4	1483	1246	0	0
T5	139091	139090	0	0
T6	759815	759758	0	0
T7	131094	131023	0	0
T11	2582	2514	0	0
T17	59213	59135	0	0
T22	806	720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	85967212	0	0
T2	353619	137446	0	0
T3	1183	0	0	0
T4	1483	0	0	0
T5	139091	426360	0	0
T6	759815	280126	0	0
T7	131094	0	0	0
T11	2582	0	0	0
T14	0	15034	0	0
T17	59213	10679	0	0
T18	0	10675	0	0
T22	806	11	0	0
T23	3626	0	0	0
T30	0	108890	0	0
T31	0	90024	0	0
T78	0	146	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	41724752	0	0
T2	353619	48421	0	0
T3	1183	0	0	0
T4	1483	0	0	0
T5	139091	524481	0	0
T6	759815	886	0	0
T7	131094	0	0	0
T11	2582	0	0	0
T14	0	41872	0	0
T17	59213	14375	0	0
T18	0	13603	0	0
T22	806	17	0	0
T23	3626	0	0	0
T63	0	142	0	0
T64	0	501	0	0
T78	0	365	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	91369736	0	0
T2	353619	163088	0	0
T3	1183	0	0	0
T4	1483	0	0	0
T5	139091	426360	0	0
T6	759815	280126	0	0
T7	131094	0	0	0
T11	2582	0	0	0
T14	0	16055	0	0
T17	59213	13243	0	0
T18	0	17188	0	0
T22	806	11	0	0
T23	3626	0	0	0
T30	0	108890	0	0
T31	0	90024	0	0
T78	0	146	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	85967212	0	0
T2	353619	137446	0	0
T3	1183	0	0	0
T4	1483	0	0	0
T5	139091	426360	0	0
T6	759815	280126	0	0
T7	131094	0	0	0
T11	2582	0	0	0
T14	0	15034	0	0
T17	59213	10679	0	0
T18	0	10675	0	0
T22	806	11	0	0
T23	3626	0	0	0
T30	0	108890	0	0
T31	0	90024	0	0
T78	0	146	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	85967212	0	0
T2	353619	137446	0	0
T3	1183	0	0	0
T4	1483	0	0	0
T5	139091	426360	0	0
T6	759815	280126	0	0
T7	131094	0	0	0
T11	2582	0	0	0
T14	0	15034	0	0
T17	59213	10679	0	0
T18	0	10675	0	0
T22	806	11	0	0
T23	3626	0	0	0
T30	0	108890	0	0
T31	0	90024	0	0
T78	0	146	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	91369736	0	0
T2	353619	163088	0	0
T3	1183	0	0	0
T4	1483	0	0	0
T5	139091	426360	0	0
T6	759815	280126	0	0
T7	131094	0	0	0
T11	2582	0	0	0
T14	0	16055	0	0
T17	59213	13243	0	0
T18	0	17188	0	0
T22	806	11	0	0
T23	3626	0	0	0
T30	0	108890	0	0
T31	0	90024	0	0
T78	0	146	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363973204	363298255	0	0
T1	3831	3255	0	0
T2	353619	353530	0	0
T3	1183	1094	0	0
T4	1483	1246	0	0
T5	139091	139090	0	0
T6	759815	759758	0	0
T7	131094	131023	0	0
T11	2582	2514	0	0
T17	59213	59135	0	0
T22	806	720	0	0