Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_count
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.84 82.84

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_ctrl_prog.u_cnt 55.17 55.17
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr 70.00 70.00
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr 70.00 70.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr 70.00 70.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr 70.00 70.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr 70.00 70.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr 70.00 70.00
tb.dut.u_flash_hw_if.u_page_cnt 75.76 75.76
tb.dut.u_flash_ctrl_rd.u_cnt 75.86 75.86
tb.dut.u_flash_hw_if.u_word_cnt 80.77 80.77
tb.dut.u_flash_hw_if.u_seed_cnt 87.50 87.50
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_outstanding_cnt 88.89 88.89
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_outstanding_cnt 88.89 88.89
tb.dut.u_flash_hw_if.u_wipe_idx_cnt 90.00 90.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr 90.00 90.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr 90.00 90.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr 90.00 90.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr 90.00 90.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr 90.00 90.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr 90.00 90.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr 90.00 90.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr 90.00 90.00
tb.dut.u_flash_hw_if.u_addr_cnt 90.91 90.91



Module Instance : tb.dut.u_flash_ctrl_prog.u_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
55.17 55.17


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
55.17 55.17


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.17 100.00 97.06 94.44 u_flash_ctrl_prog


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.00 70.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.00 70.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.19 100.00 73.91 66.67 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.00 70.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.00 70.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.19 100.00 73.91 66.67 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.00 70.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.00 70.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.19 100.00 73.91 66.67 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.00 70.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.00 70.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.19 100.00 73.91 66.67 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.00 70.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.00 70.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.19 100.00 73.91 66.67 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.00 70.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.00 70.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.19 100.00 73.91 66.67 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_page_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.76 75.76


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.76 75.76


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.89 100.00 76.04 89.47 98.94 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_ctrl_rd.u_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.86 75.86


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.86 75.86


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.29 100.00 93.94 80.00 95.24 u_flash_ctrl_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_word_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.77 80.77


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.77 80.77


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.89 100.00 76.04 89.47 98.94 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_seed_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 87.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 87.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.89 100.00 76.04 89.47 98.94 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_outstanding_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.89 88.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.89 88.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.30 100.00 88.68 100.00 97.83 100.00 gen_flash_cores[0].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_outstanding_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.89 88.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.89 88.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.17 100.00 83.02 100.00 97.83 100.00 gen_flash_cores[1].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_wipe_idx_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.89 100.00 76.04 89.47 98.94 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.10 100.00 91.30 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.10 100.00 91.30 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.09 100.00 82.61 66.67 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.09 100.00 82.61 66.67 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.10 100.00 91.30 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.10 100.00 91.30 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.09 100.00 82.61 66.67 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.09 100.00 82.61 66.67 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_addr_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.91 90.91


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.91 90.91


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.89 100.00 76.04 89.47 98.94 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=10,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
80.77 80.77
tb.dut.u_flash_hw_if.u_word_cnt

TotalCoveredPercent
Totals 8 5 62.50
Total Bits 52 42 80.77
Total Bits 0->1 26 21 80.77
Total Bits 1->0 26 21 80.77

Ports 8 5 62.50
Port Bits 52 42 80.77
Port Bits 0->1 26 21 80.77
Port Bits 1->0 26 21 80.77

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T5,T27,T28 Yes T5,T27,T28 INPUT
set_i Yes Yes T5,T27,T29 Yes T5,T27,T29 INPUT
set_cnt_i[9:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T5,T27,T28 Yes T5,T27,T28 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[9:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] No No No OUTPUT
cnt_o[9:2] Yes Yes T5,T27,T28 Yes T5,T27,T28 OUTPUT
cnt_after_commit_o[1:0] No No No OUTPUT
cnt_after_commit_o[9:2] Yes Yes T5,T27,T28 Yes T5,T27,T28 OUTPUT
err_o No No No OUTPUT


Toggle Coverage for Module : prim_count ( parameter Width=12,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
55.17 55.17
tb.dut.u_flash_ctrl_prog.u_cnt

SCORETOGGLE
75.86 75.86
tb.dut.u_flash_ctrl_rd.u_cnt

TotalCoveredPercent
Totals 7 4 57.14
Total Bits 58 44 75.86
Total Bits 0->1 29 22 75.86
Total Bits 1->0 29 22 75.86

Ports 7 4 57.14
Port Bits 58 44 75.86
Port Bits 0->1 29 22 75.86
Port Bits 1->0 29 22 75.86

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[11:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[11:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[8:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
cnt_o[11:9] No No No OUTPUT
cnt_after_commit_o[8:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[11:9] No No No OUTPUT
err_o No No No OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Module : prim_count ( parameter Width=2,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
87.50 87.50
tb.dut.u_flash_hw_if.u_seed_cnt

SCORETOGGLE
70.00 70.00
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORETOGGLE
70.00 70.00
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

SCORETOGGLE
70.00 70.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORETOGGLE
70.00 70.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

SCORETOGGLE
88.89 88.89
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_outstanding_cnt

SCORETOGGLE
90.00 90.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORETOGGLE
90.00 90.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

SCORETOGGLE
90.00 90.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORETOGGLE
90.00 90.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

SCORETOGGLE
70.00 70.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORETOGGLE
70.00 70.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

SCORETOGGLE
88.89 88.89
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_outstanding_cnt

SCORETOGGLE
90.00 90.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORETOGGLE
90.00 90.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

SCORETOGGLE
90.00 90.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORETOGGLE
90.00 90.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

TotalCoveredPercent
Totals 9 8 88.89
Total Bits 22 20 90.91
Total Bits 0->1 11 10 90.91
Total Bits 1->0 11 10 90.91

Ports 9 8 88.89
Port Bits 22 20 90.91
Port Bits 0->1 11 10 90.91
Port Bits 1->0 11 10 90.91

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Yes Yes T2,T17,T22 Yes T2,T17,T22 INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o No No No OUTPUT


Toggle Coverage for Module : prim_count ( parameter Width=3,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
90.91 90.91
tb.dut.u_flash_hw_if.u_addr_cnt

SCORETOGGLE
90.00 90.00
tb.dut.u_flash_hw_if.u_wipe_idx_cnt

TotalCoveredPercent
Totals 7 6 85.71
Total Bits 22 20 90.91
Total Bits 0->1 11 10 90.91
Total Bits 1->0 11 10 90.91

Ports 7 6 85.71
Port Bits 22 20 90.91
Port Bits 0->1 11 10 90.91
Port Bits 1->0 11 10 90.91

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[2:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[2:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o No No No OUTPUT


Toggle Coverage for Module : prim_count ( parameter Width=9,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
75.76 75.76
tb.dut.u_flash_hw_if.u_page_cnt

TotalCoveredPercent
Totals 9 7 77.78
Total Bits 66 50 75.76
Total Bits 0->1 33 25 75.76
Total Bits 1->0 33 25 75.76

Ports 9 7 77.78
Port Bits 66 50 75.76
Port Bits 0->1 33 25 75.76
Port Bits 1->0 33 25 75.76

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T5,T27,T28 Yes T5,T27,T28 INPUT
set_i Yes Yes T1,T5,T23 Yes T1,T5,T23 INPUT
set_cnt_i[1:0] Yes Yes T5,T27,T28 Yes T5,T27,T28 INPUT
set_cnt_i[8:2] No No No INPUT
incr_en_i Yes Yes T5,T27,T28 Yes T5,T27,T28 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[8:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[8:0] Yes Yes T1,T5,T23 Yes T1,T5,T23 OUTPUT
cnt_after_commit_o[8:0] Yes Yes T1,T5,T23 Yes T1,T5,T23 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_flash_ctrl_prog.u_cnt
TotalCoveredPercent
Totals 7 4 57.14
Total Bits 58 32 55.17
Total Bits 0->1 29 16 55.17
Total Bits 1->0 29 16 55.17

Ports 7 4 57.14
Port Bits 58 32 55.17
Port Bits 0->1 29 16 55.17
Port Bits 1->0 29 16 55.17

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[11:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[11:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[5:0] Yes Yes *T2,*T6,*T5 Yes T2,T6,T5 OUTPUT
cnt_o[11:6] No No No OUTPUT
cnt_after_commit_o[5:0] Yes Yes *T2,*T6,*T5 Yes T2,T6,T5 OUTPUT
cnt_after_commit_o[11:6] No No No OUTPUT
err_o No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr
TotalCoveredPercent
Totals 8 5 62.50
Total Bits 20 14 70.00
Total Bits 0->1 10 7 70.00
Total Bits 1->0 10 7 70.00

Ports 8 5 62.50
Port Bits 20 14 70.00
Port Bits 0->1 10 7 70.00
Port Bits 1->0 10 7 70.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
incr_en_i Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[0] No No No OUTPUT
cnt_o[1] Yes Yes T2,T6,T5 Yes T2,T6,T5 OUTPUT
cnt_after_commit_o[0] No No No OUTPUT
cnt_after_commit_o[1] Yes Yes T2,T6,T5 Yes T2,T6,T5 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr
TotalCoveredPercent
Totals 8 5 62.50
Total Bits 20 14 70.00
Total Bits 0->1 10 7 70.00
Total Bits 1->0 10 7 70.00

Ports 8 5 62.50
Port Bits 20 14 70.00
Port Bits 0->1 10 7 70.00
Port Bits 1->0 10 7 70.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
incr_en_i Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[0] No No No OUTPUT
cnt_o[1] Yes Yes T2,T6,T5 Yes T2,T6,T5 OUTPUT
cnt_after_commit_o[0] No No No OUTPUT
cnt_after_commit_o[1] Yes Yes T2,T6,T5 Yes T2,T6,T5 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr
TotalCoveredPercent
Totals 8 5 62.50
Total Bits 20 14 70.00
Total Bits 0->1 10 7 70.00
Total Bits 1->0 10 7 70.00

Ports 8 5 62.50
Port Bits 20 14 70.00
Port Bits 0->1 10 7 70.00
Port Bits 1->0 10 7 70.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T2,T17,T25 Yes T2,T17,T25 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T2,T17,T25 Yes T2,T17,T25 INPUT
incr_en_i Yes Yes T2,T17,T25 Yes T2,T17,T25 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[0] No No No OUTPUT
cnt_o[1] Yes Yes T2,T17,T25 Yes T2,T17,T25 OUTPUT
cnt_after_commit_o[0] No No No OUTPUT
cnt_after_commit_o[1] Yes Yes T2,T17,T25 Yes T2,T17,T25 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr
TotalCoveredPercent
Totals 8 5 62.50
Total Bits 20 14 70.00
Total Bits 0->1 10 7 70.00
Total Bits 1->0 10 7 70.00

Ports 8 5 62.50
Port Bits 20 14 70.00
Port Bits 0->1 10 7 70.00
Port Bits 1->0 10 7 70.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T2,T17,T25 Yes T2,T17,T25 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T2,T17,T25 Yes T2,T17,T25 INPUT
incr_en_i Yes Yes T2,T17,T25 Yes T2,T17,T25 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[0] No No No OUTPUT
cnt_o[1] Yes Yes T2,T17,T25 Yes T2,T17,T25 OUTPUT
cnt_after_commit_o[0] No No No OUTPUT
cnt_after_commit_o[1] Yes Yes T2,T17,T25 Yes T2,T17,T25 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr
TotalCoveredPercent
Totals 8 5 62.50
Total Bits 20 14 70.00
Total Bits 0->1 10 7 70.00
Total Bits 1->0 10 7 70.00

Ports 8 5 62.50
Port Bits 20 14 70.00
Port Bits 0->1 10 7 70.00
Port Bits 1->0 10 7 70.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T2,T17,T22 Yes T2,T17,T22 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T2,T17,T22 Yes T2,T17,T22 INPUT
incr_en_i Yes Yes T2,T17,T22 Yes T2,T17,T22 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[0] No No No OUTPUT
cnt_o[1] Yes Yes T2,T17,T22 Yes T2,T17,T22 OUTPUT
cnt_after_commit_o[0] No No No OUTPUT
cnt_after_commit_o[1] Yes Yes T2,T17,T22 Yes T2,T17,T22 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr
TotalCoveredPercent
Totals 8 5 62.50
Total Bits 20 14 70.00
Total Bits 0->1 10 7 70.00
Total Bits 1->0 10 7 70.00

Ports 8 5 62.50
Port Bits 20 14 70.00
Port Bits 0->1 10 7 70.00
Port Bits 1->0 10 7 70.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T2,T17,T22 Yes T2,T17,T22 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T2,T17,T22 Yes T2,T17,T22 INPUT
incr_en_i Yes Yes T2,T17,T22 Yes T2,T17,T22 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[0] No No No OUTPUT
cnt_o[1] Yes Yes T2,T17,T22 Yes T2,T17,T22 OUTPUT
cnt_after_commit_o[0] No No No OUTPUT
cnt_after_commit_o[1] Yes Yes T2,T17,T22 Yes T2,T17,T22 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_flash_hw_if.u_page_cnt
TotalCoveredPercent
Totals 9 7 77.78
Total Bits 66 50 75.76
Total Bits 0->1 33 25 75.76
Total Bits 1->0 33 25 75.76

Ports 9 7 77.78
Port Bits 66 50 75.76
Port Bits 0->1 33 25 75.76
Port Bits 1->0 33 25 75.76

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T5,T27,T28 Yes T5,T27,T28 INPUT
set_i Yes Yes T1,T5,T23 Yes T1,T5,T23 INPUT
set_cnt_i[1:0] Yes Yes T5,T27,T28 Yes T5,T27,T28 INPUT
set_cnt_i[8:2] No No No INPUT
incr_en_i Yes Yes T5,T27,T28 Yes T5,T27,T28 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[8:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[8:0] Yes Yes T1,T5,T23 Yes T1,T5,T23 OUTPUT
cnt_after_commit_o[8:0] Yes Yes T1,T5,T23 Yes T1,T5,T23 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_flash_ctrl_rd.u_cnt
TotalCoveredPercent
Totals 7 4 57.14
Total Bits 58 44 75.86
Total Bits 0->1 29 22 75.86
Total Bits 1->0 29 22 75.86

Ports 7 4 57.14
Port Bits 58 44 75.86
Port Bits 0->1 29 22 75.86
Port Bits 1->0 29 22 75.86

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[11:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[11:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[8:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
cnt_o[11:9] No No No OUTPUT
cnt_after_commit_o[8:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[11:9] No No No OUTPUT
err_o No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_flash_hw_if.u_word_cnt
TotalCoveredPercent
Totals 8 5 62.50
Total Bits 52 42 80.77
Total Bits 0->1 26 21 80.77
Total Bits 1->0 26 21 80.77

Ports 8 5 62.50
Port Bits 52 42 80.77
Port Bits 0->1 26 21 80.77
Port Bits 1->0 26 21 80.77

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T5,T27,T28 Yes T5,T27,T28 INPUT
set_i Yes Yes T5,T27,T29 Yes T5,T27,T29 INPUT
set_cnt_i[9:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T5,T27,T28 Yes T5,T27,T28 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[9:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] No No No OUTPUT
cnt_o[9:2] Yes Yes T5,T27,T28 Yes T5,T27,T28 OUTPUT
cnt_after_commit_o[1:0] No No No OUTPUT
cnt_after_commit_o[9:2] Yes Yes T5,T27,T28 Yes T5,T27,T28 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_flash_hw_if.u_seed_cnt
TotalCoveredPercent
Totals 6 5 83.33
Total Bits 16 14 87.50
Total Bits 0->1 8 7 87.50
Total Bits 1->0 8 7 87.50

Ports 6 5 83.33
Port Bits 16 14 87.50
Port Bits 0->1 8 7 87.50
Port Bits 1->0 8 7 87.50

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[1:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_outstanding_cnt
TotalCoveredPercent
Totals 7 6 85.71
Total Bits 18 16 88.89
Total Bits 0->1 9 8 88.89
Total Bits 1->0 9 8 88.89

Ports 7 6 85.71
Port Bits 18 16 88.89
Port Bits 0->1 9 8 88.89
Port Bits 1->0 9 8 88.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[1:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T2,T17,T25 Yes T2,T17,T25 INPUT
decr_en_i Yes Yes T2,T17,T25 Yes T2,T17,T25 INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T2,T17,T25 Yes T2,T17,T25 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T2,T17,T25 Yes T2,T17,T25 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_outstanding_cnt
TotalCoveredPercent
Totals 7 6 85.71
Total Bits 18 16 88.89
Total Bits 0->1 9 8 88.89
Total Bits 1->0 9 8 88.89

Ports 7 6 85.71
Port Bits 18 16 88.89
Port Bits 0->1 9 8 88.89
Port Bits 1->0 9 8 88.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[1:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T2,T17,T22 Yes T2,T17,T22 INPUT
decr_en_i Yes Yes T2,T17,T22 Yes T2,T17,T22 INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T2,T17,T22 Yes T2,T17,T22 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T2,T17,T22 Yes T2,T17,T22 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_flash_hw_if.u_wipe_idx_cnt
TotalCoveredPercent
Totals 6 5 83.33
Total Bits 20 18 90.00
Total Bits 0->1 10 9 90.00
Total Bits 1->0 10 9 90.00

Ports 6 5 83.33
Port Bits 20 18 90.00
Port Bits 0->1 10 9 90.00
Port Bits 1->0 10 9 90.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[2:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T5,T27,T28 Yes T5,T27,T28 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[2:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[2:0] Yes Yes T5,T27,T28 Yes T5,T27,T28 OUTPUT
cnt_after_commit_o[2:0] Yes Yes T5,T27,T28 Yes T5,T27,T28 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr
TotalCoveredPercent
Totals 8 7 87.50
Total Bits 20 18 90.00
Total Bits 0->1 10 9 90.00
Total Bits 1->0 10 9 90.00

Ports 8 7 87.50
Port Bits 20 18 90.00
Port Bits 0->1 10 9 90.00
Port Bits 1->0 10 9 90.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr
TotalCoveredPercent
Totals 8 7 87.50
Total Bits 20 18 90.00
Total Bits 0->1 10 9 90.00
Total Bits 1->0 10 9 90.00

Ports 8 7 87.50
Port Bits 20 18 90.00
Port Bits 0->1 10 9 90.00
Port Bits 1->0 10 9 90.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr
TotalCoveredPercent
Totals 8 7 87.50
Total Bits 20 18 90.00
Total Bits 0->1 10 9 90.00
Total Bits 1->0 10 9 90.00

Ports 8 7 87.50
Port Bits 20 18 90.00
Port Bits 0->1 10 9 90.00
Port Bits 1->0 10 9 90.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr
TotalCoveredPercent
Totals 8 7 87.50
Total Bits 20 18 90.00
Total Bits 0->1 10 9 90.00
Total Bits 1->0 10 9 90.00

Ports 8 7 87.50
Port Bits 20 18 90.00
Port Bits 0->1 10 9 90.00
Port Bits 1->0 10 9 90.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr
TotalCoveredPercent
Totals 8 7 87.50
Total Bits 20 18 90.00
Total Bits 0->1 10 9 90.00
Total Bits 1->0 10 9 90.00

Ports 8 7 87.50
Port Bits 20 18 90.00
Port Bits 0->1 10 9 90.00
Port Bits 1->0 10 9 90.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
incr_en_i Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T2,T6,T5 Yes T2,T6,T5 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T2,T6,T5 Yes T2,T6,T5 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr
TotalCoveredPercent
Totals 8 7 87.50
Total Bits 20 18 90.00
Total Bits 0->1 10 9 90.00
Total Bits 1->0 10 9 90.00

Ports 8 7 87.50
Port Bits 20 18 90.00
Port Bits 0->1 10 9 90.00
Port Bits 1->0 10 9 90.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
incr_en_i Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T2,T6,T5 Yes T2,T6,T5 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T2,T6,T5 Yes T2,T6,T5 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr
TotalCoveredPercent
Totals 8 7 87.50
Total Bits 20 18 90.00
Total Bits 0->1 10 9 90.00
Total Bits 1->0 10 9 90.00

Ports 8 7 87.50
Port Bits 20 18 90.00
Port Bits 0->1 10 9 90.00
Port Bits 1->0 10 9 90.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
incr_en_i Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T2,T6,T5 Yes T2,T6,T5 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T2,T6,T5 Yes T2,T6,T5 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr
TotalCoveredPercent
Totals 8 7 87.50
Total Bits 20 18 90.00
Total Bits 0->1 10 9 90.00
Total Bits 1->0 10 9 90.00

Ports 8 7 87.50
Port Bits 20 18 90.00
Port Bits 0->1 10 9 90.00
Port Bits 1->0 10 9 90.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
incr_en_i Yes Yes T2,T6,T5 Yes T2,T6,T5 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T2,T6,T5 Yes T2,T6,T5 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T2,T6,T5 Yes T2,T6,T5 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_flash_hw_if.u_addr_cnt
TotalCoveredPercent
Totals 7 6 85.71
Total Bits 22 20 90.91
Total Bits 0->1 11 10 90.91
Total Bits 1->0 11 10 90.91

Ports 7 6 85.71
Port Bits 22 20 90.91
Port Bits 0->1 11 10 90.91
Port Bits 1->0 11 10 90.91

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[2:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[2:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o No No No OUTPUT

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