Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 97.92 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 95.83 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
95.83 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 1 15 93.75


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 1 15 93.75 100 1 1 0


Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 23287589 1 T1 32820 T2 34031 T3 119
full_word 7245655 1 T1 27460 T2 197 T3 43


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 30532944 1 T1 60280 T2 34228 T3 162
auto[TlIntgErrCmd] 84 1 T63 5 T231 2 T232 6
auto[TlIntgErrData] 106 1 T63 8 T231 8 T232 3
auto[TlIntgErrBoth] 110 1 T63 7 T231 10 T232 1


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 26638442 1 T1 41821 T2 34113 T3 115
auto[1] 3894802 1 T1 18459 T2 115 T3 47


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 1 15 93.75 1


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBER
[auto[TlIntgErrCmd]] [full_word] [auto[1]] 0 1 1


Covered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 22705434 1 T1 31439 T2 34013 T3 115
auto[TlIntgErrNone] partial auto[1] 581881 1 T1 1381 T2 18 T3 4
auto[TlIntgErrNone] full_word auto[0] 3932869 1 T1 10382 T2 100 T6 158
auto[TlIntgErrNone] full_word auto[1] 3312760 1 T1 17078 T2 97 T3 43
auto[TlIntgErrCmd] partial auto[0] 26 1 T63 1 T231 1 T232 3
auto[TlIntgErrCmd] partial auto[1] 53 1 T63 3 T231 1 T232 3
auto[TlIntgErrCmd] full_word auto[0] 5 1 T63 1 T327 1 T328 1
auto[TlIntgErrData] partial auto[0] 50 1 T63 3 T231 6 T232 1
auto[TlIntgErrData] partial auto[1] 45 1 T63 4 T231 1 T232 2
auto[TlIntgErrData] full_word auto[0] 7 1 T63 1 T324 1 T326 1
auto[TlIntgErrData] full_word auto[1] 4 1 T231 1 T324 1 T326 1
auto[TlIntgErrBoth] partial auto[0] 46 1 T63 3 T231 3 T232 1
auto[TlIntgErrBoth] partial auto[1] 54 1 T63 4 T231 4 T323 5
auto[TlIntgErrBoth] full_word auto[0] 5 1 T231 2 T324 1 T325 1
auto[TlIntgErrBoth] full_word auto[1] 5 1 T231 1 T323 1 T267 2


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 23228 1 T63 16 T64 902 T67 1042
full_word 3413861 1 T2 105 T16 41253 T4 30


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 3436816 1 T2 105 T16 41253 T4 30
auto[TlIntgErrCmd] 79 1 T63 4 T231 8 T232 1
auto[TlIntgErrData] 106 1 T63 7 T231 6 T232 4
auto[TlIntgErrBoth] 88 1 T63 7 T231 5 T232 4


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3407218 1 T2 105 T16 41253 T4 30
auto[1] 29871 1 T63 15 T64 1146 T67 1312


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 1642 1 T64 59 T67 85 T65 10
auto[TlIntgErrNone] partial auto[1] 21337 1 T64 843 T67 957 T65 99
auto[TlIntgErrNone] full_word auto[0] 3405465 1 T2 105 T16 41253 T4 30
auto[TlIntgErrNone] full_word auto[1] 8372 1 T64 303 T67 355 T65 29
auto[TlIntgErrCmd] partial auto[0] 28 1 T63 1 T231 2 T323 3
auto[TlIntgErrCmd] partial auto[1] 46 1 T63 3 T231 5 T232 1
auto[TlIntgErrCmd] full_word auto[0] 3 1 T231 1 T255 1 T262 1
auto[TlIntgErrCmd] full_word auto[1] 2 1 T323 1 T263 1 - -
auto[TlIntgErrData] partial auto[0] 41 1 T231 3 T323 1 T324 3
auto[TlIntgErrData] partial auto[1] 54 1 T63 6 T231 2 T232 3
auto[TlIntgErrData] full_word auto[0] 7 1 T63 1 T231 1 T323 1
auto[TlIntgErrData] full_word auto[1] 4 1 T232 1 T255 1 T325 1
auto[TlIntgErrBoth] partial auto[0] 31 1 T63 1 T231 1 T232 4
auto[TlIntgErrBoth] partial auto[1] 49 1 T63 5 T231 3 T323 4
auto[TlIntgErrBoth] full_word auto[0] 1 1 T328 1 - - - -
auto[TlIntgErrBoth] full_word auto[1] 7 1 T63 1 T231 1 T323 1

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