Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T16,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T16,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T5,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T16,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T5,T17
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T16,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T16,T4

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1476822540	1474147864	0	0
CheckNGreaterZero_A	3516	3516	0	0
GntImpliesReady_A	1476822540	349701682	0	0
GntImpliesValid_A	1476822540	349701682	0	0
GrantKnown_A	1476822540	1474147864	0	0
IdxKnown_A	1476822540	1474147864	0	0
IndexIsCorrect_A	1476822540	349701682	0	0
NoReadyValidNoGrant_A	1476822540	173213966	0	0
Priority_A	1476822540	371798908	0	0
ReadyAndValidImplyGrant_A	1476822540	349701682	0	0
ReqAndReadyImplyGrant_A	1476822540	349701682	0	0
ReqImpliesValid_A	1476822540	371798908	0	0
ValidKnown_A	1476822540	1474147864	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476822540	1474147864	0	0
T1	1688500	1688268	0	0
T2	281704	281452	0	0
T3	924976	924324	0	0
T4	103956	98744	0	0
T5	3341540	3340928	0	0
T6	9112	8860	0	0
T10	6624	6392	0	0
T16	1759032	1758808	0	0
T17	237340	237048	0	0
T25	4824	4616	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3516	3516	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T10	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T25	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476822540	349701682	0	0
T1	1688500	216736	0	0
T2	281704	135942	0	0
T3	924976	132534	0	0
T4	103956	13400	0	0
T5	3341540	59138	0	0
T6	9112	356	0	0
T10	6624	742	0	0
T14	0	26394	0	0
T15	0	31048	0	0
T16	1759032	575618	0	0
T17	237340	47908	0	0
T25	4824	64	0	0
T83	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476822540	349701682	0	0
T1	1688500	216736	0	0
T2	281704	135942	0	0
T3	924976	132534	0	0
T4	103956	13400	0	0
T5	3341540	59138	0	0
T6	9112	356	0	0
T10	6624	742	0	0
T14	0	26394	0	0
T15	0	31048	0	0
T16	1759032	575618	0	0
T17	237340	47908	0	0
T25	4824	64	0	0
T83	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476822540	1474147864	0	0
T1	1688500	1688268	0	0
T2	281704	281452	0	0
T3	924976	924324	0	0
T4	103956	98744	0	0
T5	3341540	3340928	0	0
T6	9112	8860	0	0
T10	6624	6392	0	0
T16	1759032	1758808	0	0
T17	237340	237048	0	0
T25	4824	4616	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476822540	1474147864	0	0
T1	1688500	1688268	0	0
T2	281704	281452	0	0
T3	924976	924324	0	0
T4	103956	98744	0	0
T5	3341540	3340928	0	0
T6	9112	8860	0	0
T10	6624	6392	0	0
T16	1759032	1758808	0	0
T17	237340	237048	0	0
T25	4824	4616	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476822540	349701682	0	0
T1	1688500	216736	0	0
T2	281704	135942	0	0
T3	924976	132534	0	0
T4	103956	13400	0	0
T5	3341540	59138	0	0
T6	9112	356	0	0
T10	6624	742	0	0
T14	0	26394	0	0
T15	0	31048	0	0
T16	1759032	575618	0	0
T17	237340	47908	0	0
T25	4824	64	0	0
T83	0	16	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476822540	173213966	0	0
T1	1688500	14970	0	0
T2	281704	856	0	0
T3	924976	175266	0	0
T4	103956	5200	0	0
T5	3341540	1872032	0	0
T6	9112	992	0	0
T10	6624	284	0	0
T14	0	74568	0	0
T15	0	85802	0	0
T16	1759032	189318	0	0
T17	237340	65422	0	0
T25	4824	256	0	0
T83	0	46	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476822540	371798908	0	0
T1	1688500	216736	0	0
T2	281704	135942	0	0
T3	924976	132534	0	0
T4	103956	13400	0	0
T5	3341540	607172	0	0
T6	9112	356	0	0
T10	6624	742	0	0
T14	0	28616	0	0
T15	0	33696	0	0
T16	1759032	652196	0	0
T17	237340	58738	0	0
T25	4824	64	0	0
T83	0	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476822540	349701682	0	0
T1	1688500	216736	0	0
T2	281704	135942	0	0
T3	924976	132534	0	0
T4	103956	13400	0	0
T5	3341540	59138	0	0
T6	9112	356	0	0
T10	6624	742	0	0
T14	0	26394	0	0
T15	0	31048	0	0
T16	1759032	575618	0	0
T17	237340	47908	0	0
T25	4824	64	0	0
T83	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476822540	349701682	0	0
T1	1688500	216736	0	0
T2	281704	135942	0	0
T3	924976	132534	0	0
T4	103956	13400	0	0
T5	3341540	59138	0	0
T6	9112	356	0	0
T10	6624	742	0	0
T14	0	26394	0	0
T15	0	31048	0	0
T16	1759032	575618	0	0
T17	237340	47908	0	0
T25	4824	64	0	0
T83	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476822540	371798908	0	0
T1	1688500	216736	0	0
T2	281704	135942	0	0
T3	924976	132534	0	0
T4	103956	13400	0	0
T5	3341540	607172	0	0
T6	9112	356	0	0
T10	6624	742	0	0
T14	0	28616	0	0
T15	0	33696	0	0
T16	1759032	652196	0	0
T17	237340	58738	0	0
T25	4824	64	0	0
T83	0	16	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476822540	1474147864	0	0
T1	1688500	1688268	0	0
T2	281704	281452	0	0
T3	924976	924324	0	0
T4	103956	98744	0	0
T5	3341540	3340928	0	0
T6	9112	8860	0	0
T10	6624	6392	0	0
T16	1759032	1758808	0	0
T17	237340	237048	0	0
T25	4824	4616	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T16,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T16,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T5,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T16,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T5,T17
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T16,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T16,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	369205635	368536966	0	0
CheckNGreaterZero_A	879	879	0	0
GntImpliesReady_A	369205635	87372268	0	0
GntImpliesValid_A	369205635	87372268	0	0
GrantKnown_A	369205635	368536966	0	0
IdxKnown_A	369205635	368536966	0	0
IndexIsCorrect_A	369205635	87372268	0	0
NoReadyValidNoGrant_A	369205635	44552574	0	0
Priority_A	369205635	92906115	0	0
ReadyAndValidImplyGrant_A	369205635	87372268	0	0
ReqAndReadyImplyGrant_A	369205635	87372268	0	0
ReqImpliesValid_A	369205635	92906115	0	0
ValidKnown_A	369205635	368536966	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87372268	0	0
T1	422125	78540	0	0
T2	70426	67971	0	0
T3	231244	66267	0	0
T4	25989	4320	0	0
T5	835385	14180	0	0
T6	2278	32	0	0
T10	1656	32	0	0
T16	439758	165786	0	0
T17	59335	11477	0	0
T25	1206	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87372268	0	0
T1	422125	78540	0	0
T2	70426	67971	0	0
T3	231244	66267	0	0
T4	25989	4320	0	0
T5	835385	14180	0	0
T6	2278	32	0	0
T10	1656	32	0	0
T16	439758	165786	0	0
T17	59335	11477	0	0
T25	1206	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87372268	0	0
T1	422125	78540	0	0
T2	70426	67971	0	0
T3	231244	66267	0	0
T4	25989	4320	0	0
T5	835385	14180	0	0
T6	2278	32	0	0
T10	1656	32	0	0
T16	439758	165786	0	0
T17	59335	11477	0	0
T25	1206	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	44552574	0	0
T1	422125	4982	0	0
T2	70426	428	0	0
T3	231244	87633	0	0
T4	25989	2495	0	0
T5	835385	455479	0	0
T6	2278	128	0	0
T10	1656	128	0	0
T16	439758	58099	0	0
T17	59335	15025	0	0
T25	1206	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	92906115	0	0
T1	422125	78540	0	0
T2	70426	67971	0	0
T3	231244	66267	0	0
T4	25989	4320	0	0
T5	835385	133446	0	0
T6	2278	32	0	0
T10	1656	32	0	0
T16	439758	194915	0	0
T17	59335	14593	0	0
T25	1206	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87372268	0	0
T1	422125	78540	0	0
T2	70426	67971	0	0
T3	231244	66267	0	0
T4	25989	4320	0	0
T5	835385	14180	0	0
T6	2278	32	0	0
T10	1656	32	0	0
T16	439758	165786	0	0
T17	59335	11477	0	0
T25	1206	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87372268	0	0
T1	422125	78540	0	0
T2	70426	67971	0	0
T3	231244	66267	0	0
T4	25989	4320	0	0
T5	835385	14180	0	0
T6	2278	32	0	0
T10	1656	32	0	0
T16	439758	165786	0	0
T17	59335	11477	0	0
T25	1206	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	92906115	0	0
T1	422125	78540	0	0
T2	70426	67971	0	0
T3	231244	66267	0	0
T4	25989	4320	0	0
T5	835385	133446	0	0
T6	2278	32	0	0
T10	1656	32	0	0
T16	439758	194915	0	0
T17	59335	14593	0	0
T25	1206	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T16,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T16,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T5,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T16,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T5,T17
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T16,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T16,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	369205635	368536966	0	0
CheckNGreaterZero_A	879	879	0	0
GntImpliesReady_A	369205635	87372022	0	0
GntImpliesValid_A	369205635	87372022	0	0
GrantKnown_A	369205635	368536966	0	0
IdxKnown_A	369205635	368536966	0	0
IndexIsCorrect_A	369205635	87372022	0	0
NoReadyValidNoGrant_A	369205635	44552576	0	0
Priority_A	369205635	92905867	0	0
ReadyAndValidImplyGrant_A	369205635	87372022	0	0
ReqAndReadyImplyGrant_A	369205635	87372022	0	0
ReqImpliesValid_A	369205635	92905867	0	0
ValidKnown_A	369205635	368536966	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87372022	0	0
T1	422125	78540	0	0
T2	70426	67971	0	0
T3	231244	66267	0	0
T4	25989	4320	0	0
T5	835385	14180	0	0
T6	2278	32	0	0
T10	1656	32	0	0
T16	439758	165786	0	0
T17	59335	11477	0	0
T25	1206	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87372022	0	0
T1	422125	78540	0	0
T2	70426	67971	0	0
T3	231244	66267	0	0
T4	25989	4320	0	0
T5	835385	14180	0	0
T6	2278	32	0	0
T10	1656	32	0	0
T16	439758	165786	0	0
T17	59335	11477	0	0
T25	1206	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87372022	0	0
T1	422125	78540	0	0
T2	70426	67971	0	0
T3	231244	66267	0	0
T4	25989	4320	0	0
T5	835385	14180	0	0
T6	2278	32	0	0
T10	1656	32	0	0
T16	439758	165786	0	0
T17	59335	11477	0	0
T25	1206	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	44552576	0	0
T1	422125	4982	0	0
T2	70426	428	0	0
T3	231244	87633	0	0
T4	25989	2495	0	0
T5	835385	455479	0	0
T6	2278	128	0	0
T10	1656	128	0	0
T16	439758	58099	0	0
T17	59335	15025	0	0
T25	1206	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	92905867	0	0
T1	422125	78540	0	0
T2	70426	67971	0	0
T3	231244	66267	0	0
T4	25989	4320	0	0
T5	835385	133446	0	0
T6	2278	32	0	0
T10	1656	32	0	0
T16	439758	194915	0	0
T17	59335	14593	0	0
T25	1206	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87372022	0	0
T1	422125	78540	0	0
T2	70426	67971	0	0
T3	231244	66267	0	0
T4	25989	4320	0	0
T5	835385	14180	0	0
T6	2278	32	0	0
T10	1656	32	0	0
T16	439758	165786	0	0
T17	59335	11477	0	0
T25	1206	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87372022	0	0
T1	422125	78540	0	0
T2	70426	67971	0	0
T3	231244	66267	0	0
T4	25989	4320	0	0
T5	835385	14180	0	0
T6	2278	32	0	0
T10	1656	32	0	0
T16	439758	165786	0	0
T17	59335	11477	0	0
T25	1206	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	92905867	0	0
T1	422125	78540	0	0
T2	70426	67971	0	0
T3	231244	66267	0	0
T4	25989	4320	0	0
T5	835385	133446	0	0
T6	2278	32	0	0
T10	1656	32	0	0
T16	439758	194915	0	0
T17	59335	14593	0	0
T25	1206	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T10
1	0	Covered	T16,T5,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T16,T5,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T16,T5,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T5,T17
1	0	Covered	T1,T6,T10
1	1	Covered	T16,T5,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T5,T17
1	1	Covered	T1,T6,T10

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T5,T17
1	1	Covered	T1,T6,T10

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T16,T5,T17

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T16,T5,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	369205635	368536966	0	0
CheckNGreaterZero_A	879	879	0	0
GntImpliesReady_A	369205635	87478662	0	0
GntImpliesValid_A	369205635	87478662	0	0
GrantKnown_A	369205635	368536966	0	0
IdxKnown_A	369205635	368536966	0	0
IndexIsCorrect_A	369205635	87478662	0	0
NoReadyValidNoGrant_A	369205635	42054414	0	0
Priority_A	369205635	92993423	0	0
ReadyAndValidImplyGrant_A	369205635	87478662	0	0
ReqAndReadyImplyGrant_A	369205635	87478662	0	0
ReqImpliesValid_A	369205635	92993423	0	0
ValidKnown_A	369205635	368536966	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87478662	0	0
T1	422125	29828	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	2380	0	0
T5	835385	15389	0	0
T6	2278	146	0	0
T10	1656	339	0	0
T14	0	13197	0	0
T15	0	15524	0	0
T16	439758	122023	0	0
T17	59335	12477	0	0
T25	1206	0	0	0
T83	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87478662	0	0
T1	422125	29828	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	2380	0	0
T5	835385	15389	0	0
T6	2278	146	0	0
T10	1656	339	0	0
T14	0	13197	0	0
T15	0	15524	0	0
T16	439758	122023	0	0
T17	59335	12477	0	0
T25	1206	0	0	0
T83	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87478662	0	0
T1	422125	29828	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	2380	0	0
T5	835385	15389	0	0
T6	2278	146	0	0
T10	1656	339	0	0
T14	0	13197	0	0
T15	0	15524	0	0
T16	439758	122023	0	0
T17	59335	12477	0	0
T25	1206	0	0	0
T83	0	8	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	42054414	0	0
T1	422125	2503	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	105	0	0
T5	835385	480537	0	0
T6	2278	368	0	0
T10	1656	14	0	0
T14	0	37284	0	0
T15	0	42901	0	0
T16	439758	36560	0	0
T17	59335	17686	0	0
T25	1206	0	0	0
T83	0	23	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	92993423	0	0
T1	422125	29828	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	2380	0	0
T5	835385	170140	0	0
T6	2278	146	0	0
T10	1656	339	0	0
T14	0	14308	0	0
T15	0	16848	0	0
T16	439758	131183	0	0
T17	59335	14776	0	0
T25	1206	0	0	0
T83	0	8	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87478662	0	0
T1	422125	29828	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	2380	0	0
T5	835385	15389	0	0
T6	2278	146	0	0
T10	1656	339	0	0
T14	0	13197	0	0
T15	0	15524	0	0
T16	439758	122023	0	0
T17	59335	12477	0	0
T25	1206	0	0	0
T83	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87478662	0	0
T1	422125	29828	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	2380	0	0
T5	835385	15389	0	0
T6	2278	146	0	0
T10	1656	339	0	0
T14	0	13197	0	0
T15	0	15524	0	0
T16	439758	122023	0	0
T17	59335	12477	0	0
T25	1206	0	0	0
T83	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	92993423	0	0
T1	422125	29828	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	2380	0	0
T5	835385	170140	0	0
T6	2278	146	0	0
T10	1656	339	0	0
T14	0	14308	0	0
T15	0	16848	0	0
T16	439758	131183	0	0
T17	59335	14776	0	0
T25	1206	0	0	0
T83	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T10
1	0	Covered	T16,T5,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T16,T5,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T16,T5,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T5,T17
1	0	Covered	T1,T6,T10
1	1	Covered	T16,T5,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T5,T17
1	1	Covered	T1,T6,T10

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T5,T17
1	1	Covered	T1,T6,T10

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T16,T5,T17

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T16,T5,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	369205635	368536966	0	0
CheckNGreaterZero_A	879	879	0	0
GntImpliesReady_A	369205635	87478730	0	0
GntImpliesValid_A	369205635	87478730	0	0
GrantKnown_A	369205635	368536966	0	0
IdxKnown_A	369205635	368536966	0	0
IndexIsCorrect_A	369205635	87478730	0	0
NoReadyValidNoGrant_A	369205635	42054402	0	0
Priority_A	369205635	92993503	0	0
ReadyAndValidImplyGrant_A	369205635	87478730	0	0
ReqAndReadyImplyGrant_A	369205635	87478730	0	0
ReqImpliesValid_A	369205635	92993503	0	0
ValidKnown_A	369205635	368536966	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87478730	0	0
T1	422125	29828	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	2380	0	0
T5	835385	15389	0	0
T6	2278	146	0	0
T10	1656	339	0	0
T14	0	13197	0	0
T15	0	15524	0	0
T16	439758	122023	0	0
T17	59335	12477	0	0
T25	1206	0	0	0
T83	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87478730	0	0
T1	422125	29828	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	2380	0	0
T5	835385	15389	0	0
T6	2278	146	0	0
T10	1656	339	0	0
T14	0	13197	0	0
T15	0	15524	0	0
T16	439758	122023	0	0
T17	59335	12477	0	0
T25	1206	0	0	0
T83	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87478730	0	0
T1	422125	29828	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	2380	0	0
T5	835385	15389	0	0
T6	2278	146	0	0
T10	1656	339	0	0
T14	0	13197	0	0
T15	0	15524	0	0
T16	439758	122023	0	0
T17	59335	12477	0	0
T25	1206	0	0	0
T83	0	8	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	42054402	0	0
T1	422125	2503	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	105	0	0
T5	835385	480537	0	0
T6	2278	368	0	0
T10	1656	14	0	0
T14	0	37284	0	0
T15	0	42901	0	0
T16	439758	36560	0	0
T17	59335	17686	0	0
T25	1206	0	0	0
T83	0	23	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	92993503	0	0
T1	422125	29828	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	2380	0	0
T5	835385	170140	0	0
T6	2278	146	0	0
T10	1656	339	0	0
T14	0	14308	0	0
T15	0	16848	0	0
T16	439758	131183	0	0
T17	59335	14776	0	0
T25	1206	0	0	0
T83	0	8	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87478730	0	0
T1	422125	29828	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	2380	0	0
T5	835385	15389	0	0
T6	2278	146	0	0
T10	1656	339	0	0
T14	0	13197	0	0
T15	0	15524	0	0
T16	439758	122023	0	0
T17	59335	12477	0	0
T25	1206	0	0	0
T83	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	87478730	0	0
T1	422125	29828	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	2380	0	0
T5	835385	15389	0	0
T6	2278	146	0	0
T10	1656	339	0	0
T14	0	13197	0	0
T15	0	15524	0	0
T16	439758	122023	0	0
T17	59335	12477	0	0
T25	1206	0	0	0
T83	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	92993503	0	0
T1	422125	29828	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	2380	0	0
T5	835385	170140	0	0
T6	2278	146	0	0
T10	1656	339	0	0
T14	0	14308	0	0
T15	0	16848	0	0
T16	439758	131183	0	0
T17	59335	14776	0	0
T25	1206	0	0	0
T83	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0