Unified Coverage Report :: Module :: prim_arbiter_tree

Module : prim_arbiter_tree

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.49	96.15	97.80			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random	94.17	92.31	97.69			100.00	86.67
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random	94.17	92.31	97.69			100.00	86.67
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb	95.50	100.00	88.24			100.00	93.75
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb	97.86	100.00	97.67			100.00	93.75
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb	97.86	100.00	97.67			100.00	93.75
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb	97.95	100.00	98.04			100.00	93.75

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.17	92.31	97.69			100.00	86.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.17	92.31	97.69			100.00	86.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.41	100.00	89.65			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.17	92.31	97.69			100.00	86.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.17	92.31	97.69			100.00	86.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.25	100.00	88.99			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.50	100.00	88.24			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.50	100.00	88.24			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_prim_arbiter_tree_op

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86	100.00	97.67			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86	100.00	97.67			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00	40.00			100.00		u_prim_arbiter_tree_calc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86	100.00	97.67			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86	100.00	97.67			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00	40.00			100.00		u_prim_arbiter_tree_calc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.95	100.00	98.04			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.95	100.00	98.04			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_prim_arbiter_tree_op

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Line Coverage for Module self-instances :

SCORE	LINE
94.17	92.31

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORE	LINE
94.17	92.31

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
TOTAL		52	48	92.31
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	4	4
118	4	4
122	0	4
126	4	4
128	4	4
148	3	3
150	3	3
151	3	3
155	3	3
156	3	3
160	3	3
161	3	3
163	1	1(2 unreachable)
164	3	3
174	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Line Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Line Coverage for Module self-instances :

SCORE	LINE
97.86	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	LINE
97.86	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

SCORE	LINE
95.50	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	LINE
97.95	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126	2	2
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :

SCORE	COND
97.86	97.67

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	COND
97.86	97.67

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	43	42	97.67
Logical	43	42	97.67
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T17,T14
1	1	Covered	T6,T17,T14

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T17,T14,T15
1	1	0	Covered	T1,T2,T3
1	1	1	Unreachable	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T17,T14,T15
1	1	0	Covered	T6,T17,T14
1	1	1	Unreachable	T6,T17,T14

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T17,T14
1	0	Unreachable	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T6,T17,T14
0	1	Covered	T6,T17,T14
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T6,T17,T14
1	1	Covered	T6,T17,T14

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T14,T15
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T17,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T17,T14

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T17,T14
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T17,T14

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :

SCORE	COND
95.50	88.24

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	COND
97.95	98.04

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	51	50	98.04
Logical	51	50	98.04
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T134
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T14,T15
1	1	Covered	T6,T14,T15

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T134
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T134
1	0	1	Covered	T134
1	1	0	Covered	T6,T14,T15
1	1	1	Covered	T6,T14,T15

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T6,T14,T15
0	1	Covered	T6,T14,T15
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T14,T15
1	1	Covered	T6,T14,T15

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T134
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T134
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T14,T15

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T14,T15
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T14,T15

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Cond Coverage for Module self-instances :

SCORE	COND
94.17	97.69

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORE	COND
94.17	97.69

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Total	Covered	Percent
Conditions	130	127	97.69
Logical	130	127	97.69
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T5
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T16,T39,T149
1	1	Covered	T1,T2,T6

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T1,T2,T6
1	1	1	Covered	T1,T2,T6

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T1,T2,T6
1	1	1	Covered	T1,T2,T6

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T1,T2,T6
1	1	1	Covered	T1,T2,T6

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T1,T2,T6
1	1	1	Covered	T1,T2,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T42
1	0	Covered	T14,T15,T42

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T42
1	0	Covered	T1,T2,T6

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T5,T17
1	0	Covered	T1,T2,T6

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T5,T17
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T6
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T6
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6

---

Branch Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
94.17	100.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORE	BRANCH
94.17	100.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
97.86	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	BRANCH
97.86	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

SCORE	BRANCH
95.50	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	BRANCH
97.95	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_tree

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	5274	5274	0	0
GntImpliesReady_A	2147483647	67406876	0	0
GntImpliesValid_A	2147483647	67406876	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	67406876	0	0
LockArbDecision_A	2147483647	62917082	0	0
NoReadyValidNoGrant_A	2147483647	1850595582	0	0
ReadyAndValidImplyGrant_A	2147483647	67406876	0	0
ReqAndReadyImplyGrant_A	2147483647	67406876	0	0
ReqImpliesValid_A	2147483647	350840389	0	0
ReqStaysHighUntilGranted0_M	2147483647	62916902	0	0
RoundRobin_A	2147483647	10967	0	5244
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	1476822540	62917109	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2532750	2532402	0	0
T2	422556	422178	0	0
T3	1387464	1386486	0	0
T4	155934	148116	0	0
T5	5012310	5011392	0	0
T6	13668	13290	0	0
T10	9936	9588	0	0
T16	2638548	2638212	0	0
T17	356010	355572	0	0
T25	7236	6924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5274	5274	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T6	6	6	0	0
T10	6	6	0	0
T16	6	6	0	0
T17	6	6	0	0
T25	6	6	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	67406876	0	0
T1	2532750	2570	0	0
T2	422556	200	0	0
T3	1387464	87632	0	0
T4	155934	2347	0	0
T5	5012310	23867	0	0
T6	13668	494	0	0
T10	9936	129	0	0
T14	0	24889	0	0
T15	0	24664	0	0
T16	2638548	74329	0	0
T17	356010	27781	0	0
T20	0	2040	0	0
T25	7236	128	0	0
T42	0	11164	0	0
T83	0	1	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	67406876	0	0
T1	2532750	2570	0	0
T2	422556	200	0	0
T3	1387464	87632	0	0
T4	155934	2347	0	0
T5	5012310	23867	0	0
T6	13668	494	0	0
T10	9936	129	0	0
T14	0	24889	0	0
T15	0	24664	0	0
T16	2638548	74329	0	0
T17	356010	27781	0	0
T20	0	2040	0	0
T25	7236	128	0	0
T42	0	11164	0	0
T83	0	1	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2532750	2532402	0	0
T2	422556	422178	0	0
T3	1387464	1386486	0	0
T4	155934	148116	0	0
T5	5012310	5011392	0	0
T6	13668	13290	0	0
T10	9936	9588	0	0
T16	2638548	2638212	0	0
T17	356010	355572	0	0
T25	7236	6924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2532750	2532402	0	0
T2	422556	422178	0	0
T3	1387464	1386486	0	0
T4	155934	148116	0	0
T5	5012310	5011392	0	0
T6	13668	13290	0	0
T10	9936	9588	0	0
T16	2638548	2638212	0	0
T17	356010	355572	0	0
T25	7236	6924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	67406876	0	0
T1	2532750	2570	0	0
T2	422556	200	0	0
T3	1387464	87632	0	0
T4	155934	2347	0	0
T5	5012310	23867	0	0
T6	13668	494	0	0
T10	9936	129	0	0
T14	0	24889	0	0
T15	0	24664	0	0
T16	2638548	74329	0	0
T17	356010	27781	0	0
T20	0	2040	0	0
T25	7236	128	0	0
T42	0	11164	0	0
T83	0	1	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	62917082	0	0
T1	1688500	128	0	0
T2	281704	128	0	0
T3	924976	87632	0	0
T4	103956	2304	0	0
T5	3341540	146	0	0
T6	9112	424	0	0
T10	6624	128	0	0
T16	1759032	25028	0	0
T17	237340	7010	0	0
T25	4824	128	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1850595582	0	0
T1	2532750	1731123	0	0
T2	422556	419810	0	0
T3	1387464	1167435	0	0
T4	155934	128626	0	0
T5	5012310	3345456	0	0
T6	13668	10633	0	0
T10	9936	8449	0	0
T16	2638548	1709519	0	0
T17	356010	223799	0	0
T25	7236	6636	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	67406876	0	0
T1	2532750	2570	0	0
T2	422556	200	0	0
T3	1387464	87632	0	0
T4	155934	2347	0	0
T5	5012310	23867	0	0
T6	13668	494	0	0
T10	9936	129	0	0
T14	0	24889	0	0
T15	0	24664	0	0
T16	2638548	74329	0	0
T17	356010	27781	0	0
T20	0	2040	0	0
T25	7236	128	0	0
T42	0	11164	0	0
T83	0	1	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	67406876	0	0
T1	2532750	2570	0	0
T2	422556	200	0	0
T3	1387464	87632	0	0
T4	155934	2347	0	0
T5	5012310	23867	0	0
T6	13668	494	0	0
T10	9936	129	0	0
T14	0	24889	0	0
T15	0	24664	0	0
T16	2638548	74329	0	0
T17	356010	27781	0	0
T20	0	2040	0	0
T25	7236	128	0	0
T42	0	11164	0	0
T83	0	1	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350840389	0	0
T1	2532750	801227	0	0
T2	422556	2300	0	0
T3	1387464	175266	0	0
T4	155934	18852	0	0
T5	5012310	1665891	0	0
T6	13668	2621	0	0
T10	9936	1103	0	0
T14	0	260987	0	0
T15	0	214895	0	0
T16	2638548	928653	0	0
T17	356010	131733	0	0
T20	0	60467	0	0
T25	7236	256	0	0
T42	0	73376	0	0
T83	0	222	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	62916902	0	0
T1	1688500	128	0	0
T2	281704	128	0	0
T3	924976	87632	0	0
T4	103956	2304	0	0
T5	3341540	146	0	0
T6	9112	424	0	0
T10	6624	128	0	0
T16	1759032	25028	0	0
T17	237340	7010	0	0
T25	4824	128	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10967	0	5244
T4	51978	0	0	2
T5	1670770	0	0	2
T14	263154	0	0	2
T15	216206	0	0	2
T16	879516	831	0	2
T17	118670	0	0	2
T25	2412	0	0	2
T29	0	313	0	0
T44	328346	0	0	2
T82	2458	0	0	2
T83	1424	0	0	2
T149	0	55	0	0
T182	0	349	0	0
T186	0	159	0	0
T189	0	145	0	0
T190	0	435	0	0
T202	0	148	0	0
T203	0	25	0	0
T204	0	110	0	0
T205	0	505	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2532750	2532402	0	0
T2	422556	422178	0	0
T3	1387464	1386486	0	0
T4	155934	148116	0	0
T5	5012310	5011392	0	0
T6	13668	13290	0	0
T10	9936	9588	0	0
T16	2638548	2638212	0	0
T17	356010	355572	0	0
T25	7236	6924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476822540	62917109	0	0
T1	1688500	128	0	0
T2	281704	128	0	0
T3	924976	87632	0	0
T4	103956	2304	0	0
T5	3341540	146	0	0
T6	9112	424	0	0
T10	6624	128	0	0
T16	1759032	25028	0	0
T17	237340	7010	0	0
T25	4824	128	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
TOTAL		52	48	92.31
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	4	4
118	4	4
122	0	4
126	4	4
128	4	4
148	3	3
150	3	3
151	3	3
155	3	3
156	3	3
160	3	3
161	3	3
163	1	1(2 unreachable)
164	3	3
174	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Total	Covered	Percent
Conditions	130	127	97.69
Logical	130	127	97.69
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T5
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T16

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T16

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T16

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T16,T39,T149
1	1	Covered	T1,T2,T16

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T16
1	1	0	Covered	T1,T2,T16
1	1	1	Covered	T1,T2,T16

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T16
1	1	0	Covered	T1,T2,T16
1	1	1	Covered	T1,T2,T16

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T16
1	1	0	Covered	T1,T2,T16
1	1	1	Covered	T1,T2,T16

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T16
1	1	0	Covered	T1,T2,T16
1	1	1	Covered	T1,T2,T16

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T16

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T16
0	1	Covered	T1,T2,T16
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T16

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T16

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T16
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T16

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T16

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T16

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T16
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T16

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T16

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T16

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T16
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T16

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T16

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T16
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T16

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T16
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T16

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T16
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T16

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T39
1	0	Covered	T14,T15,T39

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T16

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T16

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T39
1	0	Covered	T1,T2,T16

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T5,T17
1	0	Covered	T1,T2,T16

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T16

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T16

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T16

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T16

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T16

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T5,T17
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T16
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T16
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	13	86.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	13	86.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	369205635	368536966	0	0
CheckNGreaterZero_A	879	879	0	0
GntImpliesReady_A	369205635	2246338	0	0
GntImpliesValid_A	369205635	2246338	0	0
GrantKnown_A	369205635	368536966	0	0
IdxKnown_A	369205635	368536966	0	0
IndexIsCorrect_A	369205635	2246338	0	0
LockArbDecision_A	369205635	0	0	0
NoReadyValidNoGrant_A	369205635	247185290	0	0
ReadyAndValidImplyGrant_A	369205635	2246338	0	0
ReqAndReadyImplyGrant_A	369205635	2246338	0	0
ReqImpliesValid_A	369205635	116139935	0	0
ReqStaysHighUntilGranted0_M	369205635	0	0	0
RoundRobin_A	369205635	5784	0	874
ValidKnown_A	369205635	368536966	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	2246338	0	0
T1	422125	1607	0	0
T2	70426	72	0	0
T3	231244	0	0	0
T4	25989	30	0	0
T5	835385	11242	0	0
T6	2278	0	0	0
T10	1656	0	0	0
T14	0	14123	0	0
T15	0	12209	0	0
T16	439758	24525	0	0
T17	59335	10376	0	0
T20	0	2040	0	0
T25	1206	0	0	0
T42	0	11164	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	2246338	0	0
T1	422125	1607	0	0
T2	70426	72	0	0
T3	231244	0	0	0
T4	25989	30	0	0
T5	835385	11242	0	0
T6	2278	0	0	0
T10	1656	0	0	0
T14	0	14123	0	0
T15	0	12209	0	0
T16	439758	24525	0	0
T17	59335	10376	0	0
T20	0	2040	0	0
T25	1206	0	0	0
T42	0	11164	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	2246338	0	0
T1	422125	1607	0	0
T2	70426	72	0	0
T3	231244	0	0	0
T4	25989	30	0	0
T5	835385	11242	0	0
T6	2278	0	0	0
T10	1656	0	0	0
T14	0	14123	0	0
T15	0	12209	0	0
T16	439758	24525	0	0
T17	59335	10376	0	0
T20	0	2040	0	0
T25	1206	0	0	0
T42	0	11164	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	247185290	0	0
T1	422125	29657	0	0
T2	70426	68251	0	0
T3	231244	187296	0	0
T4	25989	15356	0	0
T5	835385	2365	0	0
T6	2278	2183	0	0
T10	1656	1566	0	0
T16	439758	372	0	0
T17	59335	369	0	0
T25	1206	1122	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	2246338	0	0
T1	422125	1607	0	0
T2	70426	72	0	0
T3	231244	0	0	0
T4	25989	30	0	0
T5	835385	11242	0	0
T6	2278	0	0	0
T10	1656	0	0	0
T14	0	14123	0	0
T15	0	12209	0	0
T16	439758	24525	0	0
T17	59335	10376	0	0
T20	0	2040	0	0
T25	1206	0	0	0
T42	0	11164	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	2246338	0	0
T1	422125	1607	0	0
T2	70426	72	0	0
T3	231244	0	0	0
T4	25989	30	0	0
T5	835385	11242	0	0
T6	2278	0	0	0
T10	1656	0	0	0
T14	0	14123	0	0
T15	0	12209	0	0
T16	439758	24525	0	0
T17	59335	10376	0	0
T20	0	2040	0	0
T25	1206	0	0	0
T42	0	11164	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	116139935	0	0
T1	422125	392362	0	0
T2	70426	2044	0	0
T3	231244	0	0	0
T4	25989	8718	0	0
T5	835385	832826	0	0
T6	2278	0	0	0
T10	1656	0	0	0
T14	0	130497	0	0
T15	0	107445	0	0
T16	439758	439294	0	0
T17	59335	58857	0	0
T20	0	60467	0	0
T25	1206	0	0	0
T42	0	73376	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	5784	0	874
T4	25989	0	0	1
T5	835385	0	0	1
T14	131577	0	0	1
T15	108103	0	0	1
T16	439758	728	0	1
T17	59335	0	0	1
T25	1206	0	0	1
T29	0	156	0	0
T44	164173	0	0	1
T82	1229	0	0	1
T83	712	0	0	1
T149	0	32	0	0
T182	0	256	0	0
T186	0	97	0	0
T189	0	105	0	0
T202	0	40	0	0
T203	0	25	0	0
T204	0	39	0	0
T205	0	286	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
TOTAL		52	48	92.31
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	4	4
118	4	4
122	0	4
126	4	4
128	4	4
148	3	3
150	3	3
151	3	3
155	3	3
156	3	3
160	3	3
161	3	3
163	1	1(2 unreachable)
164	3	3
174	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Total	Covered	Percent
Conditions	130	127	97.69
Logical	130	127	97.69
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T5,T17
1	0	Covered	T1,T6,T10
1	1	Covered	T1,T6,T10

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T5,T17
1	0	Covered	T1,T6,T10
1	1	Covered	T1,T6,T10

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T5,T17
1	0	Covered	T1,T6,T10
1	1	Covered	T1,T6,T10

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T16,T149,T29
1	1	Covered	T1,T6,T10

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T6,T16
1	1	0	Covered	T1,T6,T10
1	1	1	Covered	T1,T6,T10

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T6,T10
1	1	0	Covered	T1,T6,T10
1	1	1	Covered	T1,T6,T16

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T6,T10
1	1	0	Covered	T1,T6,T16
1	1	1	Covered	T1,T6,T16

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T10
1	0	1	Covered	T1,T6,T10
1	1	0	Covered	T1,T6,T16
1	1	1	Covered	T1,T6,T16

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T10

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T10
0	1	Covered	T1,T6,T10
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T6,T10
1	1	Covered	T1,T6,T10

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T10

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T16
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T6,T10

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T6,T16
1	1	Covered	T1,T6,T10

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T10

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T16
0	1	Covered	T1,T6,T16
1	0	Covered	T1,T6,T10

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T6,T16
1	1	Covered	T1,T6,T16

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T10

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T16
0	1	Covered	T1,T6,T16
1	0	Covered	T1,T6,T10

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T6,T16
1	1	Covered	T1,T6,T16

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T10
0	1	Covered	T1,T6,T16
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T16

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T10
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T10

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T10
0	1	Covered	T1,T6,T16
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T16

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T42
1	0	Covered	T14,T15,T42

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T6,T16

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T16
1	0	Covered	T1,T6,T10

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T42
1	0	Covered	T1,T6,T16

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T5,T17
1	0	Covered	T1,T6,T10

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T6,T16

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T6,T10
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T6,T10
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T6,T10
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T6,T10
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T6,T10
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T6,T10
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T10

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T16
1	0	Covered	T1,T6,T10
1	1	Covered	T1,T6,T10

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T16

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T6,T10
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T10
1	1	Covered	T1,T6,T10

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T5,T17
1	0	Covered	T1,T6,T16
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T10
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T10
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T16
1	0	Covered	T1,T6,T10

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T10

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T10

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T10

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T10

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T10

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T10

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	13	86.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	13	86.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	369205635	368536966	0	0
CheckNGreaterZero_A	879	879	0	0
GntImpliesReady_A	369205635	2243429	0	0
GntImpliesValid_A	369205635	2243429	0	0
GrantKnown_A	369205635	368536966	0	0
IdxKnown_A	369205635	368536966	0	0
IndexIsCorrect_A	369205635	2243429	0	0
LockArbDecision_A	369205635	0	0	0
NoReadyValidNoGrant_A	369205635	255096718	0	0
ReadyAndValidImplyGrant_A	369205635	2243429	0	0
ReqAndReadyImplyGrant_A	369205635	2243429	0	0
ReqImpliesValid_A	369205635	108866199	0	0
ReqStaysHighUntilGranted0_M	369205635	0	0	0
RoundRobin_A	369205635	5183	0	874
ValidKnown_A	369205635	368536966	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	2243429	0	0
T1	422125	835	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	13	0	0
T5	835385	12479	0	0
T6	2278	70	0	0
T10	1656	1	0	0
T14	0	10766	0	0
T15	0	12455	0	0
T16	439758	24776	0	0
T17	59335	10395	0	0
T25	1206	0	0	0
T83	0	1	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	2243429	0	0
T1	422125	835	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	13	0	0
T5	835385	12479	0	0
T6	2278	70	0	0
T10	1656	1	0	0
T14	0	10766	0	0
T15	0	12455	0	0
T16	439758	24776	0	0
T17	59335	10395	0	0
T25	1206	0	0	0
T83	0	1	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	2243429	0	0
T1	422125	835	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	13	0	0
T5	835385	12479	0	0
T6	2278	70	0	0
T10	1656	1	0	0
T14	0	10766	0	0
T15	0	12455	0	0
T16	439758	24776	0	0
T17	59335	10395	0	0
T25	1206	0	0	0
T83	0	1	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	255096718	0	0
T1	422125	13454	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	19134	0	0
T5	835385	2455	0	0
T6	2278	438	0	0
T10	1656	747	0	0
T16	439758	395	0	0
T17	59335	402	0	0
T25	1206	1154	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	2243429	0	0
T1	422125	835	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	13	0	0
T5	835385	12479	0	0
T6	2278	70	0	0
T10	1656	1	0	0
T14	0	10766	0	0
T15	0	12455	0	0
T16	439758	24776	0	0
T17	59335	10395	0	0
T25	1206	0	0	0
T83	0	1	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	2243429	0	0
T1	422125	835	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	13	0	0
T5	835385	12479	0	0
T6	2278	70	0	0
T10	1656	1	0	0
T14	0	10766	0	0
T15	0	12455	0	0
T16	439758	24776	0	0
T17	59335	10395	0	0
T25	1206	0	0	0
T83	0	1	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	108866199	0	0
T1	422125	408609	0	0
T2	70426	0	0	0
T3	231244	0	0	0
T4	25989	5526	0	0
T5	835385	832773	0	0
T6	2278	1773	0	0
T10	1656	847	0	0
T14	0	130490	0	0
T15	0	107450	0	0
T16	439758	439303	0	0
T17	59335	58856	0	0
T25	1206	0	0	0
T83	0	222	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	5183	0	874
T4	25989	0	0	1
T5	835385	0	0	1
T14	131577	0	0	1
T15	108103	0	0	1
T16	439758	103	0	1
T17	59335	0	0	1
T25	1206	0	0	1
T29	0	157	0	0
T44	164173	0	0	1
T82	1229	0	0	1
T83	712	0	0	1
T149	0	23	0	0
T182	0	93	0	0
T186	0	62	0	0
T189	0	40	0	0
T190	0	435	0	0
T202	0	108	0	0
T204	0	71	0	0
T205	0	219	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126	2	2
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	51	45	88.24
Logical	51	45	88.24
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T14,T15
1	1	Covered	T6,T14,T15

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T134
1	0	1	Not Covered
1	1	0	Covered	T6,T14,T15
1	1	1	Covered	T6,T14,T15

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T6,T14,T15
0	1	Covered	T6,T14,T15
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T14,T15
1	1	Covered	T6,T14,T15

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T14,T15

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T14,T15
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T14,T15

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	369205635	368536966	0	0
CheckNGreaterZero_A	879	879	0	0
GntImpliesReady_A	369205635	15036050	0	0
GntImpliesValid_A	369205635	15036050	0	0
GrantKnown_A	369205635	368536966	0	0
IdxKnown_A	369205635	368536966	0	0
IndexIsCorrect_A	369205635	15036050	0	0
LockArbDecision_A	369205565	15036050	0	0
NoReadyValidNoGrant_A	369205635	338464825	0	0
ReadyAndValidImplyGrant_A	369205635	15036050	0	0
ReqAndReadyImplyGrant_A	369205635	15036050	0	0
ReqImpliesValid_A	369205635	30072107	0	0
ReqStaysHighUntilGranted0_M	369162673	15035960	0	0
RoundRobin_A	369205635	0	0	874
ValidKnown_A	369205635	368536966	0	0
gen_data_port_assertion.DataFlow_A	369205635	15036050	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	15036050	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	32	0	0
T4	25989	576	0	0
T5	835385	36	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	1151	0	0
T17	59335	156	0	0
T25	1206	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	15036050	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	32	0	0
T4	25989	576	0	0
T5	835385	36	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	1151	0	0
T17	59335	156	0	0
T25	1206	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	15036050	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	32	0	0
T4	25989	576	0	0
T5	835385	36	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	1151	0	0
T17	59335	156	0	0
T25	1206	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205565	15036050	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	32	0	0
T4	25989	576	0	0
T5	835385	36	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	1151	0	0
T17	59335	156	0	0
T25	1206	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	338464825	0	0
T1	422125	422003	0	0
T2	70426	70299	0	0
T3	231244	231017	0	0
T4	25989	23534	0	0
T5	835385	835160	0	0
T6	2278	2003	0	0
T10	1656	1534	0	0
T16	439758	437400	0	0
T17	59335	58950	0	0
T25	1206	1090	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	15036050	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	32	0	0
T4	25989	576	0	0
T5	835385	36	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	1151	0	0
T17	59335	156	0	0
T25	1206	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	15036050	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	32	0	0
T4	25989	576	0	0
T5	835385	36	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	1151	0	0
T17	59335	156	0	0
T25	1206	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	30072107	0	0
T1	422125	64	0	0
T2	70426	64	0	0
T3	231244	64	0	0
T4	25989	1152	0	0
T5	835385	72	0	0
T6	2278	212	0	0
T10	1656	64	0	0
T16	439758	2302	0	0
T17	59335	312	0	0
T25	1206	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	369162673	15035960	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	32	0	0
T4	25989	576	0	0
T5	835385	36	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	1151	0	0
T17	59335	156	0	0
T25	1206	32	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	0	0	874

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	15036050	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	32	0	0
T4	25989	576	0	0
T5	835385	36	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	1151	0	0
T17	59335	156	0	0
T25	1206	32	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126		unreachable
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	43	42	97.67
Logical	43	42	97.67
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T17,T14
1	1	Covered	T6,T17,T14

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T17,T14,T15
1	1	0	Covered	T1,T2,T3
1	1	1	Unreachable	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T17,T14,T15
1	1	0	Covered	T6,T17,T14
1	1	1	Unreachable	T6,T17,T14

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T17,T14
1	0	Unreachable	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T6,T17,T14
0	1	Covered	T6,T17,T14
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T6,T17,T14
1	1	Covered	T6,T17,T14

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T14,T15
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T17,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T17,T14

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T17,T14
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T17,T14

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	369205635	368536966	0	0
CheckNGreaterZero_A	879	879	0	0
GntImpliesReady_A	369205635	16422488	0	0
GntImpliesValid_A	369205635	16422488	0	0
GrantKnown_A	369205635	368536966	0	0
IdxKnown_A	369205635	368536966	0	0
IndexIsCorrect_A	369205635	16422488	0	0
LockArbDecision_A	369205637	16422491	0	0
NoReadyValidNoGrant_A	369205635	335691979	0	0
ReadyAndValidImplyGrant_A	369205635	16422488	0	0
ReqAndReadyImplyGrant_A	369205635	16422488	0	0
ReqImpliesValid_A	369205635	32844987	0	0
ReqStaysHighUntilGranted0_M	369205637	16422491	0	0
RoundRobin_A	369205635	0	0	874
ValidKnown_A	369205635	368536966	0	0
gen_data_port_assertion.DataFlow_A	369205635	16422488	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	16422488	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	43784	0	0
T4	25989	576	0	0
T5	835385	37	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	11363	0	0
T17	59335	3349	0	0
T25	1206	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	16422488	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	43784	0	0
T4	25989	576	0	0
T5	835385	37	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	11363	0	0
T17	59335	3349	0	0
T25	1206	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	16422488	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	43784	0	0
T4	25989	576	0	0
T5	835385	37	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	11363	0	0
T17	59335	3349	0	0
T25	1206	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205637	16422491	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	43784	0	0
T4	25989	576	0	0
T5	835385	37	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	11363	0	0
T17	59335	3349	0	0
T25	1206	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	335691979	0	0
T1	422125	422003	0	0
T2	70426	70299	0	0
T3	231244	143512	0	0
T4	25989	23534	0	0
T5	835385	835158	0	0
T6	2278	2003	0	0
T10	1656	1534	0	0
T16	439758	416976	0	0
T17	59335	52564	0	0
T25	1206	1090	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	16422488	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	43784	0	0
T4	25989	576	0	0
T5	835385	37	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	11363	0	0
T17	59335	3349	0	0
T25	1206	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	16422488	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	43784	0	0
T4	25989	576	0	0
T5	835385	37	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	11363	0	0
T17	59335	3349	0	0
T25	1206	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	32844987	0	0
T1	422125	64	0	0
T2	70426	64	0	0
T3	231244	87569	0	0
T4	25989	1152	0	0
T5	835385	74	0	0
T6	2278	212	0	0
T10	1656	64	0	0
T16	439758	22726	0	0
T17	59335	6698	0	0
T25	1206	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205637	16422491	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	43784	0	0
T4	25989	576	0	0
T5	835385	37	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	11363	0	0
T17	59335	3349	0	0
T25	1206	32	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	0	0	874

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	16422488	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	43784	0	0
T4	25989	576	0	0
T5	835385	37	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	11363	0	0
T17	59335	3349	0	0
T25	1206	32	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126		unreachable
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	43	42	97.67
Logical	43	42	97.67
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T17,T14
1	1	Covered	T6,T17,T14

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T17,T14,T15
1	1	0	Covered	T1,T2,T3
1	1	1	Unreachable	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T17,T14,T15
1	1	0	Covered	T6,T17,T14
1	1	1	Unreachable	T6,T17,T14

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T17,T14
1	0	Unreachable	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T6,T17,T14
0	1	Covered	T6,T17,T14
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T6,T17,T14
1	1	Covered	T6,T17,T14

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T14,T15
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T17,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T17,T14

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T17,T14
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T17,T14

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	369205635	368536966	0	0
CheckNGreaterZero_A	879	879	0	0
GntImpliesReady_A	369205635	16422488	0	0
GntImpliesValid_A	369205635	16422488	0	0
GrantKnown_A	369205635	368536966	0	0
IdxKnown_A	369205635	368536966	0	0
IndexIsCorrect_A	369205635	16422488	0	0
LockArbDecision_A	369205637	16422491	0	0
NoReadyValidNoGrant_A	369205635	335691979	0	0
ReadyAndValidImplyGrant_A	369205635	16422488	0	0
ReqAndReadyImplyGrant_A	369205635	16422488	0	0
ReqImpliesValid_A	369205635	32844987	0	0
ReqStaysHighUntilGranted0_M	369205637	16422491	0	0
RoundRobin_A	369205635	0	0	874
ValidKnown_A	369205635	368536966	0	0
gen_data_port_assertion.DataFlow_A	369205635	16422488	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	16422488	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	43784	0	0
T4	25989	576	0	0
T5	835385	37	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	11363	0	0
T17	59335	3349	0	0
T25	1206	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	16422488	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	43784	0	0
T4	25989	576	0	0
T5	835385	37	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	11363	0	0
T17	59335	3349	0	0
T25	1206	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	16422488	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	43784	0	0
T4	25989	576	0	0
T5	835385	37	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	11363	0	0
T17	59335	3349	0	0
T25	1206	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205637	16422491	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	43784	0	0
T4	25989	576	0	0
T5	835385	37	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	11363	0	0
T17	59335	3349	0	0
T25	1206	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	335691979	0	0
T1	422125	422003	0	0
T2	70426	70299	0	0
T3	231244	143512	0	0
T4	25989	23534	0	0
T5	835385	835158	0	0
T6	2278	2003	0	0
T10	1656	1534	0	0
T16	439758	416976	0	0
T17	59335	52564	0	0
T25	1206	1090	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	16422488	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	43784	0	0
T4	25989	576	0	0
T5	835385	37	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	11363	0	0
T17	59335	3349	0	0
T25	1206	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	16422488	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	43784	0	0
T4	25989	576	0	0
T5	835385	37	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	11363	0	0
T17	59335	3349	0	0
T25	1206	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	32844987	0	0
T1	422125	64	0	0
T2	70426	64	0	0
T3	231244	87569	0	0
T4	25989	1152	0	0
T5	835385	74	0	0
T6	2278	212	0	0
T10	1656	64	0	0
T16	439758	22726	0	0
T17	59335	6698	0	0
T25	1206	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205637	16422491	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	43784	0	0
T4	25989	576	0	0
T5	835385	37	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	11363	0	0
T17	59335	3349	0	0
T25	1206	32	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	0	0	874

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	16422488	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	43784	0	0
T4	25989	576	0	0
T5	835385	37	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	11363	0	0
T17	59335	3349	0	0
T25	1206	32	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126	2	2
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	51	50	98.04
Logical	51	50	98.04
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T134
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T14,T15
1	1	Covered	T6,T14,T15

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T134
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T134
1	0	1	Covered	T134
1	1	0	Covered	T6,T14,T15
1	1	1	Covered	T6,T14,T15

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T6,T14,T15
0	1	Covered	T6,T14,T15
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T14,T15
1	1	Covered	T6,T14,T15

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T134
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T134
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T14,T15

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T14,T15
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T14,T15

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	369205635	368536966	0	0
CheckNGreaterZero_A	879	879	0	0
GntImpliesReady_A	369205635	15036083	0	0
GntImpliesValid_A	369205635	15036083	0	0
GrantKnown_A	369205635	368536966	0	0
IdxKnown_A	369205635	368536966	0	0
IndexIsCorrect_A	369205635	15036083	0	0
LockArbDecision_A	369205565	15036050	0	0
NoReadyValidNoGrant_A	369205635	338464791	0	0
ReadyAndValidImplyGrant_A	369205635	15036083	0	0
ReqAndReadyImplyGrant_A	369205635	15036083	0	0
ReqImpliesValid_A	369205635	30072174	0	0
ReqStaysHighUntilGranted0_M	369162673	15035960	0	0
RoundRobin_A	369205635	0	0	874
ValidKnown_A	369205635	368536966	0	0
gen_data_port_assertion.DataFlow_A	369205635	15036083	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	15036083	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	32	0	0
T4	25989	576	0	0
T5	835385	36	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	1151	0	0
T17	59335	156	0	0
T25	1206	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	15036083	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	32	0	0
T4	25989	576	0	0
T5	835385	36	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	1151	0	0
T17	59335	156	0	0
T25	1206	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	15036083	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	32	0	0
T4	25989	576	0	0
T5	835385	36	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	1151	0	0
T17	59335	156	0	0
T25	1206	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205565	15036050	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	32	0	0
T4	25989	576	0	0
T5	835385	36	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	1151	0	0
T17	59335	156	0	0
T25	1206	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	338464791	0	0
T1	422125	422003	0	0
T2	70426	70299	0	0
T3	231244	231017	0	0
T4	25989	23534	0	0
T5	835385	835160	0	0
T6	2278	2003	0	0
T10	1656	1534	0	0
T16	439758	437400	0	0
T17	59335	58950	0	0
T25	1206	1090	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	15036083	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	32	0	0
T4	25989	576	0	0
T5	835385	36	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	1151	0	0
T17	59335	156	0	0
T25	1206	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	15036083	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	32	0	0
T4	25989	576	0	0
T5	835385	36	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	1151	0	0
T17	59335	156	0	0
T25	1206	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	30072174	0	0
T1	422125	64	0	0
T2	70426	64	0	0
T3	231244	64	0	0
T4	25989	1152	0	0
T5	835385	72	0	0
T6	2278	212	0	0
T10	1656	64	0	0
T16	439758	2302	0	0
T17	59335	312	0	0
T25	1206	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	369162673	15035960	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	32	0	0
T4	25989	576	0	0
T5	835385	36	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	1151	0	0
T17	59335	156	0	0
T25	1206	32	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	0	0	874

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	15036083	0	0
T1	422125	32	0	0
T2	70426	32	0	0
T3	231244	32	0	0
T4	25989	576	0	0
T5	835385	36	0	0
T6	2278	106	0	0
T10	1656	32	0	0
T16	439758	1151	0	0
T17	59335	156	0	0
T25	1206	32	0	0