Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_to_prog_fifo.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	100.00	75.00			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.89	100.00	65.22			85.71	84.62	u_to_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	90.30	100.00	80.00			90.91

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	371727562	31670701	0	0
DepthKnown_A	371727562	370974313	0	0
RvalidKnown_A	371727562	370974313	0	0
WreadyKnown_A	371727562	370974313	0	0
gen_passthru_fifo.paramCheckPass	1094	1094	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	31670701	0	0
T1	422125	60280	0	0
T2	70426	34228	0	0
T3	231244	162	0	0
T4	25989	5538	0	0
T5	835385	20669	0	0
T6	2278	539	0	0
T10	1656	318	0	0
T16	439758	225108	0	0
T17	59335	32258	0	0
T25	1206	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1094	1094	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	371727562	40467228	0	0
DepthKnown_A	371727562	370974313	0	0
RvalidKnown_A	371727562	370974313	0	0
WreadyKnown_A	371727562	370974313	0	0
gen_passthru_fifo.paramCheckPass	1094	1094	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	40467228	0	0
T1	422125	60280	0	0
T2	70426	34228	0	0
T3	231244	162	0	0
T4	25989	4868	0	0
T5	835385	20669	0	0
T6	2278	539	0	0
T10	1656	266	0	0
T16	439758	213481	0	0
T17	59335	25243	0	0
T25	1206	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1094	1094	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	371727562	2069809	0	0
DepthKnown_A	371727562	370974313	0	0
RvalidKnown_A	371727562	370974313	0	0
WreadyKnown_A	371727562	370974313	0	0
gen_passthru_fifo.paramCheckPass	1094	1094	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	2069809	0	0
T1	422125	10021	0	0
T2	70426	46	0	0
T3	231244	0	0	0
T4	25989	720	0	0
T5	835385	0	0	0
T6	2278	0	0	0
T10	1656	56	0	0
T11	0	87	0	0
T12	0	1067	0	0
T16	439758	15146	0	0
T17	59335	0	0	0
T20	0	2560	0	0
T25	1206	0	0	0
T44	0	17550	0	0
T83	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1094	1094	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	371727562	3187700	0	0
DepthKnown_A	371727562	370974313	0	0
RvalidKnown_A	371727562	370974313	0	0
WreadyKnown_A	371727562	370974313	0	0
gen_passthru_fifo.paramCheckPass	1094	1094	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	3187700	0	0
T1	422125	10021	0	0
T2	70426	46	0	0
T3	231244	0	0	0
T4	25989	151	0	0
T5	835385	0	0	0
T6	2278	0	0	0
T10	1656	10	0	0
T11	0	35	0	0
T12	0	1067	0	0
T16	439758	15146	0	0
T17	59335	0	0	0
T20	0	2560	0	0
T25	1206	0	0	0
T44	0	5632	0	0
T83	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1094	1094	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	371727562	3884512	0	0
DepthKnown_A	371727562	370974313	0	0
RvalidKnown_A	371727562	370974313	0	0
WreadyKnown_A	371727562	370974313	0	0
gen_passthru_fifo.paramCheckPass	1094	1094	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	3884512	0	0
T1	422125	9708	0	0
T2	70426	87	0	0
T3	231244	0	0	0
T4	25989	262	0	0
T5	835385	13120	0	0
T6	2278	146	0	0
T10	1656	15	0	0
T14	0	16880	0	0
T16	439758	25263	0	0
T17	59335	15491	0	0
T25	1206	0	0	0
T44	0	5632	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1094	1094	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	371727562	4871325	0	0
DepthKnown_A	371727562	370974313	0	0
RvalidKnown_A	371727562	370974313	0	0
WreadyKnown_A	371727562	370974313	0	0
gen_passthru_fifo.paramCheckPass	1094	1094	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	4871325	0	0
T1	422125	9708	0	0
T2	70426	87	0	0
T3	231244	0	0	0
T4	25989	161	0	0
T5	835385	13120	0	0
T6	2278	146	0	0
T10	1656	9	0	0
T14	0	16880	0	0
T16	439758	13636	0	0
T17	59335	8476	0	0
T25	1206	0	0	0
T44	0	5632	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1094	1094	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	371727562	25692476	0	0
DepthKnown_A	371727562	370974313	0	0
RvalidKnown_A	371727562	370974313	0	0
WreadyKnown_A	371727562	370974313	0	0
gen_passthru_fifo.paramCheckPass	1094	1094	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	25692476	0	0
T1	422125	40551	0	0
T2	70426	34095	0	0
T3	231244	162	0	0
T4	25989	4556	0	0
T5	835385	7549	0	0
T6	2278	393	0	0
T10	1656	247	0	0
T16	439758	184699	0	0
T17	59335	16767	0	0
T25	1206	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1094	1094	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	371727562	32408203	0	0
DepthKnown_A	371727562	370974313	0	0
RvalidKnown_A	371727562	370974313	0	0
WreadyKnown_A	371727562	370974313	0	0
gen_passthru_fifo.paramCheckPass	1094	1094	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	32408203	0	0
T1	422125	40551	0	0
T2	70426	34095	0	0
T3	231244	162	0	0
T4	25989	4556	0	0
T5	835385	7549	0	0
T6	2278	393	0	0
T10	1656	247	0	0
T16	439758	184699	0	0
T17	59335	16767	0	0
T25	1206	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727562	370974313	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1094	1094	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T16,T26
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T10

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T10

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	369205635	3178247	0	0
DepthKnown_A	369205635	368536966	0	0
RvalidKnown_A	369205635	368536966	0	0
WreadyKnown_A	369205635	368536966	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	369205635	3178247	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	3178247	0	0
T1	422125	10021	0	0
T2	70426	46	0	0
T3	231244	0	0	0
T4	25989	151	0	0
T5	835385	0	0	0
T6	2278	0	0	0
T10	1656	10	0	0
T11	0	35	0	0
T12	0	1067	0	0
T16	439758	15146	0	0
T17	59335	0	0	0
T20	0	2560	0	0
T25	1206	0	0	0
T44	0	5632	0	0
T83	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	368536966	0	0
T1	422125	422067	0	0
T2	70426	70363	0	0
T3	231244	231081	0	0
T4	25989	24686	0	0
T5	835385	835232	0	0
T6	2278	2215	0	0
T10	1656	1598	0	0
T16	439758	439702	0	0
T17	59335	59262	0	0
T25	1206	1154	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	369205635	3178247	0	0
T1	422125	10021	0	0
T2	70426	46	0	0
T3	231244	0	0	0
T4	25989	151	0	0
T5	835385	0	0	0
T6	2278	0	0	0
T10	1656	10	0	0
T11	0	35	0	0
T12	0	1067	0	0
T16	439758	15146	0	0
T17	59335	0	0	0
T20	0	2560	0	0
T25	1206	0	0	0
T44	0	5632	0	0
T83	0	4	0	0