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Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 100.00 68.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.41 100.00 82.05 90.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.25 100.00 88.99 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 95.33 100.00 91.30 90.00 100.00


Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.62 100.00 62.50 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.87 100.00 74.36 90.00 90.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.25 100.00 88.99 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 84.82 100.00 82.61 90.00 66.67


Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 100.00 68.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 80.56 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.25 100.00 88.99 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 93.64 100.00 90.00 90.91

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Module Instances:
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo
TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT14,T15,T42
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T6,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T6,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T6,T10
110Not Covered
111CoveredT1,T6,T10

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T6,T10
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T6,T10


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T6,T10
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 369205635 48041222 0 0
DepthKnown_A 369205635 368536966 0 0
RvalidKnown_A 369205635 368536966 0 0
WreadyKnown_A 369205635 368536966 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 369205635 48041222 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 48041222 0 0
T1 422125 2503 0 0
T2 70426 0 0 0
T3 231244 0 0 0
T4 25989 105 0 0
T5 835385 639539 0 0
T6 2278 368 0 0
T10 1656 14 0 0
T14 0 42328 0 0
T15 0 48740 0 0
T16 439758 55718 0 0
T17 59335 22876 0 0
T25 1206 0 0 0
T83 0 23 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 368536966 0 0
T1 422125 422067 0 0
T2 70426 70363 0 0
T3 231244 231081 0 0
T4 25989 24686 0 0
T5 835385 835232 0 0
T6 2278 2215 0 0
T10 1656 1598 0 0
T16 439758 439702 0 0
T17 59335 59262 0 0
T25 1206 1154 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 368536966 0 0
T1 422125 422067 0 0
T2 70426 70363 0 0
T3 231244 231081 0 0
T4 25989 24686 0 0
T5 835385 835232 0 0
T6 2278 2215 0 0
T10 1656 1598 0 0
T16 439758 439702 0 0
T17 59335 59262 0 0
T25 1206 1154 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 368536966 0 0
T1 422125 422067 0 0
T2 70426 70363 0 0
T3 231244 231081 0 0
T4 25989 24686 0 0
T5 835385 835232 0 0
T6 2278 2215 0 0
T10 1656 1598 0 0
T16 439758 439702 0 0
T17 59335 59262 0 0
T25 1206 1154 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 48041222 0 0
T1 422125 2503 0 0
T2 70426 0 0 0
T3 231244 0 0 0
T4 25989 105 0 0
T5 835385 639539 0 0
T6 2278 368 0 0
T10 1656 14 0 0
T14 0 42328 0 0
T15 0 48740 0 0
T16 439758 55718 0 0
T17 59335 22876 0 0
T25 1206 0 0 0
T83 0 23 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
TotalCoveredPercent
Conditions161062.50
Logical161062.50
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T6,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T6,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT6,T17,T14
110Not Covered
111CoveredT1,T6,T10

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T6,T10
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T6,T10


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T6,T10
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 369205635 12172141 0 0
DepthKnown_A 369205635 368536966 0 0
RvalidKnown_A 369205635 368536966 0 0
WreadyKnown_A 369205635 368536966 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 369205635 12172141 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 12172141 0 0
T1 422125 839 0 0
T2 70426 0 0 0
T3 231244 0 0 0
T4 25989 39 0 0
T5 835385 12483 0 0
T6 2278 148 0 0
T10 1656 5 0 0
T14 0 24419 0 0
T15 0 27446 0 0
T16 439758 24642 0 0
T17 59335 10486 0 0
T25 1206 0 0 0
T83 0 10 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 368536966 0 0
T1 422125 422067 0 0
T2 70426 70363 0 0
T3 231244 231081 0 0
T4 25989 24686 0 0
T5 835385 835232 0 0
T6 2278 2215 0 0
T10 1656 1598 0 0
T16 439758 439702 0 0
T17 59335 59262 0 0
T25 1206 1154 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 368536966 0 0
T1 422125 422067 0 0
T2 70426 70363 0 0
T3 231244 231081 0 0
T4 25989 24686 0 0
T5 835385 835232 0 0
T6 2278 2215 0 0
T10 1656 1598 0 0
T16 439758 439702 0 0
T17 59335 59262 0 0
T25 1206 1154 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 368536966 0 0
T1 422125 422067 0 0
T2 70426 70363 0 0
T3 231244 231081 0 0
T4 25989 24686 0 0
T5 835385 835232 0 0
T6 2278 2215 0 0
T10 1656 1598 0 0
T16 439758 439702 0 0
T17 59335 59262 0 0
T25 1206 1154 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 12172141 0 0
T1 422125 839 0 0
T2 70426 0 0 0
T3 231244 0 0 0
T4 25989 39 0 0
T5 835385 12483 0 0
T6 2278 148 0 0
T10 1656 5 0 0
T14 0 24419 0 0
T15 0 27446 0 0
T16 439758 24642 0 0
T17 59335 10486 0 0
T25 1206 0 0 0
T83 0 10 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT6,T17,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT6,T17,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T10,T16
101CoveredT6,T14,T15
110Not Covered
111CoveredT6,T17,T14

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT6,T17,T14
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T6,T17,T14


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T6,T17,T14
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 369205635 10790863 0 0
DepthKnown_A 369205635 368536966 0 0
RvalidKnown_A 369205635 368536966 0 0
WreadyKnown_A 369205635 368536966 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 369205635 10790863 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 10790863 0 0
T4 25989 0 0 0
T5 835385 0 0 0
T6 2278 148 0 0
T10 1656 0 0 0
T14 131577 21540 0 0
T15 0 24918 0 0
T16 439758 0 0 0
T17 59335 2340 0 0
T20 0 262144 0 0
T25 1206 0 0 0
T27 0 262144 0 0
T42 0 8076 0 0
T44 164173 0 0 0
T82 1229 0 0 0
T83 0 10 0 0
T84 0 10293 0 0
T100 0 688 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 368536966 0 0
T1 422125 422067 0 0
T2 70426 70363 0 0
T3 231244 231081 0 0
T4 25989 24686 0 0
T5 835385 835232 0 0
T6 2278 2215 0 0
T10 1656 1598 0 0
T16 439758 439702 0 0
T17 59335 59262 0 0
T25 1206 1154 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 368536966 0 0
T1 422125 422067 0 0
T2 70426 70363 0 0
T3 231244 231081 0 0
T4 25989 24686 0 0
T5 835385 835232 0 0
T6 2278 2215 0 0
T10 1656 1598 0 0
T16 439758 439702 0 0
T17 59335 59262 0 0
T25 1206 1154 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 368536966 0 0
T1 422125 422067 0 0
T2 70426 70363 0 0
T3 231244 231081 0 0
T4 25989 24686 0 0
T5 835385 835232 0 0
T6 2278 2215 0 0
T10 1656 1598 0 0
T16 439758 439702 0 0
T17 59335 59262 0 0
T25 1206 1154 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 10790863 0 0
T4 25989 0 0 0
T5 835385 0 0 0
T6 2278 148 0 0
T10 1656 0 0 0
T14 131577 21540 0 0
T15 0 24918 0 0
T16 439758 0 0 0
T17 59335 2340 0 0
T20 0 262144 0 0
T25 1206 0 0 0
T27 0 262144 0 0
T42 0 8076 0 0
T44 164173 0 0 0
T82 1229 0 0 0
T83 0 10 0 0
T84 0 10293 0 0
T100 0 688 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%