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Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.00 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.00 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_csr20_field0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field1.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.00 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.00 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_csr20_field1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field2.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
60.48 71.43 50.00 60.00 u_csr20_field2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

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Module Instances:
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field0.wr_en_data_arb
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field1.wr_en_data_arb
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field2.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
110 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field0.wr_en_data_arb
TotalCoveredPercent
Conditions10660.00
Logical10660.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT62,T63,T68

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT62,T63,T68
Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field1.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
110 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field1.wr_en_data_arb
TotalCoveredPercent
Conditions10660.00
Logical10660.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT62,T63,T68

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT62,T63,T68
Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field2.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN43100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 0 1
51 unreachable
52 unreachable
53 unreachable

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