Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.05	97.12	88.00	98.44		100.00	41.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	87	87	100.00	87	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	87	87	100.00	87	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	371727590	4473	0	0
addr_rd_A	371727590	1821	0	0
bank0_info0_page_cfg_0_rd_A	371727590	2328	0	0
bank0_info0_page_cfg_1_rd_A	371727590	2219	0	0
bank0_info0_page_cfg_2_rd_A	371727590	2702	0	0
bank0_info0_page_cfg_3_rd_A	371727590	2789	0	0
bank0_info0_page_cfg_4_rd_A	371727590	2008	0	0
bank0_info0_page_cfg_5_rd_A	371727590	2269	0	0
bank0_info0_page_cfg_6_rd_A	371727590	2780	0	0
bank0_info0_page_cfg_7_rd_A	371727590	2383	0	0
bank0_info0_page_cfg_8_rd_A	371727590	2291	0	0
bank0_info0_page_cfg_9_rd_A	371727590	2816	0	0
bank0_info0_regwen_0_rd_A	371727590	856	0	0
bank0_info0_regwen_1_rd_A	371727590	2351	0	0
bank0_info0_regwen_2_rd_A	371727590	1384	0	0
bank0_info0_regwen_3_rd_A	371727590	1964	0	0
bank0_info0_regwen_4_rd_A	371727590	2298	0	0
bank0_info0_regwen_5_rd_A	371727590	2350	0	0
bank0_info0_regwen_6_rd_A	371727590	2312	0	0
bank0_info0_regwen_7_rd_A	371727590	1789	0	0
bank0_info0_regwen_8_rd_A	371727590	2360	0	0
bank0_info0_regwen_9_rd_A	371727590	1333	0	0
bank0_info1_page_cfg_rd_A	371727590	1810	0	0
bank0_info1_regwen_rd_A	371727590	1752	0	0
bank0_info2_page_cfg_0_rd_A	371727590	2275	0	0
bank0_info2_page_cfg_1_rd_A	371727590	2235	0	0
bank0_info2_regwen_0_rd_A	371727590	2368	0	0
bank0_info2_regwen_1_rd_A	371727590	1723	0	0
bank1_info0_page_cfg_0_rd_A	371727590	2652	0	0
bank1_info0_page_cfg_1_rd_A	371727590	2695	0	0
bank1_info0_page_cfg_2_rd_A	371727590	2797	0	0
bank1_info0_page_cfg_3_rd_A	371727590	2840	0	0
bank1_info0_page_cfg_4_rd_A	371727590	2298	0	0
bank1_info0_page_cfg_5_rd_A	371727590	2844	0	0
bank1_info0_page_cfg_6_rd_A	371727590	2092	0	0
bank1_info0_page_cfg_7_rd_A	371727590	2597	0	0
bank1_info0_page_cfg_8_rd_A	371727590	2799	0	0
bank1_info0_page_cfg_9_rd_A	371727590	2536	0	0
bank1_info0_regwen_0_rd_A	371727590	1824	0	0
bank1_info0_regwen_1_rd_A	371727590	1815	0	0
bank1_info0_regwen_2_rd_A	371727590	2377	0	0
bank1_info0_regwen_3_rd_A	371727590	1935	0	0
bank1_info0_regwen_4_rd_A	371727590	1679	0	0
bank1_info0_regwen_5_rd_A	371727590	1231	0	0
bank1_info0_regwen_6_rd_A	371727590	1752	0	0
bank1_info0_regwen_7_rd_A	371727590	1846	0	0
bank1_info0_regwen_8_rd_A	371727590	1903	0	0
bank1_info0_regwen_9_rd_A	371727590	1467	0	0
bank1_info1_page_cfg_rd_A	371727590	1788	0	0
bank1_info1_regwen_rd_A	371727590	2262	0	0
bank1_info2_page_cfg_0_rd_A	371727590	2271	0	0
bank1_info2_page_cfg_1_rd_A	371727590	2731	0	0
bank1_info2_regwen_0_rd_A	371727590	1377	0	0
bank1_info2_regwen_1_rd_A	371727590	1426	0	0
bank_cfg_regwen_rd_A	371727590	1317	0	0
default_region_rd_A	371727590	2762	0	0
exec_rd_A	371727590	2084	0	0
fifo_lvl_rd_A	371727590	2348	0	0
fifo_rst_rd_A	371727590	2223	0	0
hw_info_cfg_override_rd_A	371727590	2344	0	0
intr_enable_rd_A	371727590	2683	0	0
mp_region_0_rd_A	371727590	2423	0	0
mp_region_1_rd_A	371727590	2294	0	0
mp_region_2_rd_A	371727590	2430	0	0
mp_region_3_rd_A	371727590	1386	0	0
mp_region_4_rd_A	371727590	2478	0	0
mp_region_5_rd_A	371727590	1731	0	0
mp_region_6_rd_A	371727590	2452	0	0
mp_region_7_rd_A	371727590	1420	0	0
mp_region_cfg_0_rd_A	371727590	2677	0	0
mp_region_cfg_1_rd_A	371727590	2156	0	0
mp_region_cfg_2_rd_A	371727590	2266	0	0
mp_region_cfg_3_rd_A	371727590	2131	0	0
mp_region_cfg_4_rd_A	371727590	2671	0	0
mp_region_cfg_5_rd_A	371727590	2746	0	0
mp_region_cfg_6_rd_A	371727590	2698	0	0
mp_region_cfg_7_rd_A	371727590	1871	0	0
phy_alert_cfg_rd_A	371727590	1237	0	0
region_cfg_regwen_0_rd_A	371727590	1740	0	0
region_cfg_regwen_1_rd_A	371727590	1864	0	0
region_cfg_regwen_2_rd_A	371727590	1781	0	0
region_cfg_regwen_3_rd_A	371727590	2189	0	0
region_cfg_regwen_4_rd_A	371727590	1886	0	0
region_cfg_regwen_5_rd_A	371727590	1231	0	0
region_cfg_regwen_6_rd_A	371727590	1961	0	0
region_cfg_regwen_7_rd_A	371727590	1718	0	0
scratch_rd_A	371727590	1712	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	4473	0	0
T63	37173	3	0	0
T64	4718	380	0	0
T65	4721	2	0	0
T66	4289	28	0	0
T67	5346	218	0	0
T208	9446	8	0	0
T209	4298	114	0	0
T210	2935	27	0	0
T211	7972	8	0	0
T212	5516	150	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1821	0	0
T200	4753	13	0	0
T208	9446	14	0	0
T213	5018	4	0	0
T221	21147	43	0	0
T224	19310	58	0	0
T225	4062	5	0	0
T231	74624	43	0	0
T289	155061	209	0	0
T290	20569	52	0	0
T291	10478	18	0	0

bank0_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2328	0	0
T62	3612	33	0	0
T200	4753	10	0	0
T208	9446	14	0	0
T213	5018	32	0	0
T221	21147	39	0	0
T224	19310	58	0	0
T225	4062	2	0	0
T231	74624	159	0	0
T289	155061	214	0	0
T290	20569	56	0	0

bank0_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2219	0	0
T62	3612	26	0	0
T200	4753	5	0	0
T208	9446	80	0	0
T213	5018	24	0	0
T221	21147	38	0	0
T224	19310	47	0	0
T225	4062	23	0	0
T231	74624	152	0	0
T289	155061	228	0	0
T290	20569	83	0	0

bank0_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2702	0	0
T62	3612	27	0	0
T200	4753	11	0	0
T208	9446	32	0	0
T213	5018	27	0	0
T221	21147	46	0	0
T224	19310	43	0	0
T225	4062	24	0	0
T231	74624	150	0	0
T289	155061	230	0	0
T290	20569	39	0	0

bank0_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2789	0	0
T62	3612	23	0	0
T200	4753	8	0	0
T208	9446	45	0	0
T221	21147	37	0	0
T224	19310	35	0	0
T225	4062	5	0	0
T231	74624	190	0	0
T289	155061	243	0	0
T290	20569	20	0	0
T291	10478	14	0	0

bank0_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2008	0	0
T62	3612	4	0	0
T200	4753	9	0	0
T208	9446	10	0	0
T213	5018	27	0	0
T221	21147	18	0	0
T224	19310	12	0	0
T225	4062	23	0	0
T231	74624	126	0	0
T289	155061	204	0	0
T290	20569	40	0	0

bank0_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2269	0	0
T62	3612	26	0	0
T200	4753	12	0	0
T208	9446	63	0	0
T213	5018	13	0	0
T221	21147	32	0	0
T224	19310	31	0	0
T225	4062	10	0	0
T231	74624	229	0	0
T289	155061	226	0	0
T290	20569	63	0	0

bank0_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2780	0	0
T62	3612	13	0	0
T200	4753	9	0	0
T208	9446	45	0	0
T213	5018	6	0	0
T221	21147	70	0	0
T224	19310	40	0	0
T225	4062	27	0	0
T231	74624	264	0	0
T289	155061	243	0	0
T290	20569	55	0	0

bank0_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2383	0	0
T62	3612	28	0	0
T200	4753	9	0	0
T208	9446	51	0	0
T213	5018	24	0	0
T221	21147	31	0	0
T224	19310	46	0	0
T225	4062	4	0	0
T231	74624	200	0	0
T289	155061	262	0	0
T290	20569	26	0	0

bank0_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2291	0	0
T62	3612	48	0	0
T200	4753	10	0	0
T208	9446	29	0	0
T213	5018	8	0	0
T221	21147	31	0	0
T224	19310	28	0	0
T225	4062	28	0	0
T231	74624	216	0	0
T289	155061	229	0	0
T290	20569	67	0	0

bank0_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2816	0	0
T62	3612	2	0	0
T200	4753	9	0	0
T208	9446	46	0	0
T213	5018	1	0	0
T221	21147	61	0	0
T224	19310	38	0	0
T225	4062	2	0	0
T231	74624	147	0	0
T289	155061	248	0	0
T290	20569	45	0	0

bank0_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	856	0	0
T62	3612	6	0	0
T200	4753	8	0	0
T208	9446	31	0	0
T221	21147	51	0	0
T224	19310	16	0	0
T231	74624	58	0	0
T289	155061	231	0	0
T290	20569	39	0	0
T291	10478	9	0	0
T292	10251	2	0	0

bank0_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2351	0	0
T62	3612	6	0	0
T200	4753	9	0	0
T208	9446	15	0	0
T221	21147	26	0	0
T224	19310	42	0	0
T225	4062	5	0	0
T231	74624	59	0	0
T289	155061	274	0	0
T290	20569	34	0	0
T291	10478	21	0	0

bank0_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1384	0	0
T62	3612	2	0	0
T200	4753	12	0	0
T208	9446	24	0	0
T213	5018	6	0	0
T221	21147	48	0	0
T224	19310	36	0	0
T225	4062	9	0	0
T231	74624	50	0	0
T289	155061	256	0	0
T290	20569	21	0	0

bank0_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1964	0	0
T62	3612	8	0	0
T200	4753	8	0	0
T208	9446	20	0	0
T213	5018	8	0	0
T221	21147	58	0	0
T224	19310	48	0	0
T225	4062	6	0	0
T231	74624	44	0	0
T289	155061	246	0	0
T290	20569	51	0	0

bank0_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2298	0	0
T62	3612	8	0	0
T200	4753	12	0	0
T208	9446	16	0	0
T213	5018	6	0	0
T221	21147	61	0	0
T224	19310	41	0	0
T225	4062	8	0	0
T231	74624	48	0	0
T289	155061	219	0	0
T290	20569	16	0	0

bank0_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2350	0	0
T62	3612	5	0	0
T200	4753	3	0	0
T208	9446	24	0	0
T213	5018	2	0	0
T221	21147	57	0	0
T224	19310	46	0	0
T225	4062	4	0	0
T231	74624	26	0	0
T289	155061	211	0	0
T290	20569	23	0	0

bank0_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2312	0	0
T62	3612	2	0	0
T200	4753	9	0	0
T208	9446	27	0	0
T213	5018	1	0	0
T221	21147	49	0	0
T224	19310	40	0	0
T225	4062	9	0	0
T231	74624	57	0	0
T289	155061	245	0	0
T290	20569	38	0	0

bank0_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1789	0	0
T62	3612	8	0	0
T200	4753	1	0	0
T208	9446	13	0	0
T213	5018	11	0	0
T221	21147	46	0	0
T224	19310	61	0	0
T225	4062	9	0	0
T231	74624	42	0	0
T289	155061	224	0	0
T290	20569	43	0	0

bank0_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2360	0	0
T62	3612	6	0	0
T200	4753	10	0	0
T208	9446	13	0	0
T221	21147	12	0	0
T224	19310	49	0	0
T225	4062	7	0	0
T231	74624	59	0	0
T289	155061	229	0	0
T290	20569	49	0	0
T291	10478	23	0	0

bank0_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1333	0	0
T200	4753	8	0	0
T208	9446	23	0	0
T221	21147	69	0	0
T224	19310	28	0	0
T225	4062	7	0	0
T231	74624	24	0	0
T289	155061	233	0	0
T290	20569	55	0	0
T291	10478	15	0	0
T292	10251	28	0	0

bank0_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1810	0	0
T62	3612	27	0	0
T200	4753	4	0	0
T208	9446	60	0	0
T213	5018	8	0	0
T221	21147	10	0	0
T224	19310	29	0	0
T225	4062	4	0	0
T231	74624	179	0	0
T289	155061	234	0	0
T290	20569	51	0	0

bank0_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1752	0	0
T200	4753	7	0	0
T208	9446	17	0	0
T221	21147	73	0	0
T224	19310	41	0	0
T225	4062	7	0	0
T231	74624	52	0	0
T289	155061	225	0	0
T290	20569	20	0	0
T291	10478	15	0	0
T292	10251	16	0	0

bank0_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2275	0	0
T62	3612	5	0	0
T200	4753	4	0	0
T208	9446	35	0	0
T213	5018	8	0	0
T221	21147	48	0	0
T224	19310	90	0	0
T225	4062	25	0	0
T231	74624	209	0	0
T289	155061	195	0	0
T290	20569	48	0	0

bank0_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2235	0	0
T62	3612	2	0	0
T200	4753	6	0	0
T208	9446	80	0	0
T213	5018	12	0	0
T221	21147	29	0	0
T224	19310	56	0	0
T225	4062	1	0	0
T231	74624	156	0	0
T289	155061	167	0	0
T290	20569	52	0	0

bank0_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2368	0	0
T62	3612	9	0	0
T200	4753	3	0	0
T208	9446	20	0	0
T213	5018	7	0	0
T221	21147	30	0	0
T224	19310	87	0	0
T225	4062	9	0	0
T231	74624	69	0	0
T289	155061	221	0	0
T290	20569	56	0	0

bank0_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1723	0	0
T62	3612	3	0	0
T200	4753	10	0	0
T208	9446	7	0	0
T221	21147	45	0	0
T224	19310	32	0	0
T225	4062	3	0	0
T231	74624	37	0	0
T289	155061	252	0	0
T290	20569	27	0	0
T291	10478	17	0	0

bank1_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2652	0	0
T62	3612	25	0	0
T200	4753	8	0	0
T208	9446	15	0	0
T213	5018	7	0	0
T221	21147	40	0	0
T224	19310	54	0	0
T225	4062	34	0	0
T231	74624	156	0	0
T289	155061	205	0	0
T290	20569	20	0	0

bank1_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2695	0	0
T62	3612	4	0	0
T200	4753	12	0	0
T208	9446	32	0	0
T213	5018	32	0	0
T221	21147	27	0	0
T224	19310	51	0	0
T231	74624	164	0	0
T289	155061	198	0	0
T290	20569	13	0	0
T291	10478	50	0	0

bank1_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2797	0	0
T62	3612	33	0	0
T200	4753	4	0	0
T208	9446	48	0	0
T213	5018	1	0	0
T221	21147	58	0	0
T224	19310	55	0	0
T225	4062	34	0	0
T231	74624	174	0	0
T289	155061	227	0	0
T290	20569	61	0	0

bank1_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2840	0	0
T62	3612	4	0	0
T200	4753	3	0	0
T208	9446	23	0	0
T213	5018	15	0	0
T221	21147	55	0	0
T224	19310	12	0	0
T225	4062	6	0	0
T231	74624	231	0	0
T289	155061	218	0	0
T290	20569	42	0	0

bank1_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2298	0	0
T62	3612	23	0	0
T200	4753	3	0	0
T208	9446	75	0	0
T221	21147	31	0	0
T224	19310	35	0	0
T225	4062	45	0	0
T231	74624	178	0	0
T289	155061	176	0	0
T290	20569	22	0	0
T291	10478	11	0	0

bank1_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2844	0	0
T62	3612	30	0	0
T200	4753	18	0	0
T208	9446	61	0	0
T213	5018	18	0	0
T221	21147	17	0	0
T224	19310	61	0	0
T225	4062	33	0	0
T231	74624	116	0	0
T289	155061	228	0	0
T290	20569	45	0	0

bank1_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2092	0	0
T62	3612	34	0	0
T200	4753	12	0	0
T208	9446	36	0	0
T213	5018	9	0	0
T221	21147	13	0	0
T224	19310	40	0	0
T225	4062	3	0	0
T231	74624	173	0	0
T289	155061	214	0	0
T290	20569	42	0	0

bank1_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2597	0	0
T62	3612	10	0	0
T200	4753	7	0	0
T208	9446	30	0	0
T213	5018	6	0	0
T221	21147	29	0	0
T224	19310	18	0	0
T225	4062	33	0	0
T231	74624	175	0	0
T289	155061	204	0	0
T290	20569	17	0	0

bank1_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2799	0	0
T62	3612	14	0	0
T200	4753	7	0	0
T208	9446	18	0	0
T213	5018	16	0	0
T221	21147	7	0	0
T224	19310	84	0	0
T225	4062	16	0	0
T231	74624	240	0	0
T289	155061	233	0	0
T290	20569	62	0	0

bank1_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2536	0	0
T200	4753	10	0	0
T208	9446	10	0	0
T213	5018	19	0	0
T221	21147	46	0	0
T224	19310	59	0	0
T231	74624	138	0	0
T289	155061	241	0	0
T290	20569	14	0	0
T291	10478	19	0	0
T292	10251	10	0	0

bank1_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1824	0	0
T62	3612	1	0	0
T200	4753	8	0	0
T208	9446	16	0	0
T213	5018	10	0	0
T221	21147	14	0	0
T224	19310	77	0	0
T225	4062	5	0	0
T231	74624	46	0	0
T289	155061	245	0	0
T290	20569	47	0	0

bank1_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1815	0	0
T62	3612	1	0	0
T200	4753	13	0	0
T208	9446	15	0	0
T213	5018	2	0	0
T221	21147	43	0	0
T224	19310	48	0	0
T225	4062	5	0	0
T231	74624	42	0	0
T289	155061	249	0	0
T290	20569	22	0	0

bank1_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2377	0	0
T62	3612	7	0	0
T200	4753	13	0	0
T208	9446	16	0	0
T213	5018	6	0	0
T221	21147	28	0	0
T224	19310	41	0	0
T225	4062	4	0	0
T231	74624	41	0	0
T289	155061	252	0	0
T290	20569	51	0	0

bank1_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1935	0	0
T62	3612	3	0	0
T200	4753	5	0	0
T208	9446	16	0	0
T213	5018	1	0	0
T221	21147	2	0	0
T224	19310	33	0	0
T225	4062	3	0	0
T231	74624	70	0	0
T289	155061	247	0	0
T290	20569	15	0	0

bank1_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1679	0	0
T62	3612	4	0	0
T200	4753	7	0	0
T208	9446	18	0	0
T213	5018	4	0	0
T221	21147	48	0	0
T224	19310	29	0	0
T225	4062	2	0	0
T231	74624	25	0	0
T289	155061	200	0	0
T290	20569	71	0	0

bank1_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1231	0	0
T62	3612	5	0	0
T200	4753	8	0	0
T208	9446	13	0	0
T213	5018	6	0	0
T221	21147	28	0	0
T224	19310	49	0	0
T225	4062	3	0	0
T231	74624	39	0	0
T289	155061	194	0	0
T290	20569	12	0	0

bank1_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1752	0	0
T62	3612	4	0	0
T200	4753	2	0	0
T208	9446	19	0	0
T213	5018	6	0	0
T221	21147	27	0	0
T224	19310	52	0	0
T225	4062	1	0	0
T231	74624	83	0	0
T289	155061	239	0	0
T290	20569	18	0	0

bank1_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1846	0	0
T62	3612	3	0	0
T200	4753	14	0	0
T208	9446	15	0	0
T213	5018	1	0	0
T221	21147	24	0	0
T224	19310	78	0	0
T225	4062	7	0	0
T231	74624	53	0	0
T289	155061	214	0	0
T290	20569	63	0	0

bank1_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1903	0	0
T62	3612	9	0	0
T200	4753	11	0	0
T208	9446	14	0	0
T213	5018	7	0	0
T221	21147	26	0	0
T224	19310	35	0	0
T231	74624	81	0	0
T289	155061	214	0	0
T290	20569	58	0	0
T291	10478	14	0	0

bank1_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1467	0	0
T62	3612	2	0	0
T200	4753	11	0	0
T208	9446	22	0	0
T213	5018	4	0	0
T221	21147	76	0	0
T224	19310	45	0	0
T225	4062	7	0	0
T231	74624	38	0	0
T289	155061	250	0	0
T290	20569	30	0	0

bank1_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1788	0	0
T62	3612	21	0	0
T200	4753	17	0	0
T208	9446	51	0	0
T213	5018	10	0	0
T221	21147	52	0	0
T224	19310	33	0	0
T225	4062	42	0	0
T231	74624	176	0	0
T289	155061	238	0	0
T290	20569	25	0	0

bank1_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2262	0	0
T62	3612	4	0	0
T200	4753	3	0	0
T208	9446	19	0	0
T213	5018	10	0	0
T221	21147	34	0	0
T224	19310	63	0	0
T225	4062	2	0	0
T231	74624	47	0	0
T289	155061	222	0	0
T290	20569	17	0	0

bank1_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2271	0	0
T62	3612	26	0	0
T200	4753	10	0	0
T208	9446	81	0	0
T213	5018	3	0	0
T221	21147	38	0	0
T224	19310	31	0	0
T225	4062	34	0	0
T231	74624	158	0	0
T289	155061	202	0	0
T290	20569	29	0	0

bank1_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2731	0	0
T62	3612	3	0	0
T200	4753	2	0	0
T208	9446	36	0	0
T213	5018	35	0	0
T221	21147	19	0	0
T224	19310	43	0	0
T225	4062	27	0	0
T231	74624	127	0	0
T289	155061	239	0	0
T290	20569	37	0	0

bank1_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1377	0	0
T62	3612	5	0	0
T200	4753	10	0	0
T208	9446	15	0	0
T213	5018	3	0	0
T221	21147	94	0	0
T224	19310	65	0	0
T225	4062	6	0	0
T231	74624	44	0	0
T289	155061	202	0	0
T290	20569	44	0	0

bank1_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1426	0	0
T62	3612	7	0	0
T200	4753	11	0	0
T208	9446	23	0	0
T213	5018	2	0	0
T221	21147	64	0	0
T224	19310	66	0	0
T225	4062	1	0	0
T231	74624	20	0	0
T289	155061	226	0	0
T290	20569	49	0	0

bank_cfg_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1317	0	0
T62	3612	3	0	0
T200	4753	12	0	0
T208	9446	8	0	0
T213	5018	7	0	0
T221	21147	89	0	0
T224	19310	51	0	0
T231	74624	50	0	0
T289	155061	220	0	0
T290	20569	27	0	0
T291	10478	19	0	0

default_region_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2762	0	0
T62	3612	2	0	0
T200	4753	11	0	0
T208	9446	24	0	0
T213	5018	17	0	0
T221	21147	39	0	0
T224	19310	19	0	0
T231	74624	156	0	0
T289	155061	198	0	0
T290	20569	97	0	0
T291	10478	63	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2084	0	0
T62	3612	1	0	0
T200	4753	1	0	0
T208	9446	17	0	0
T213	5018	8	0	0
T221	21147	35	0	0
T224	19310	30	0	0
T225	4062	4	0	0
T231	74624	54	0	0
T289	155061	237	0	0
T290	20569	28	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2348	0	0
T62	3612	8	0	0
T200	4753	10	0	0
T208	9446	29	0	0
T213	5018	7	0	0
T221	21147	28	0	0
T224	19310	46	0	0
T225	4062	11	0	0
T231	74624	109	0	0
T289	155061	209	0	0
T290	20569	53	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2223	0	0
T62	3612	9	0	0
T200	4753	5	0	0
T208	9446	8	0	0
T221	21147	3	0	0
T224	19310	19	0	0
T225	4062	8	0	0
T231	74624	33	0	0
T289	155061	230	0	0
T290	20569	52	0	0
T291	10478	12	0	0

hw_info_cfg_override_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2344	0	0
T62	3612	8	0	0
T200	4753	8	0	0
T208	9446	8	0	0
T213	5018	1	0	0
T221	21147	55	0	0
T224	19310	17	0	0
T225	4062	7	0	0
T231	74624	88	0	0
T289	155061	208	0	0
T290	20569	41	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2683	0	0
T62	3612	28	0	0
T200	4753	6	0	0
T208	9446	59	0	0
T213	5018	6	0	0
T221	21147	68	0	0
T224	19310	83	0	0
T225	4062	13	0	0
T231	74624	86	0	0
T289	155061	196	0	0
T290	20569	19	0	0

mp_region_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2423	0	0
T62	3612	13	0	0
T200	4753	10	0	0
T208	9446	20	0	0
T213	5018	17	0	0
T221	21147	57	0	0
T224	19310	55	0	0
T225	4062	3	0	0
T231	74624	62	0	0
T289	155061	229	0	0
T290	20569	58	0	0

mp_region_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2294	0	0
T62	3612	10	0	0
T200	4753	1	0	0
T208	9446	24	0	0
T213	5018	4	0	0
T221	21147	23	0	0
T224	19310	50	0	0
T225	4062	2	0	0
T231	74624	37	0	0
T289	155061	216	0	0
T290	20569	82	0	0

mp_region_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2430	0	0
T62	3612	3	0	0
T200	4753	7	0	0
T208	9446	13	0	0
T221	21147	67	0	0
T224	19310	21	0	0
T225	4062	5	0	0
T231	74624	58	0	0
T289	155061	214	0	0
T290	20569	36	0	0
T291	10478	24	0	0

mp_region_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1386	0	0
T62	3612	6	0	0
T200	4753	9	0	0
T208	9446	16	0	0
T213	5018	14	0	0
T221	21147	26	0	0
T224	19310	77	0	0
T225	4062	7	0	0
T231	74624	57	0	0
T289	155061	212	0	0
T290	20569	62	0	0

mp_region_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2478	0	0
T62	3612	3	0	0
T200	4753	15	0	0
T208	9446	14	0	0
T213	5018	3	0	0
T221	21147	18	0	0
T224	19310	33	0	0
T225	4062	3	0	0
T231	74624	95	0	0
T289	155061	217	0	0
T290	20569	52	0	0

mp_region_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1731	0	0
T62	3612	3	0	0
T200	4753	10	0	0
T208	9446	7	0	0
T221	21147	7	0	0
T224	19310	10	0	0
T225	4062	8	0	0
T231	74624	35	0	0
T289	155061	202	0	0
T290	20569	49	0	0
T291	10478	9	0	0

mp_region_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2452	0	0
T62	3612	9	0	0
T200	4753	10	0	0
T208	9446	23	0	0
T213	5018	2	0	0
T221	21147	47	0	0
T224	19310	33	0	0
T225	4062	8	0	0
T231	74624	74	0	0
T289	155061	252	0	0
T290	20569	91	0	0

mp_region_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1420	0	0
T62	3612	2	0	0
T200	4753	12	0	0
T208	9446	11	0	0
T213	5018	1	0	0
T221	21147	50	0	0
T224	19310	24	0	0
T225	4062	5	0	0
T231	74624	84	0	0
T289	155061	194	0	0
T290	20569	60	0	0

mp_region_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2677	0	0
T62	3612	27	0	0
T200	4753	11	0	0
T208	9446	35	0	0
T213	5018	12	0	0
T221	21147	17	0	0
T224	19310	84	0	0
T225	4062	35	0	0
T231	74624	158	0	0
T289	155061	223	0	0
T290	20569	25	0	0

mp_region_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2156	0	0
T62	3612	29	0	0
T200	4753	10	0	0
T208	9446	34	0	0
T221	21147	55	0	0
T224	19310	52	0	0
T225	4062	17	0	0
T231	74624	123	0	0
T289	155061	214	0	0
T290	20569	16	0	0
T291	10478	45	0	0

mp_region_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2266	0	0
T62	3612	20	0	0
T200	4753	6	0	0
T208	9446	47	0	0
T213	5018	8	0	0
T221	21147	21	0	0
T224	19310	69	0	0
T231	74624	130	0	0
T289	155061	232	0	0
T290	20569	11	0	0
T291	10478	30	0	0

mp_region_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2131	0	0
T62	3612	15	0	0
T200	4753	6	0	0
T208	9446	24	0	0
T221	21147	84	0	0
T224	19310	12	0	0
T225	4062	3	0	0
T231	74624	145	0	0
T289	155061	214	0	0
T290	20569	38	0	0
T291	10478	36	0	0

mp_region_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2671	0	0
T200	4753	9	0	0
T208	9446	39	0	0
T221	21147	57	0	0
T224	19310	15	0	0
T225	4062	30	0	0
T231	74624	185	0	0
T289	155061	212	0	0
T290	20569	2	0	0
T291	10478	22	0	0
T292	10251	23	0	0

mp_region_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2746	0	0
T62	3612	22	0	0
T200	4753	7	0	0
T208	9446	37	0	0
T213	5018	14	0	0
T221	21147	34	0	0
T224	19310	46	0	0
T225	4062	2	0	0
T231	74624	150	0	0
T289	155061	208	0	0
T290	20569	47	0	0

mp_region_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2698	0	0
T62	3612	19	0	0
T200	4753	2	0	0
T208	9446	45	0	0
T213	5018	23	0	0
T221	21147	25	0	0
T224	19310	73	0	0
T225	4062	2	0	0
T231	74624	154	0	0
T289	155061	211	0	0
T290	20569	24	0	0

mp_region_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1871	0	0
T62	3612	6	0	0
T200	4753	5	0	0
T208	9446	31	0	0
T213	5018	8	0	0
T221	21147	58	0	0
T224	19310	60	0	0
T225	4062	3	0	0
T231	74624	221	0	0
T289	155061	268	0	0
T290	20569	48	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1237	0	0
T200	4753	11	0	0
T208	9446	7	0	0
T221	21147	20	0	0
T224	19310	59	0	0
T290	20569	71	0	0
T291	10478	6	0	0
T292	10251	19	0	0
T293	2978	5	0	0
T294	10546	14	0	0
T295	78699	505	0	0

region_cfg_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1740	0	0
T62	3612	3	0	0
T200	4753	10	0	0
T208	9446	25	0	0
T213	5018	6	0	0
T221	21147	58	0	0
T224	19310	16	0	0
T225	4062	2	0	0
T231	74624	55	0	0
T289	155061	190	0	0
T290	20569	14	0	0

region_cfg_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1864	0	0
T62	3612	6	0	0
T200	4753	13	0	0
T208	9446	11	0	0
T213	5018	4	0	0
T221	21147	46	0	0
T224	19310	34	0	0
T225	4062	7	0	0
T231	74624	64	0	0
T289	155061	238	0	0
T290	20569	67	0	0

region_cfg_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1781	0	0
T62	3612	1	0	0
T200	4753	8	0	0
T208	9446	22	0	0
T213	5018	15	0	0
T221	21147	50	0	0
T224	19310	41	0	0
T225	4062	6	0	0
T231	74624	26	0	0
T289	155061	238	0	0
T290	20569	21	0	0

region_cfg_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	2189	0	0
T62	3612	6	0	0
T200	4753	8	0	0
T208	9446	7	0	0
T213	5018	3	0	0
T221	21147	27	0	0
T224	19310	25	0	0
T231	74624	37	0	0
T289	155061	195	0	0
T290	20569	39	0	0
T291	10478	13	0	0

region_cfg_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1886	0	0
T200	4753	9	0	0
T208	9446	22	0	0
T213	5018	3	0	0
T221	21147	74	0	0
T224	19310	67	0	0
T225	4062	2	0	0
T231	74624	52	0	0
T289	155061	196	0	0
T290	20569	72	0	0
T291	10478	10	0	0

region_cfg_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1231	0	0
T62	3612	3	0	0
T200	4753	8	0	0
T208	9446	14	0	0
T213	5018	8	0	0
T221	21147	21	0	0
T224	19310	16	0	0
T225	4062	7	0	0
T231	74624	46	0	0
T289	155061	226	0	0
T290	20569	50	0	0

region_cfg_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1961	0	0
T62	3612	2	0	0
T200	4753	9	0	0
T208	9446	11	0	0
T213	5018	2	0	0
T221	21147	100	0	0
T224	19310	47	0	0
T225	4062	9	0	0
T231	74624	40	0	0
T289	155061	247	0	0
T290	20569	20	0	0

region_cfg_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1718	0	0
T62	3612	3	0	0
T200	4753	2	0	0
T208	9446	13	0	0
T221	21147	35	0	0
T224	19310	28	0	0
T225	4062	2	0	0
T231	74624	46	0	0
T289	155061	222	0	0
T290	20569	16	0	0
T291	10478	11	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371727590	1712	0	0
T62	3612	6	0	0
T200	4753	12	0	0
T208	9446	21	0	0
T213	5018	7	0	0
T221	21147	35	0	0
T224	19310	26	0	0
T225	4062	3	0	0
T231	74624	45	0	0
T289	155061	239	0	0
T290	20569	36	0	0