Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22756077	1		T1	7112		T2	2377		T3	1379
full_word	7234659	1		T1	13379		T2	559		T3	311

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	29990436	1		T1	20491		T2	2936		T3	1690
auto[TlIntgErrCmd]	103	1		T63	3		T64	2		T205	8
auto[TlIntgErrData]	106	1		T63	11		T64	5		T205	7
auto[TlIntgErrBoth]	91	1		T63	6		T64	3		T205	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26019728	1		T1	13134		T2	2642		T3	1468
auto[1]	3971008	1		T1	7357		T2	294		T3	222

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22168329	1		T1	6803		T2	2299		T3	1360
auto[TlIntgErrNone]	partial	auto[1]	587479	1		T1	309		T2	78		T3	19
auto[TlIntgErrNone]	full_word	auto[0]	3851260	1		T1	6331		T2	343		T3	108
auto[TlIntgErrNone]	full_word	auto[1]	3383368	1		T1	7048		T2	216		T3	203
auto[TlIntgErrCmd]	partial	auto[0]	46	1		T63	3		T64	1		T205	5
auto[TlIntgErrCmd]	partial	auto[1]	46	1		T64	1		T205	3		T216	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T268	1		T332	1		T333	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T269	1		T332	1		T334	1
auto[TlIntgErrData]	partial	auto[0]	45	1		T63	4		T64	2		T205	4
auto[TlIntgErrData]	partial	auto[1]	51	1		T63	5		T64	3		T205	3
auto[TlIntgErrData]	full_word	auto[0]	5	1		T63	1		T265	1		T271	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T63	1		T216	1		T331	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1		T63	1		T64	2		T205	1
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T63	3		T64	1		T205	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T216	1		T335	1		T334	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T63	2		T205	1		T265	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20699	1		T61	361		T63	18		T65	1324
full_word	3445269	1		T2	7		T3	146		T4	16770

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3465692	1		T2	7		T3	146		T4	16770
auto[TlIntgErrCmd]	90	1		T63	10		T64	3		T205	3
auto[TlIntgErrData]	109	1		T63	6		T64	5		T205	8
auto[TlIntgErrBoth]	77	1		T63	3		T64	2		T205	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3440351	1		T2	7		T3	146		T4	16770
auto[1]	25617	1		T61	391		T63	11		T65	1500

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1264	1		T61	9		T65	142		T204	106
auto[TlIntgErrNone]	partial	auto[1]	19175	1		T61	352		T65	1182		T204	1288
auto[TlIntgErrNone]	full_word	auto[0]	3438976	1		T2	7		T3	146		T4	16770
auto[TlIntgErrNone]	full_word	auto[1]	6277	1		T61	39		T65	318		T204	336
auto[TlIntgErrCmd]	partial	auto[0]	29	1		T63	4		T205	1		T265	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1		T63	5		T64	3		T205	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T335	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T63	1		T336	1		T337	1
auto[TlIntgErrData]	partial	auto[0]	54	1		T63	2		T64	3		T205	4
auto[TlIntgErrData]	partial	auto[1]	47	1		T63	4		T64	1		T205	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T205	1		T332	2		T336	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T64	1		T205	1		T268	1
auto[TlIntgErrBoth]	partial	auto[0]	20	1		T63	2		T205	2		T268	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1		T63	1		T64	2		T205	7
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T332	1		T334	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T338	1		T339	1		-	-