Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1381349108	1378567264	0	0
CheckNGreaterZero_A	3516	3516	0	0
GntImpliesReady_A	1381349108	349265574	0	0
GntImpliesValid_A	1381349108	349265574	0	0
GrantKnown_A	1381349108	1378567264	0	0
IdxKnown_A	1381349108	1378567264	0	0
IndexIsCorrect_A	1381349108	349265574	0	0
NoReadyValidNoGrant_A	1381349108	170760840	0	0
Priority_A	1381349108	372257520	0	0
ReadyAndValidImplyGrant_A	1381349108	349265574	0	0
ReqAndReadyImplyGrant_A	1381349108	349265574	0	0
ReqImpliesValid_A	1381349108	372257520	0	0
ValidKnown_A	1381349108	1378567264	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1381349108	1378567264	0	0
T1	576600	576208	0	0
T2	30496	30032	0	0
T3	73636	73160	0	0
T4	484868	484280	0	0
T5	2980	2732	0	0
T6	7352	7108	0	0
T23	6108	5884	0	0
T24	4892	4592	0	0
T25	1623192	1548312	0	0
T26	3304	3004	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3516	3516	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T23	4	4	0	0
T24	4	4	0	0
T25	4	4	0	0
T26	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1381349108	349265574	0	0
T1	288300	3136	0	0
T2	15248	6952	0	0
T3	73636	5510	0	0
T4	484868	69618	0	0
T5	2980	86	0	0
T6	7352	64	0	0
T9	416498	38422	0	0
T10	0	255794	0	0
T11	0	806098	0	0
T12	5124	590	0	0
T16	0	4976	0	0
T17	0	313234	0	0
T23	6108	64	0	0
T24	4892	64	0	0
T25	1623192	349924	0	0
T26	3304	64	0	0
T59	0	19548	0	0
T71	0	7786	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1381349108	349265574	0	0
T1	288300	3136	0	0
T2	15248	6952	0	0
T3	73636	5510	0	0
T4	484868	69618	0	0
T5	2980	86	0	0
T6	7352	64	0	0
T9	416498	38422	0	0
T10	0	255794	0	0
T11	0	806098	0	0
T12	5124	590	0	0
T16	0	4976	0	0
T17	0	313234	0	0
T23	6108	64	0	0
T24	4892	64	0	0
T25	1623192	349924	0	0
T26	3304	64	0	0
T59	0	19548	0	0
T71	0	7786	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1381349108	1378567264	0	0
T1	576600	576208	0	0
T2	30496	30032	0	0
T3	73636	73160	0	0
T4	484868	484280	0	0
T5	2980	2732	0	0
T6	7352	7108	0	0
T23	6108	5884	0	0
T24	4892	4592	0	0
T25	1623192	1548312	0	0
T26	3304	3004	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1381349108	1378567264	0	0
T1	576600	576208	0	0
T2	30496	30032	0	0
T3	73636	73160	0	0
T4	484868	484280	0	0
T5	2980	2732	0	0
T6	7352	7108	0	0
T23	6108	5884	0	0
T24	4892	4592	0	0
T25	1623192	1548312	0	0
T26	3304	3004	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1381349108	349265574	0	0
T1	288300	3136	0	0
T2	15248	6952	0	0
T3	73636	5510	0	0
T4	484868	69618	0	0
T5	2980	86	0	0
T6	7352	64	0	0
T9	416498	38422	0	0
T10	0	255794	0	0
T11	0	806098	0	0
T12	5124	590	0	0
T16	0	4976	0	0
T17	0	313234	0	0
T23	6108	64	0	0
T24	4892	64	0	0
T25	1623192	349924	0	0
T26	3304	64	0	0
T59	0	19548	0	0
T71	0	7786	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1381349108	170760840	0	0
T1	288300	4736	0	0
T2	15248	1810	0	0
T3	73636	1186	0	0
T4	484868	115002	0	0
T5	2980	314	0	0
T6	7352	256	0	0
T9	416498	3120	0	0
T10	0	1048576	0	0
T11	0	806400	0	0
T12	5124	328	0	0
T16	0	568	0	0
T17	0	98136	0	0
T23	6108	256	0	0
T24	4892	256	0	0
T25	1623192	91624	0	0
T26	3304	256	0	0
T59	0	782	0	0
T71	0	1142	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1381349108	372257520	0	0
T1	288300	3136	0	0
T2	15248	6952	0	0
T3	73636	5614	0	0
T4	484868	79378	0	0
T5	2980	86	0	0
T6	7352	64	0	0
T9	416498	38422	0	0
T10	0	255794	0	0
T11	0	806098	0	0
T12	5124	590	0	0
T16	0	4976	0	0
T17	0	354732	0	0
T23	6108	64	0	0
T24	4892	64	0	0
T25	1623192	349924	0	0
T26	3304	64	0	0
T59	0	19548	0	0
T71	0	7786	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1381349108	349265574	0	0
T1	288300	3136	0	0
T2	15248	6952	0	0
T3	73636	5510	0	0
T4	484868	69618	0	0
T5	2980	86	0	0
T6	7352	64	0	0
T9	416498	38422	0	0
T10	0	255794	0	0
T11	0	806098	0	0
T12	5124	590	0	0
T16	0	4976	0	0
T17	0	313234	0	0
T23	6108	64	0	0
T24	4892	64	0	0
T25	1623192	349924	0	0
T26	3304	64	0	0
T59	0	19548	0	0
T71	0	7786	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1381349108	349265574	0	0
T1	288300	3136	0	0
T2	15248	6952	0	0
T3	73636	5510	0	0
T4	484868	69618	0	0
T5	2980	86	0	0
T6	7352	64	0	0
T9	416498	38422	0	0
T10	0	255794	0	0
T11	0	806098	0	0
T12	5124	590	0	0
T16	0	4976	0	0
T17	0	313234	0	0
T23	6108	64	0	0
T24	4892	64	0	0
T25	1623192	349924	0	0
T26	3304	64	0	0
T59	0	19548	0	0
T71	0	7786	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1381349108	372257520	0	0
T1	288300	3136	0	0
T2	15248	6952	0	0
T3	73636	5614	0	0
T4	484868	79378	0	0
T5	2980	86	0	0
T6	7352	64	0	0
T9	416498	38422	0	0
T10	0	255794	0	0
T11	0	806098	0	0
T12	5124	590	0	0
T16	0	4976	0	0
T17	0	354732	0	0
T23	6108	64	0	0
T24	4892	64	0	0
T25	1623192	349924	0	0
T26	3304	64	0	0
T59	0	19548	0	0
T71	0	7786	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1381349108	1378567264	0	0
T1	576600	576208	0	0
T2	30496	30032	0	0
T3	73636	73160	0	0
T4	484868	484280	0	0
T5	2980	2732	0	0
T6	7352	7108	0	0
T23	6108	5884	0	0
T24	4892	4592	0	0
T25	1623192	1548312	0	0
T26	3304	3004	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	345337277	344641816	0	0
CheckNGreaterZero_A	879	879	0	0
GntImpliesReady_A	345337277	86532838	0	0
GntImpliesValid_A	345337277	86532838	0	0
GrantKnown_A	345337277	344641816	0	0
IdxKnown_A	345337277	344641816	0	0
IndexIsCorrect_A	345337277	86532838	0	0
NoReadyValidNoGrant_A	345337277	43607996	0	0
Priority_A	345337277	92259913	0	0
ReadyAndValidImplyGrant_A	345337277	86532838	0	0
ReqAndReadyImplyGrant_A	345337277	86532838	0	0
ReqImpliesValid_A	345337277	92259913	0	0
ValidKnown_A	345337277	344641816	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	344641816	0	0
T1	144150	144052	0	0
T2	7624	7508	0	0
T3	18409	18290	0	0
T4	121217	121070	0	0
T5	745	683	0	0
T6	1838	1777	0	0
T23	1527	1471	0	0
T24	1223	1148	0	0
T25	405798	387078	0	0
T26	826	751	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	86532838	0	0
T1	144150	1568	0	0
T2	7624	3476	0	0
T3	18409	2619	0	0
T4	121217	18352	0	0
T5	745	43	0	0
T6	1838	32	0	0
T23	1527	32	0	0
T24	1223	32	0	0
T25	405798	174962	0	0
T26	826	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	86532838	0	0
T1	144150	1568	0	0
T2	7624	3476	0	0
T3	18409	2619	0	0
T4	121217	18352	0	0
T5	745	43	0	0
T6	1838	32	0	0
T23	1527	32	0	0
T24	1223	32	0	0
T25	405798	174962	0	0
T26	826	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	344641816	0	0
T1	144150	144052	0	0
T2	7624	7508	0	0
T3	18409	18290	0	0
T4	121217	121070	0	0
T5	745	683	0	0
T6	1838	1777	0	0
T23	1527	1471	0	0
T24	1223	1148	0	0
T25	405798	387078	0	0
T26	826	751	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	344641816	0	0
T1	144150	144052	0	0
T2	7624	7508	0	0
T3	18409	18290	0	0
T4	121217	121070	0	0
T5	745	683	0	0
T6	1838	1777	0	0
T23	1527	1471	0	0
T24	1223	1148	0	0
T25	405798	387078	0	0
T26	826	751	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	86532838	0	0
T1	144150	1568	0	0
T2	7624	3476	0	0
T3	18409	2619	0	0
T4	121217	18352	0	0
T5	745	43	0	0
T6	1838	32	0	0
T23	1527	32	0	0
T24	1223	32	0	0
T25	405798	174962	0	0
T26	826	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	43607996	0	0
T1	144150	2368	0	0
T2	7624	905	0	0
T3	18409	468	0	0
T4	121217	31091	0	0
T5	745	157	0	0
T6	1838	128	0	0
T23	1527	128	0	0
T24	1223	128	0	0
T25	405798	45812	0	0
T26	826	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	92259913	0	0
T1	144150	1568	0	0
T2	7624	3476	0	0
T3	18409	2631	0	0
T4	121217	20896	0	0
T5	745	43	0	0
T6	1838	32	0	0
T23	1527	32	0	0
T24	1223	32	0	0
T25	405798	174962	0	0
T26	826	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	86532838	0	0
T1	144150	1568	0	0
T2	7624	3476	0	0
T3	18409	2619	0	0
T4	121217	18352	0	0
T5	745	43	0	0
T6	1838	32	0	0
T23	1527	32	0	0
T24	1223	32	0	0
T25	405798	174962	0	0
T26	826	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	86532838	0	0
T1	144150	1568	0	0
T2	7624	3476	0	0
T3	18409	2619	0	0
T4	121217	18352	0	0
T5	745	43	0	0
T6	1838	32	0	0
T23	1527	32	0	0
T24	1223	32	0	0
T25	405798	174962	0	0
T26	826	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	92259913	0	0
T1	144150	1568	0	0
T2	7624	3476	0	0
T3	18409	2631	0	0
T4	121217	20896	0	0
T5	745	43	0	0
T6	1838	32	0	0
T23	1527	32	0	0
T24	1223	32	0	0
T25	405798	174962	0	0
T26	826	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	344641816	0	0
T1	144150	144052	0	0
T2	7624	7508	0	0
T3	18409	18290	0	0
T4	121217	121070	0	0
T5	745	683	0	0
T6	1838	1777	0	0
T23	1527	1471	0	0
T24	1223	1148	0	0
T25	405798	387078	0	0
T26	826	751	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	345337277	344641816	0	0
CheckNGreaterZero_A	879	879	0	0
GntImpliesReady_A	345337277	86532762	0	0
GntImpliesValid_A	345337277	86532762	0	0
GrantKnown_A	345337277	344641816	0	0
IdxKnown_A	345337277	344641816	0	0
IndexIsCorrect_A	345337277	86532762	0	0
NoReadyValidNoGrant_A	345337277	43607996	0	0
Priority_A	345337277	92259837	0	0
ReadyAndValidImplyGrant_A	345337277	86532762	0	0
ReqAndReadyImplyGrant_A	345337277	86532762	0	0
ReqImpliesValid_A	345337277	92259837	0	0
ValidKnown_A	345337277	344641816	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	344641816	0	0
T1	144150	144052	0	0
T2	7624	7508	0	0
T3	18409	18290	0	0
T4	121217	121070	0	0
T5	745	683	0	0
T6	1838	1777	0	0
T23	1527	1471	0	0
T24	1223	1148	0	0
T25	405798	387078	0	0
T26	826	751	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	86532762	0	0
T1	144150	1568	0	0
T2	7624	3476	0	0
T3	18409	2619	0	0
T4	121217	18352	0	0
T5	745	43	0	0
T6	1838	32	0	0
T23	1527	32	0	0
T24	1223	32	0	0
T25	405798	174962	0	0
T26	826	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	86532762	0	0
T1	144150	1568	0	0
T2	7624	3476	0	0
T3	18409	2619	0	0
T4	121217	18352	0	0
T5	745	43	0	0
T6	1838	32	0	0
T23	1527	32	0	0
T24	1223	32	0	0
T25	405798	174962	0	0
T26	826	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	344641816	0	0
T1	144150	144052	0	0
T2	7624	7508	0	0
T3	18409	18290	0	0
T4	121217	121070	0	0
T5	745	683	0	0
T6	1838	1777	0	0
T23	1527	1471	0	0
T24	1223	1148	0	0
T25	405798	387078	0	0
T26	826	751	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	344641816	0	0
T1	144150	144052	0	0
T2	7624	7508	0	0
T3	18409	18290	0	0
T4	121217	121070	0	0
T5	745	683	0	0
T6	1838	1777	0	0
T23	1527	1471	0	0
T24	1223	1148	0	0
T25	405798	387078	0	0
T26	826	751	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	86532762	0	0
T1	144150	1568	0	0
T2	7624	3476	0	0
T3	18409	2619	0	0
T4	121217	18352	0	0
T5	745	43	0	0
T6	1838	32	0	0
T23	1527	32	0	0
T24	1223	32	0	0
T25	405798	174962	0	0
T26	826	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	43607996	0	0
T1	144150	2368	0	0
T2	7624	905	0	0
T3	18409	468	0	0
T4	121217	31091	0	0
T5	745	157	0	0
T6	1838	128	0	0
T23	1527	128	0	0
T24	1223	128	0	0
T25	405798	45812	0	0
T26	826	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	92259837	0	0
T1	144150	1568	0	0
T2	7624	3476	0	0
T3	18409	2631	0	0
T4	121217	20896	0	0
T5	745	43	0	0
T6	1838	32	0	0
T23	1527	32	0	0
T24	1223	32	0	0
T25	405798	174962	0	0
T26	826	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	86532762	0	0
T1	144150	1568	0	0
T2	7624	3476	0	0
T3	18409	2619	0	0
T4	121217	18352	0	0
T5	745	43	0	0
T6	1838	32	0	0
T23	1527	32	0	0
T24	1223	32	0	0
T25	405798	174962	0	0
T26	826	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	86532762	0	0
T1	144150	1568	0	0
T2	7624	3476	0	0
T3	18409	2619	0	0
T4	121217	18352	0	0
T5	745	43	0	0
T6	1838	32	0	0
T23	1527	32	0	0
T24	1223	32	0	0
T25	405798	174962	0	0
T26	826	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	92259837	0	0
T1	144150	1568	0	0
T2	7624	3476	0	0
T3	18409	2631	0	0
T4	121217	20896	0	0
T5	745	43	0	0
T6	1838	32	0	0
T23	1527	32	0	0
T24	1223	32	0	0
T25	405798	174962	0	0
T26	826	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	344641816	0	0
T1	144150	144052	0	0
T2	7624	7508	0	0
T3	18409	18290	0	0
T4	121217	121070	0	0
T5	745	683	0	0
T6	1838	1777	0	0
T23	1527	1471	0	0
T24	1223	1148	0	0
T25	405798	387078	0	0
T26	826	751	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T12
1	0	Covered	T3,T4,T12

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T12
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T12
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T12
1	0	Covered	T3,T4,T12
1	1	Covered	T3,T4,T12

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T12
1	1	Covered	T3,T4,T12

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T12
1	1	Covered	T3,T4,T12

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T12

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T12

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	345337277	344641816	0	0
CheckNGreaterZero_A	879	879	0	0
GntImpliesReady_A	345337277	88100023	0	0
GntImpliesValid_A	345337277	88100023	0	0
GrantKnown_A	345337277	344641816	0	0
IdxKnown_A	345337277	344641816	0	0
IndexIsCorrect_A	345337277	88100023	0	0
NoReadyValidNoGrant_A	345337277	41772423	0	0
Priority_A	345337277	93868922	0	0
ReadyAndValidImplyGrant_A	345337277	88100023	0	0
ReqAndReadyImplyGrant_A	345337277	88100023	0	0
ReqImpliesValid_A	345337277	93868922	0	0
ValidKnown_A	345337277	344641816	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	344641816	0	0
T1	144150	144052	0	0
T2	7624	7508	0	0
T3	18409	18290	0	0
T4	121217	121070	0	0
T5	745	683	0	0
T6	1838	1777	0	0
T23	1527	1471	0	0
T24	1223	1148	0	0
T25	405798	387078	0	0
T26	826	751	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	88100023	0	0
T3	18409	172	0	0
T4	121217	16457	0	0
T5	745	0	0	0
T6	1838	0	0	0
T9	208249	19211	0	0
T10	0	127897	0	0
T11	0	403049	0	0
T12	2562	295	0	0
T16	0	2488	0	0
T17	0	156617	0	0
T23	1527	0	0	0
T24	1223	0	0	0
T25	405798	0	0	0
T26	826	0	0	0
T59	0	9774	0	0
T71	0	3893	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	88100023	0	0
T3	18409	172	0	0
T4	121217	16457	0	0
T5	745	0	0	0
T6	1838	0	0	0
T9	208249	19211	0	0
T10	0	127897	0	0
T11	0	403049	0	0
T12	2562	295	0	0
T16	0	2488	0	0
T17	0	156617	0	0
T23	1527	0	0	0
T24	1223	0	0	0
T25	405798	0	0	0
T26	826	0	0	0
T59	0	9774	0	0
T71	0	3893	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	344641816	0	0
T1	144150	144052	0	0
T2	7624	7508	0	0
T3	18409	18290	0	0
T4	121217	121070	0	0
T5	745	683	0	0
T6	1838	1777	0	0
T23	1527	1471	0	0
T24	1223	1148	0	0
T25	405798	387078	0	0
T26	826	751	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	344641816	0	0
T1	144150	144052	0	0
T2	7624	7508	0	0
T3	18409	18290	0	0
T4	121217	121070	0	0
T5	745	683	0	0
T6	1838	1777	0	0
T23	1527	1471	0	0
T24	1223	1148	0	0
T25	405798	387078	0	0
T26	826	751	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	88100023	0	0
T3	18409	172	0	0
T4	121217	16457	0	0
T5	745	0	0	0
T6	1838	0	0	0
T9	208249	19211	0	0
T10	0	127897	0	0
T11	0	403049	0	0
T12	2562	295	0	0
T16	0	2488	0	0
T17	0	156617	0	0
T23	1527	0	0	0
T24	1223	0	0	0
T25	405798	0	0	0
T26	826	0	0	0
T59	0	9774	0	0
T71	0	3893	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	41772423	0	0
T3	18409	124	0	0
T4	121217	26410	0	0
T5	745	0	0	0
T6	1838	0	0	0
T9	208249	1560	0	0
T10	0	524288	0	0
T11	0	403200	0	0
T12	2562	164	0	0
T16	0	284	0	0
T17	0	49068	0	0
T23	1527	0	0	0
T24	1223	0	0	0
T25	405798	0	0	0
T26	826	0	0	0
T59	0	391	0	0
T71	0	571	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	93868922	0	0
T3	18409	213	0	0
T4	121217	18793	0	0
T5	745	0	0	0
T6	1838	0	0	0
T9	208249	19211	0	0
T10	0	127897	0	0
T11	0	403049	0	0
T12	2562	295	0	0
T16	0	2488	0	0
T17	0	177366	0	0
T23	1527	0	0	0
T24	1223	0	0	0
T25	405798	0	0	0
T26	826	0	0	0
T59	0	9774	0	0
T71	0	3893	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	88100023	0	0
T3	18409	172	0	0
T4	121217	16457	0	0
T5	745	0	0	0
T6	1838	0	0	0
T9	208249	19211	0	0
T10	0	127897	0	0
T11	0	403049	0	0
T12	2562	295	0	0
T16	0	2488	0	0
T17	0	156617	0	0
T23	1527	0	0	0
T24	1223	0	0	0
T25	405798	0	0	0
T26	826	0	0	0
T59	0	9774	0	0
T71	0	3893	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	88100023	0	0
T3	18409	172	0	0
T4	121217	16457	0	0
T5	745	0	0	0
T6	1838	0	0	0
T9	208249	19211	0	0
T10	0	127897	0	0
T11	0	403049	0	0
T12	2562	295	0	0
T16	0	2488	0	0
T17	0	156617	0	0
T23	1527	0	0	0
T24	1223	0	0	0
T25	405798	0	0	0
T26	826	0	0	0
T59	0	9774	0	0
T71	0	3893	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	93868922	0	0
T3	18409	213	0	0
T4	121217	18793	0	0
T5	745	0	0	0
T6	1838	0	0	0
T9	208249	19211	0	0
T10	0	127897	0	0
T11	0	403049	0	0
T12	2562	295	0	0
T16	0	2488	0	0
T17	0	177366	0	0
T23	1527	0	0	0
T24	1223	0	0	0
T25	405798	0	0	0
T26	826	0	0	0
T59	0	9774	0	0
T71	0	3893	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	344641816	0	0
T1	144150	144052	0	0
T2	7624	7508	0	0
T3	18409	18290	0	0
T4	121217	121070	0	0
T5	745	683	0	0
T6	1838	1777	0	0
T23	1527	1471	0	0
T24	1223	1148	0	0
T25	405798	387078	0	0
T26	826	751	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T12
1	0	Covered	T3,T4,T12

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T12
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T12
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T12
1	0	Covered	T3,T4,T12
1	1	Covered	T3,T4,T12

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T12
1	1	Covered	T3,T4,T12

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T12
1	1	Covered	T3,T4,T12

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T12

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T12

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	345337277	344641816	0	0
CheckNGreaterZero_A	879	879	0	0
GntImpliesReady_A	345337277	88099951	0	0
GntImpliesValid_A	345337277	88099951	0	0
GrantKnown_A	345337277	344641816	0	0
IdxKnown_A	345337277	344641816	0	0
IndexIsCorrect_A	345337277	88099951	0	0
NoReadyValidNoGrant_A	345337277	41772425	0	0
Priority_A	345337277	93868848	0	0
ReadyAndValidImplyGrant_A	345337277	88099951	0	0
ReqAndReadyImplyGrant_A	345337277	88099951	0	0
ReqImpliesValid_A	345337277	93868848	0	0
ValidKnown_A	345337277	344641816	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	344641816	0	0
T1	144150	144052	0	0
T2	7624	7508	0	0
T3	18409	18290	0	0
T4	121217	121070	0	0
T5	745	683	0	0
T6	1838	1777	0	0
T23	1527	1471	0	0
T24	1223	1148	0	0
T25	405798	387078	0	0
T26	826	751	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	88099951	0	0
T3	18409	100	0	0
T4	121217	16457	0	0
T5	745	0	0	0
T6	1838	0	0	0
T9	208249	19211	0	0
T10	0	127897	0	0
T11	0	403049	0	0
T12	2562	295	0	0
T16	0	2488	0	0
T17	0	156617	0	0
T23	1527	0	0	0
T24	1223	0	0	0
T25	405798	0	0	0
T26	826	0	0	0
T59	0	9774	0	0
T71	0	3893	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	88099951	0	0
T3	18409	100	0	0
T4	121217	16457	0	0
T5	745	0	0	0
T6	1838	0	0	0
T9	208249	19211	0	0
T10	0	127897	0	0
T11	0	403049	0	0
T12	2562	295	0	0
T16	0	2488	0	0
T17	0	156617	0	0
T23	1527	0	0	0
T24	1223	0	0	0
T25	405798	0	0	0
T26	826	0	0	0
T59	0	9774	0	0
T71	0	3893	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	344641816	0	0
T1	144150	144052	0	0
T2	7624	7508	0	0
T3	18409	18290	0	0
T4	121217	121070	0	0
T5	745	683	0	0
T6	1838	1777	0	0
T23	1527	1471	0	0
T24	1223	1148	0	0
T25	405798	387078	0	0
T26	826	751	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	344641816	0	0
T1	144150	144052	0	0
T2	7624	7508	0	0
T3	18409	18290	0	0
T4	121217	121070	0	0
T5	745	683	0	0
T6	1838	1777	0	0
T23	1527	1471	0	0
T24	1223	1148	0	0
T25	405798	387078	0	0
T26	826	751	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	88099951	0	0
T3	18409	100	0	0
T4	121217	16457	0	0
T5	745	0	0	0
T6	1838	0	0	0
T9	208249	19211	0	0
T10	0	127897	0	0
T11	0	403049	0	0
T12	2562	295	0	0
T16	0	2488	0	0
T17	0	156617	0	0
T23	1527	0	0	0
T24	1223	0	0	0
T25	405798	0	0	0
T26	826	0	0	0
T59	0	9774	0	0
T71	0	3893	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	41772425	0	0
T3	18409	126	0	0
T4	121217	26410	0	0
T5	745	0	0	0
T6	1838	0	0	0
T9	208249	1560	0	0
T10	0	524288	0	0
T11	0	403200	0	0
T12	2562	164	0	0
T16	0	284	0	0
T17	0	49068	0	0
T23	1527	0	0	0
T24	1223	0	0	0
T25	405798	0	0	0
T26	826	0	0	0
T59	0	391	0	0
T71	0	571	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	93868848	0	0
T3	18409	139	0	0
T4	121217	18793	0	0
T5	745	0	0	0
T6	1838	0	0	0
T9	208249	19211	0	0
T10	0	127897	0	0
T11	0	403049	0	0
T12	2562	295	0	0
T16	0	2488	0	0
T17	0	177366	0	0
T23	1527	0	0	0
T24	1223	0	0	0
T25	405798	0	0	0
T26	826	0	0	0
T59	0	9774	0	0
T71	0	3893	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	88099951	0	0
T3	18409	100	0	0
T4	121217	16457	0	0
T5	745	0	0	0
T6	1838	0	0	0
T9	208249	19211	0	0
T10	0	127897	0	0
T11	0	403049	0	0
T12	2562	295	0	0
T16	0	2488	0	0
T17	0	156617	0	0
T23	1527	0	0	0
T24	1223	0	0	0
T25	405798	0	0	0
T26	826	0	0	0
T59	0	9774	0	0
T71	0	3893	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	88099951	0	0
T3	18409	100	0	0
T4	121217	16457	0	0
T5	745	0	0	0
T6	1838	0	0	0
T9	208249	19211	0	0
T10	0	127897	0	0
T11	0	403049	0	0
T12	2562	295	0	0
T16	0	2488	0	0
T17	0	156617	0	0
T23	1527	0	0	0
T24	1223	0	0	0
T25	405798	0	0	0
T26	826	0	0	0
T59	0	9774	0	0
T71	0	3893	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	93868848	0	0
T3	18409	139	0	0
T4	121217	18793	0	0
T5	745	0	0	0
T6	1838	0	0	0
T9	208249	19211	0	0
T10	0	127897	0	0
T11	0	403049	0	0
T12	2562	295	0	0
T16	0	2488	0	0
T17	0	177366	0	0
T23	1527	0	0	0
T24	1223	0	0	0
T25	405798	0	0	0
T26	826	0	0	0
T59	0	9774	0	0
T71	0	3893	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	344641816	0	0
T1	144150	144052	0	0
T2	7624	7508	0	0
T3	18409	18290	0	0
T4	121217	121070	0	0
T5	745	683	0	0
T6	1838	1777	0	0
T23	1527	1471	0	0
T24	1223	1148	0	0
T25	405798	387078	0	0
T26	826	751	0	0