Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.69	100.00	98.46		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	99.69	100.00	98.46		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.65	100.00	96.92	95.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	100.00	83.02		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.69	100.00	98.46		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.74	100.00	98.46	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.62		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	64	98.46
Logical	65	64	98.46
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T25,T12

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T25,T12

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T113,T125
1	0	Covered	T18,T113,T125

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T25,T12
1	1	Covered	T18,T113,T125

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T113,T125
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T25,T12

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T3,T25,T12
1	Covered	T16,T78,T39

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T25,T12
1	0	Covered	T3,T25,T12
1	1	Covered	T3,T25,T12

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T25,T12

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T25,T12
1	1	Covered	T16,T78,T39

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T19
1	Covered	T16,T78,T39

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T25,T12
1	0	Covered	T3,T25,T12
1	1	Covered	T3,T25,T12

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T3,T25,T12
1	Covered	T3,T25,T12

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T25,T12
1	0	Covered	T3,T25,T12
1	1	Covered	T16,T78,T39

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T19
1	Covered	T16,T78,T39

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T3,T9,T11
1	Covered	T3,T25,T12

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T3,T25,T12
1	Covered	T3,T25,T12

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T3,T25,T12
1	Covered	T3,T25,T12

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T25,T12
1	1	Covered	T3,T25,T12

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T23
1	0	Covered	T3,T25,T12
1	1	Covered	T3,T25,T12

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T23
1	0	Covered	T3,T25,T12
1	1	Covered	T3,T25,T12

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T25,T12
1	1	0	Covered	T3,T25,T12
1	1	1	Covered	T3,T25,T12

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T25,T12

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T3,T25,T12
StCalcMask	237	Covered	T3,T25,T12
StCalcPlainEcc	215	Covered	T3,T25,T12
StDisabled	193	Covered	T5,T21,T10
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T3,T25,T12
StPostPack	218	Covered	T16,T78,T39
StPrePack	195	Covered	T16,T78,T39
StReqFlash	237	Covered	T3,T25,T12
StScrambleData	244	Covered	T3,T25,T12
StWaitFlash	270	Covered	T3,T25,T12

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T3,T25,T12
StCalcMask->StScrambleData	244	Covered	T3,T25,T12
StCalcPlainEcc->StCalcMask	237	Covered	T3,T25,T12
StCalcPlainEcc->StReqFlash	237	Covered	T3,T9,T11
StIdle->StDisabled	193	Covered	T5,T21,T10
StIdle->StPackData	197	Covered	T3,T25,T12
StIdle->StPrePack	195	Covered	T16,T78,T39
StPackData->StCalcPlainEcc	215	Covered	T3,T25,T12
StPackData->StPostPack	218	Covered	T16,T78,T39
StPostPack->StCalcPlainEcc	231	Covered	T16,T78,T39
StPrePack->StPackData	205	Covered	T16,T78,T39
StReqFlash->StIdle	273	Covered	T3,T25,T12
StReqFlash->StWaitFlash	270	Covered	T3,T25,T12
StScrambleData->StCalcEcc	252	Covered	T3,T25,T12
StWaitFlash->StIdle	280	Covered	T3,T25,T12

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T25,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T25,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T25,T12
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T25,T12
0	0	1	Covered	T3,T25,T12
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T21,T10
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T78,T39
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T12
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T78,T39
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T19
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T12
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T16,T78,T39
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T3,T25,T12
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T3,T25,T12
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T16,T78,T39
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T19
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T25,T12
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T3,T9,T11
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T3,T25,T12
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T25,T12
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T25,T12
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T25,T12
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T12
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T3,T25,T12
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T3,T25,T12
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T3,T25,T12
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T3,T25,T12
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T25,T12
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T25,T12
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T21,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T3,T25,T12
0	0	1	-	-	Covered	T3,T25,T12
0	0	0	1	-	Covered	T3,T25,T12
0	0	0	0	1	Covered	T3,T25,T12
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T25,T12
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	690674554	2380144	0	0
PostPackRule_A	690674554	1956	0	0
PrePackRule_A	690674554	1373	0	0
WidthCheck_A	1758	1758	0	0
u_state_regs_A	690674554	689283632	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690674554	2380144	0	0
T3	18409	13	0	0
T4	121217	0	0	0
T5	745	0	0	0
T6	1838	0	0	0
T9	416498	100	0	0
T10	385053	65921	0	0
T11	489128	8608	0	0
T12	5124	1	0	0
T16	4764	4	0	0
T17	0	2246	0	0
T21	3495	0	0	0
T22	3521	0	0	0
T23	1527	0	0	0
T24	1223	0	0	0
T25	405798	363	0	0
T26	826	0	0	0
T27	0	3	0	0
T32	3634	0	0	0
T33	0	1472	0	0
T39	0	4	0	0
T43	0	7	0	0
T59	13213	0	0	0
T71	6913	0	0	0
T78	0	2	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690674554	1956	0	0
T7	7182	0	0	0
T13	0	51	0	0
T16	4764	1	0	0
T17	459681	0	0	0
T22	3521	0	0	0
T27	72672	4	0	0
T28	0	9	0	0
T31	3449	0	0	0
T33	479578	0	0	0
T39	274232	2	0	0
T43	142120	3	0	0
T60	3510	0	0	0
T66	3489	0	0	0
T67	0	11	0	0
T72	1283	0	0	0
T78	7200	1	0	0
T126	0	23	0	0
T151	2192	0	0	0
T177	0	43	0	0
T207	0	2	0	0
T218	0	1	0	0
T232	0	4	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690674554	1373	0	0
T7	7182	0	0	0
T13	0	34	0	0
T16	4764	2	0	0
T17	459681	0	0	0
T22	3521	0	0	0
T27	72672	3	0	0
T28	0	6	0	0
T31	3449	0	0	0
T33	479578	0	0	0
T39	274232	2	0	0
T43	142120	4	0	0
T60	3510	0	0	0
T66	3489	0	0	0
T67	0	3	0	0
T72	1283	0	0	0
T78	7200	2	0	0
T151	2192	0	0	0
T177	0	22	0	0
T218	0	1	0	0
T232	0	3	0	0
T233	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1758	1758	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T23	2	2	0	0
T24	2	2	0	0
T25	2	2	0	0
T26	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690674554	689283632	0	0
T1	288300	288104	0	0
T2	15248	15016	0	0
T3	36818	36580	0	0
T4	242434	242140	0	0
T5	1490	1366	0	0
T6	3676	3554	0	0
T23	3054	2942	0	0
T24	2446	2296	0	0
T25	811596	774156	0	0
T26	1652	1502	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T9,T10

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T9,T10

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T20,T234
1	0	Covered	T18,T20,T234

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T9,T10
1	1	Covered	T18,T20,T234

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T20,T234
1	0	Covered	T3,T4,T12

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T9,T10

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T12,T9,T10
1	Covered	T16,T39,T27

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T12,T9,T10
1	0	Covered	T12,T9,T10
1	1	Covered	T12,T9,T10

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T9,T10

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T9,T10
1	1	Covered	T16,T78,T39

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T19
1	Covered	T16,T78,T39

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T12,T9,T10
1	0	Covered	T12,T9,T10
1	1	Covered	T12,T9,T10

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T12,T9,T10
1	Covered	T12,T9,T10

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T12,T9,T10
1	0	Covered	T12,T9,T10
1	1	Covered	T16,T39,T27

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T19
1	Covered	T16,T39,T27

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T9,T11,T16
1	Covered	T12,T10,T29

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T12,T9,T11
1	Covered	T12,T9,T10

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T12,T9,T11
1	Covered	T12,T9,T10

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T9,T11
1	1	Covered	T12,T9,T10

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T12
1	0	Covered	T12,T10,T29
1	1	Covered	T12,T10,T29

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T59
1	0	Covered	T12,T10,T29
1	1	Covered	T12,T10,T29

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T12,T9,T10
1	1	0	Covered	T12,T9,T10
1	1	1	Covered	T12,T9,T10

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T9,T10

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T12

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T12,T95,T84
StCalcMask	237	Covered	T12,T95,T84
StCalcPlainEcc	215	Covered	T12,T9,T11
StDisabled	193	Covered	T5,T21,T10
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T12,T9,T11
StPostPack	218	Covered	T16,T39,T27
StPrePack	195	Covered	T16,T78,T39
StReqFlash	237	Covered	T12,T9,T11
StScrambleData	244	Covered	T12,T95,T84
StWaitFlash	270	Covered	T12,T9,T10

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T12,T95,T84
StCalcMask->StScrambleData	244	Covered	T12,T95,T84
StCalcPlainEcc->StCalcMask	237	Covered	T12,T95,T84
StCalcPlainEcc->StReqFlash	237	Covered	T9,T11,T16
StIdle->StDisabled	193	Covered	T5,T21,T10
StIdle->StPackData	197	Covered	T12,T9,T11
StIdle->StPrePack	195	Covered	T16,T78,T39
StPackData->StCalcPlainEcc	215	Covered	T12,T9,T11
StPackData->StPostPack	218	Covered	T16,T39,T27
StPostPack->StCalcPlainEcc	231	Covered	T16,T39,T27
StPrePack->StPackData	205	Covered	T16,T78,T39
StReqFlash->StIdle	273	Covered	T12,T9,T10
StReqFlash->StWaitFlash	270	Covered	T12,T9,T10
StScrambleData->StCalcEcc	252	Covered	T12,T95,T84
StWaitFlash->StIdle	280	Covered	T12,T9,T10

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T9,T10
0	1	Covered	T3,T4,T12
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T12,T9,T10
0	0	1	Covered	T12,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T21,T10
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T78,T39
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T9,T10
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T78,T39
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T19
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T9,T10
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T16,T39,T27
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T12,T9,T10
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T12,T9,T10
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T16,T39,T27
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T19
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T12,T10,T29
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T9,T11,T16
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T12,T10,T29
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T12,T10,T29
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T12,T10,T29
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T12,T10,T29
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T10,T29
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T12,T9,T10
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T12,T9,T11
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T12,T9,T10
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T12,T9,T11
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12,T9,T10
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T12,T9,T10
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T21,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T12,T9,T10
0	0	1	-	-	Covered	T12,T10,T29
0	0	0	1	-	Covered	T12,T10,T29
0	0	0	0	1	Covered	T12,T9,T10
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T12,T9,T10
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	345337277	1189534	0	0
PostPackRule_A	345337277	988	0	0
PrePackRule_A	345337277	696	0	0
WidthCheck_A	879	879	0	0
u_state_regs_A	345337277	344641816	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	1189534	0	0
T9	208249	43	0	0
T10	385053	32768	0	0
T11	489128	8608	0	0
T12	2562	1	0	0
T16	4764	4	0	0
T17	0	1031	0	0
T21	3495	0	0	0
T22	3521	0	0	0
T32	3634	0	0	0
T33	0	1105	0	0
T39	0	3	0	0
T43	0	1	0	0
T59	13213	0	0	0
T71	6913	0	0	0
T78	0	1	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	988	0	0
T7	3591	0	0	0
T13	0	26	0	0
T16	4764	1	0	0
T17	459681	0	0	0
T22	3521	0	0	0
T27	0	2	0	0
T28	0	5	0	0
T33	239789	0	0	0
T39	137116	1	0	0
T43	71060	0	0	0
T60	3510	0	0	0
T67	0	5	0	0
T78	3600	0	0	0
T126	0	23	0	0
T151	1096	0	0	0
T177	0	26	0	0
T207	0	2	0	0
T232	0	1	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	696	0	0
T7	3591	0	0	0
T13	0	17	0	0
T16	4764	2	0	0
T17	459681	0	0	0
T22	3521	0	0	0
T27	0	2	0	0
T28	0	4	0	0
T33	239789	0	0	0
T39	137116	1	0	0
T43	71060	1	0	0
T60	3510	0	0	0
T67	0	3	0	0
T78	3600	1	0	0
T151	1096	0	0	0
T177	0	13	0	0
T232	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	344641816	0	0
T1	144150	144052	0	0
T2	7624	7508	0	0
T3	18409	18290	0	0
T4	121217	121070	0	0
T5	745	683	0	0
T6	1838	1777	0	0
T23	1527	1471	0	0
T24	1223	1148	0	0
T25	405798	387078	0	0
T26	826	751	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	64	98.46
Logical	65	64	98.46
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T25,T9

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T25,T9

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T113,T125
1	0	Covered	T18,T113,T125

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T25,T9
1	1	Covered	T18,T113,T125

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T113,T125
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T25,T9

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T3,T25,T9
1	Covered	T78,T39,T43

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T25,T9
1	0	Covered	T3,T25,T9
1	1	Covered	T3,T25,T9

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T25,T9

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T25,T9
1	1	Covered	T78,T39,T43

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T19
1	Covered	T78,T39,T43

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T25,T9
1	0	Covered	T3,T25,T9
1	1	Covered	T3,T25,T9

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T3,T25,T9
1	Covered	T3,T25,T9

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T25,T9
1	0	Covered	T3,T25,T9
1	1	Covered	T78,T39,T43

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T19
1	Covered	T78,T39,T43

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T3,T9,T17
1	Covered	T3,T25,T10

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T3,T25,T9
1	Covered	T3,T25,T9

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T3,T25,T9
1	Covered	T3,T25,T9

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T25,T9
1	1	Covered	T3,T25,T9

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T23
1	0	Covered	T3,T25,T10
1	1	Covered	T3,T25,T10

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T23
1	0	Covered	T3,T25,T10
1	1	Covered	T3,T25,T10

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T25,T9
1	1	0	Covered	T3,T25,T9
1	1	1	Covered	T3,T25,T9

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T25,T9

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T3,T25,T10
StCalcMask	237	Covered	T3,T25,T10
StCalcPlainEcc	215	Covered	T3,T25,T9
StDisabled	193	Covered	T5,T21,T10
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T3,T25,T9
StPostPack	218	Covered	T78,T39,T43
StPrePack	195	Covered	T78,T39,T43
StReqFlash	237	Covered	T3,T25,T9
StScrambleData	244	Covered	T3,T25,T10
StWaitFlash	270	Covered	T3,T25,T9

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T3,T25,T10
StCalcMask->StScrambleData	244	Covered	T3,T25,T10
StCalcPlainEcc->StCalcMask	237	Covered	T3,T25,T10
StCalcPlainEcc->StReqFlash	237	Covered	T3,T9,T17
StIdle->StDisabled	193	Covered	T5,T21,T10
StIdle->StPackData	197	Covered	T3,T25,T9
StIdle->StPrePack	195	Covered	T78,T39,T43
StPackData->StCalcPlainEcc	215	Covered	T3,T25,T9
StPackData->StPostPack	218	Covered	T78,T39,T43
StPostPack->StCalcPlainEcc	231	Covered	T78,T39,T43
StPrePack->StPackData	205	Covered	T78,T39,T43
StReqFlash->StIdle	273	Covered	T3,T25,T9
StReqFlash->StWaitFlash	270	Covered	T3,T25,T9
StScrambleData->StCalcEcc	252	Covered	T3,T25,T10
StWaitFlash->StIdle	280	Covered	T3,T25,T9

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T25,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T25,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T25,T9
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T25,T9
0	0	1	Covered	T3,T25,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T21,T10
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T78,T39,T43
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T9
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T78,T39,T43
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T19
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T9
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T78,T39,T43
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T3,T25,T9
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T3,T25,T9
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T78,T39,T43
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T19
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T25,T10
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T3,T9,T17
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T3,T25,T10
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T25,T10
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T25,T10
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T25,T10
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T10
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T3,T25,T9
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T3,T25,T9
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T3,T25,T9
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T3,T25,T9
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T25,T9
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T25,T9
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T21,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T3,T25,T9
0	0	1	-	-	Covered	T3,T25,T10
0	0	0	1	-	Covered	T3,T25,T10
0	0	0	0	1	Covered	T3,T25,T9
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T25,T9
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	345337277	1190610	0	0
PostPackRule_A	345337277	968	0	0
PrePackRule_A	345337277	677	0	0
WidthCheck_A	879	879	0	0
u_state_regs_A	345337277	344641816	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	1190610	0	0
T3	18409	13	0	0
T4	121217	0	0	0
T5	745	0	0	0
T6	1838	0	0	0
T9	208249	57	0	0
T10	0	33153	0	0
T12	2562	0	0	0
T17	0	1215	0	0
T23	1527	0	0	0
T24	1223	0	0	0
T25	405798	363	0	0
T26	826	0	0	0
T27	0	3	0	0
T33	0	367	0	0
T39	0	1	0	0
T43	0	6	0	0
T78	0	1	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	968	0	0
T7	3591	0	0	0
T13	0	25	0	0
T27	72672	2	0	0
T28	0	4	0	0
T31	3449	0	0	0
T33	239789	0	0	0
T39	137116	1	0	0
T43	71060	3	0	0
T66	3489	0	0	0
T67	0	6	0	0
T72	1283	0	0	0
T78	3600	1	0	0
T151	1096	0	0	0
T177	0	17	0	0
T218	0	1	0	0
T232	0	3	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	677	0	0
T7	3591	0	0	0
T13	0	17	0	0
T27	72672	1	0	0
T28	0	2	0	0
T31	3449	0	0	0
T33	239789	0	0	0
T39	137116	1	0	0
T43	71060	3	0	0
T66	3489	0	0	0
T72	1283	0	0	0
T78	3600	1	0	0
T151	1096	0	0	0
T177	0	9	0	0
T218	0	1	0	0
T232	0	2	0	0
T233	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345337277	344641816	0	0
T1	144150	144052	0	0
T2	7624	7508	0	0
T3	18409	18290	0	0
T4	121217	121070	0	0
T5	745	683	0	0
T6	1838	1777	0	0
T23	1527	1471	0	0
T24	1223	1148	0	0
T25	405798	387078	0	0
T26	826	751	0	0