Module Definition
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Module Instance : tb.dut.u_intr_prog_lvl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.61 90.00 44.44 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.61 90.00 44.44 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.73 97.12 86.40 98.44 100.00 41.67 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_intr_prog_empty

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.73 97.12 86.40 98.44 100.00 41.67 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_intr_rd_full

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.73 97.12 86.40 98.44 100.00 41.67 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_intr_rd_lvl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.73 97.12 86.40 98.44 100.00 41.67 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_intr_op_done

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.73 97.12 86.40 98.44 100.00 41.67 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_intr_corr_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.73 97.12 86.40 98.44 100.00 41.67 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Line Coverage for Module self-instances :
SCORELINE
86.94 90.00
tb.dut.u_intr_prog_empty

SCORELINE
78.61 90.00
tb.dut.u_intr_prog_lvl

SCORELINE
86.94 90.00
tb.dut.u_intr_rd_full

SCORELINE
86.94 90.00
tb.dut.u_intr_rd_lvl

Line No.TotalCoveredPercent
TOTAL10990.00
ALWAYS754375.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 2 2
76 1 2
MISSING_ELSE
81 1 1
83 1 1
88 1 1
95 1 1
96 1 1
98 1 1


Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Line Coverage for Module self-instances :
SCORELINE
93.75 100.00
tb.dut.u_intr_op_done

SCORELINE
93.75 100.00
tb.dut.u_intr_corr_err

Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Cond Coverage for Module self-instances :
SCORECOND
86.94 77.78
tb.dut.u_intr_prog_empty

SCORECOND
78.61 44.44
tb.dut.u_intr_prog_lvl

SCORECOND
86.94 77.78
tb.dut.u_intr_rd_full

SCORECOND
86.94 77.78
tb.dut.u_intr_rd_lvl

TotalCoveredPercent
Conditions9777.78
Logical9777.78
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT2,T4,T12
10CoveredT1,T2,T3
11CoveredT2,T4,T12

Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Cond Coverage for Module self-instances :
SCORECOND
93.75 75.00
tb.dut.u_intr_op_done

SCORECOND
93.75 75.00
tb.dut.u_intr_corr_err

TotalCoveredPercent
Conditions12975.00
Logical12975.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT2,T4,T12
10CoveredT1,T3,T25
11CoveredT2,T4,T12

Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Branch Coverage for Module self-instances :
SCOREBRANCH
86.94 80.00
tb.dut.u_intr_prog_empty

SCOREBRANCH
78.61 80.00
tb.dut.u_intr_prog_lvl

SCOREBRANCH
86.94 80.00
tb.dut.u_intr_rd_full

SCOREBRANCH
86.94 80.00
tb.dut.u_intr_rd_lvl

Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 75 3 2 66.67
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 76 if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Branch Coverage for Module self-instances :
SCOREBRANCH
93.75 100.00
tb.dut.u_intr_op_done

SCOREBRANCH
93.75 100.00
tb.dut.u_intr_corr_err

Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_intr_hw
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 5274 5274 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5274 5274 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T5 6 6 0 0
T6 6 6 0 0
T23 6 6 0 0
T24 6 6 0 0
T25 6 6 0 0
T26 6 6 0 0

Line Coverage for Instance : tb.dut.u_intr_prog_lvl
Line No.TotalCoveredPercent
TOTAL10990.00
ALWAYS754375.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 2 2
76 1 2
MISSING_ELSE
81 1 1
83 1 1
88 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.u_intr_prog_lvl
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT1,T2,T3

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T12,T59

Branch Coverage for Instance : tb.dut.u_intr_prog_lvl
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 75 3 2 66.67
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 76 if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_intr_prog_lvl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 879 879 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 879 879 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0

Line Coverage for Instance : tb.dut.u_intr_prog_empty
Line No.TotalCoveredPercent
TOTAL10990.00
ALWAYS754375.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 2 2
76 1 2
MISSING_ELSE
81 1 1
83 1 1
88 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.u_intr_prog_empty
TotalCoveredPercent
Conditions9777.78
Logical9777.78
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T3,T25
01Not Covered
10CoveredT1,T2,T3

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T3,T25
01Not Covered
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT12,T74,T47
10CoveredT1,T2,T3
11CoveredT2,T12,T59

Branch Coverage for Instance : tb.dut.u_intr_prog_empty
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 75 3 2 66.67
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 76 if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_intr_prog_empty
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 879 879 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 879 879 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0

Line Coverage for Instance : tb.dut.u_intr_rd_full
Line No.TotalCoveredPercent
TOTAL10990.00
ALWAYS754375.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 2 2
76 1 2
MISSING_ELSE
81 1 1
83 1 1
88 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.u_intr_rd_full
TotalCoveredPercent
Conditions9777.78
Logical9777.78
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T4,T79

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T4,T79

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT2,T4,T12
10CoveredT1,T79,T80
11CoveredT4,T14,T76

Branch Coverage for Instance : tb.dut.u_intr_rd_full
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 75 3 2 66.67
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 76 if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_intr_rd_full
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 879 879 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 879 879 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0

Line Coverage for Instance : tb.dut.u_intr_rd_lvl
Line No.TotalCoveredPercent
TOTAL10990.00
ALWAYS754375.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 2 2
76 1 2
MISSING_ELSE
81 1 1
83 1 1
88 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.u_intr_rd_lvl
TotalCoveredPercent
Conditions9777.78
Logical9777.78
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T4,T79

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T4,T79

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT2,T4,T12
10CoveredT1,T79,T80
11CoveredT4,T14,T15

Branch Coverage for Instance : tb.dut.u_intr_rd_lvl
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 75 3 2 66.67
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 76 if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_intr_rd_lvl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 879 879 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 879 879 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0

Line Coverage for Instance : tb.dut.u_intr_op_done
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.u_intr_op_done
TotalCoveredPercent
Conditions12975.00
Logical12975.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT2,T4,T12
10CoveredT1,T3,T25
11CoveredT2,T4,T12

Branch Coverage for Instance : tb.dut.u_intr_op_done
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_intr_op_done
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 879 879 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 879 879 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0

Line Coverage for Instance : tb.dut.u_intr_corr_err
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.u_intr_corr_err
TotalCoveredPercent
Conditions12975.00
Logical12975.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT74,T49,T50
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT74,T49,T50
10CoveredT74,T49,T50

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT2,T4,T12
10CoveredT49,T50,T81
11CoveredT74,T48,T75

Branch Coverage for Instance : tb.dut.u_intr_corr_err
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_intr_corr_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 879 879 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 879 879 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%