Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	97.92	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	95.83	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23401683	1		T1	57		T2	17595		T3	127615
full_word	7345906	1		T1	1		T2	4239		T3	18146

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30747259	1		T1	58		T2	21834		T3	145761
auto[TlIntgErrCmd]	105	1		T64	3		T66	8		T228	7
auto[TlIntgErrData]	120	1		T64	2		T66	7		T228	6
auto[TlIntgErrBoth]	105	1		T64	5		T66	5		T228	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26795536	1		T1	57		T2	17233		T3	127122
auto[1]	3952053	1		T1	1		T2	4601		T3	18639

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22830945	1		T1	57		T2	17225		T3	126187
auto[TlIntgErrNone]	partial	auto[1]	570435	1		T2	370		T3	1428		T25	1
auto[TlIntgErrNone]	full_word	auto[0]	3964434	1		T2	8		T3	935		T4	156
auto[TlIntgErrNone]	full_word	auto[1]	3381445	1		T1	1		T2	4231		T3	17211
auto[TlIntgErrCmd]	partial	auto[0]	39	1		T64	3		T66	1		T228	4
auto[TlIntgErrCmd]	partial	auto[1]	62	1		T66	7		T228	3		T259	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T345	1		T346	1		T347	1
auto[TlIntgErrData]	partial	auto[0]	57	1		T64	1		T66	3		T228	4
auto[TlIntgErrData]	partial	auto[1]	51	1		T64	1		T66	3		T259	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T228	1		T343	1		T348	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T66	1		T228	1		T259	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1		T64	3		T66	3		T228	3
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T64	2		T66	2		T228	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T259	1		T261	1		T282	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T282	1		T262	1		T342	2

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19475	1		T61	523		T63	1254		T64	9
full_word	3428117	1		T4	131		T7	41473		T17	16501

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3447276	1		T4	131		T7	41473		T17	16501
auto[TlIntgErrCmd]	103	1		T64	3		T66	7		T228	3
auto[TlIntgErrData]	114	1		T64	6		T66	6		T228	8
auto[TlIntgErrBoth]	99	1		T64	1		T66	6		T228	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3423032	1		T4	131		T7	41473		T17	16501
auto[1]	24560	1		T61	588		T63	1540		T64	2

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1156	1		T61	46		T63	69		T65	25
auto[TlIntgErrNone]	partial	auto[1]	18029	1		T61	477		T63	1185		T65	329
auto[TlIntgErrNone]	full_word	auto[0]	3421752	1		T4	131		T7	41473		T17	16501
auto[TlIntgErrNone]	full_word	auto[1]	6339	1		T61	111		T63	355		T65	77
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T64	2		T66	2		T228	1
auto[TlIntgErrCmd]	partial	auto[1]	57	1		T64	1		T66	5		T228	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T262	1		T258	1		T349	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T228	1		T262	1		T344	1
auto[TlIntgErrData]	partial	auto[0]	53	1		T64	4		T66	1		T228	3
auto[TlIntgErrData]	partial	auto[1]	52	1		T64	1		T66	4		T228	4
auto[TlIntgErrData]	full_word	auto[0]	3	1		T64	1		T66	1		T349	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T228	1		T258	1		T343	1
auto[TlIntgErrBoth]	partial	auto[0]	27	1		T64	1		T66	2		T228	4
auto[TlIntgErrBoth]	partial	auto[1]	66	1		T66	4		T228	5		T259	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T343	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T262	1		T343	1		T345	1