Unified Coverage Report :: Module :: prim_intr_hw

Module : prim_intr_hw

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.35	95.00	76.39			90.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_intr_prog_lvl	78.61	90.00	44.44			80.00	100.00
tb.dut.u_intr_prog_empty	86.94	90.00	77.78			80.00	100.00
tb.dut.u_intr_rd_full	86.94	90.00	77.78			80.00	100.00
tb.dut.u_intr_rd_lvl	86.94	90.00	77.78			80.00	100.00
tb.dut.u_intr_op_done	93.75	100.00	75.00			100.00	100.00
tb.dut.u_intr_corr_err	93.75	100.00	75.00			100.00	100.00

---

Module Instance : tb.dut.u_intr_prog_lvl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.61	90.00	44.44			80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.61	90.00	44.44			80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.89	97.12	87.20	98.44		100.00	41.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_prog_empty

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.94	90.00	77.78			80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.94	90.00	77.78			80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.89	97.12	87.20	98.44		100.00	41.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_rd_full

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.94	90.00	77.78			80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.94	90.00	77.78			80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.89	97.12	87.20	98.44		100.00	41.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_rd_lvl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.94	90.00	77.78			80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.94	90.00	77.78			80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.89	97.12	87.20	98.44		100.00	41.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_op_done

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.89	97.12	87.20	98.44		100.00	41.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_corr_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.89	97.12	87.20	98.44		100.00	41.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Line Coverage for Module self-instances :

SCORE	LINE
86.94	90.00

tb.dut.u_intr_prog_empty

SCORE	LINE
78.61	90.00

tb.dut.u_intr_prog_lvl

SCORE	LINE
86.94	90.00

tb.dut.u_intr_rd_full

SCORE	LINE
86.94	90.00

tb.dut.u_intr_rd_lvl

	Line No.	Total	Covered	Percent
TOTAL		10	9	90.00
ALWAYS	75	4	3	75.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	2	2
76	1	2
			MISSING_ELSE
81	1	1
83	1	1
88	1	1
95	1	1
96	1	1
98	1	1

---

Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Line Coverage for Module self-instances :

SCORE	LINE
93.75	100.00

tb.dut.u_intr_op_done

SCORE	LINE
93.75	100.00

tb.dut.u_intr_corr_err

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
64	1	1
67	1	1
69	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Cond Coverage for Module self-instances :

SCORE	COND
86.94	77.78

tb.dut.u_intr_prog_empty

SCORE	COND
78.61	44.44

tb.dut.u_intr_prog_lvl

SCORE	COND
86.94	77.78

tb.dut.u_intr_rd_full

SCORE	COND
86.94	77.78

tb.dut.u_intr_rd_lvl

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T75,T12

---

Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Cond Coverage for Module self-instances :

SCORE	COND
93.75	75.00

tb.dut.u_intr_op_done

SCORE	COND
93.75	75.00

tb.dut.u_intr_corr_err

	Total	Covered	Percent
Conditions	12	9	75.00
Logical	12	9	75.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T13,T14
1	0	Covered	T2,T3,T4
1	1	Covered	T5,T13,T14

---

Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Branch Coverage for Module self-instances :

SCORE	BRANCH
86.94	80.00

tb.dut.u_intr_prog_empty

SCORE	BRANCH
78.61	80.00

tb.dut.u_intr_prog_lvl

SCORE	BRANCH
86.94	80.00

tb.dut.u_intr_rd_full

SCORE	BRANCH
86.94	80.00

tb.dut.u_intr_rd_lvl

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	75	3	2	66.67
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	if ((!rst_ni))
-2-:	76	if (reg2hw_intr_test_qe_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Branch Coverage for Module self-instances :

SCORE	BRANCH
93.75	100.00

tb.dut.u_intr_op_done

SCORE	BRANCH
93.75	100.00

tb.dut.u_intr_corr_err

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_intr_hw

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	5238	5238	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5238	5238	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T6	6	6	0	0
T7	6	6	0	0
T11	6	6	0	0
T15	6	6	0	0
T17	6	6	0	0
T25	6	6	0	0

Line Coverage for Instance : tb.dut.u_intr_prog_lvl

	Line No.	Total	Covered	Percent
TOTAL		10	9	90.00
ALWAYS	75	4	3	75.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	2	2
76	1	2
			MISSING_ELSE
81	1	1
83	1	1
88	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_prog_lvl

	Total	Covered	Percent
Conditions	9	4	44.44
Logical	9	4	44.44
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T75,T12,T79

---

Branch Coverage for Instance : tb.dut.u_intr_prog_lvl

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	75	3	2	66.67
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	if ((!rst_ni))
-2-:	76	if (reg2hw_intr_test_qe_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_intr_prog_lvl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	873	873	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_prog_empty

	Line No.	Total	Covered	Percent
TOTAL		10	9	90.00
ALWAYS	75	4	3	75.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	2	2
76	1	2
			MISSING_ELSE
81	1	1
83	1	1
88	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_prog_empty

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T75,T12,T77
1	0	Covered	T1,T2,T3
1	1	Covered	T75,T12,T79

---

Branch Coverage for Instance : tb.dut.u_intr_prog_empty

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	75	3	2	66.67
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	if ((!rst_ni))
-2-:	76	if (reg2hw_intr_test_qe_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_intr_prog_empty

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	873	873	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_rd_full

	Line No.	Total	Covered	Percent
TOTAL		10	9	90.00
ALWAYS	75	4	3	75.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	2	2
76	1	2
			MISSING_ELSE
81	1	1
83	1	1
88	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_rd_full

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T39,T87,T88

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T39,T87,T88

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T13,T14
1	0	Covered	T39,T87,T88
1	1	Covered	T80,T81,T82

---

Branch Coverage for Instance : tb.dut.u_intr_rd_full

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	75	3	2	66.67
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	if ((!rst_ni))
-2-:	76	if (reg2hw_intr_test_qe_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_intr_rd_full

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	873	873	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_rd_lvl

	Line No.	Total	Covered	Percent
TOTAL		10	9	90.00
ALWAYS	75	4	3	75.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	2	2
76	1	2
			MISSING_ELSE
81	1	1
83	1	1
88	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_rd_lvl

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T5,T13,T39

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T5,T13,T39

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T13,T14
1	0	Covered	T39,T87,T88
1	1	Covered	T5,T13,T14

---

Branch Coverage for Instance : tb.dut.u_intr_rd_lvl

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	75	3	2	66.67
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	if ((!rst_ni))
-2-:	76	if (reg2hw_intr_test_qe_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_intr_rd_lvl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	873	873	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_op_done

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
64	1	1
67	1	1
69	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_op_done

	Total	Covered	Percent
Conditions	12	9	75.00
Logical	12	9	75.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T13,T14
1	0	Covered	T2,T3,T4
1	1	Covered	T5,T13,T14

---

Branch Coverage for Instance : tb.dut.u_intr_op_done

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_intr_op_done

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	873	873	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_corr_err

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
64	1	1
67	1	1
69	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_corr_err

	Total	Covered	Percent
Conditions	12	9	75.00
Logical	12	9	75.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T75,T45,T46
1	0	Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T75,T45,T46
1	0	Covered	T75,T45,T46

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T13,T14
1	0	Covered	T45,T46,T89
1	1	Covered	T75,T77,T78

---

Branch Coverage for Instance : tb.dut.u_intr_corr_err

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_intr_corr_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	873	873	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0