GPIO Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: `ac0bef2ce`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.420s	740.785us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.640s	1.162ms	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.640s	41.416us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	34.946us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.980s	159.177us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.800s	46.073us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.340s	130.438us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	34.946us	20	20	100.00
		gpio_csr_aliasing	0.800s	46.073us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.470s	75.334us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.350s	36.260us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.950s	59.240us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.470s	56.569us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.820s	445.689us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.760s	90.677us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.230s	843.571us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.890s	11.846ms	50	50	100.00
V2	full_random	gpio_full_random	1.100s	88.316us	50	50	100.00
V2	stress_all	gpio_stress_all	3.603m	38.384ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.640s	65.277us	50	50	100.00
V2	intr_test	gpio_intr_test	0.660s	17.963us	25	50	50.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.720s	147.232us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.720s	147.232us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	34.946us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	163.553us	20	20	100.00
		gpio_csr_aliasing	0.800s	46.073us	5	5	100.00
		gpio_csr_hw_reset	0.640s	41.416us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	34.946us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	163.553us	20	20	100.00
		gpio_csr_aliasing	0.800s	46.073us	5	5	100.00
		gpio_csr_hw_reset	0.640s	41.416us	5	5	100.00
V2		TOTAL			615	640	96.09
V2S	tl_intg_err	gpio_tl_intg_err	1.470s	212.995us	20	20	100.00
		gpio_sec_cm	0.950s	652.674us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.470s	212.995us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	40.256m	231.073ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			845	870	97.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	14	14	13	92.86
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.61	99.07	99.10	100.00	--	99.80	99.68	100.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:455) [gpio_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRgpio_reg_block.intr_state

has 25 failures:

Test gpio_intr_test has 25 failures.

0.gpio_intr_test.2088068808
Line 221, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_intr_test/latest/run.log

  UVM_ERROR @  18830531 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 1849867231 [0x6e42bbdf]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @  18830531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.gpio_intr_test.3073491142
Line 218, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_intr_test/latest/run.log

  UVM_ERROR @   1390417 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1395390126 [0x532bf6ae]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @   1390417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 23 more failures.